WO1985002039A2 - Microcomputer - Google Patents

Microcomputer

Info

Publication number
WO1985002039A2
WO1985002039A2 PCT/GB1984/000379 GB8400379W WO8502039A2 WO 1985002039 A2 WO1985002039 A2 WO 1985002039A2 GB 8400379 W GB8400379 W GB 8400379W WO 8502039 A2 WO8502039 A2 WO 8502039A2
Authority
WO
WIPO (PCT)
Prior art keywords
channels
data transmission
inputting
alternative
processes
Prior art date
Application number
PCT/GB1984/000379
Other languages
French (fr)
Other versions
WO1985002039A3 (en
Inventor
Michael David May
Roger Mark Shepherd
Original Assignee
Inmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inmos Ltd filed Critical Inmos Ltd
Publication of WO1985002039A2 publication Critical patent/WO1985002039A2/en
Publication of WO1985002039A3 publication Critical patent/WO1985002039A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/54Interprogram communication

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A microcomputer comprises memory (60) and a processor including a plurality of channels (70) to enable data transmission between concurrent processes. An inputting process may input data through one of a plurality of alternative input channels (70). Data transmission occurs when both processes are at corresponding stages in their programs. If an inputting process finds that no outputting process is yet ready on any of the alternative channels the inputting process may be descheduled and synchronisation achieved by special values located in locations (67) in a workspace (60) for the process.
PCT/GB1984/000379 1983-11-04 1984-11-02 Microcomputer WO1985002039A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB838329509A GB8329509D0 (en) 1983-11-04 1983-11-04 Computer
GB8329509 1983-11-04

Publications (2)

Publication Number Publication Date
WO1985002039A2 true WO1985002039A2 (en) 1985-05-09
WO1985002039A3 WO1985002039A3 (en) 1985-07-18

Family

ID=10551256

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/GB1984/000379 WO1985002039A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000378 WO1985002038A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000377 WO1985002037A2 (en) 1983-11-04 1984-11-02 Microcomputer

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/GB1984/000378 WO1985002038A2 (en) 1983-11-04 1984-11-02 Microcomputer
PCT/GB1984/000377 WO1985002037A2 (en) 1983-11-04 1984-11-02 Microcomputer

Country Status (6)

Country Link
US (3) US4758948A (en)
EP (3) EP0149311B1 (en)
JP (3) JP2664664B2 (en)
DE (3) DE3481946D1 (en)
GB (1) GB8329509D0 (en)
WO (3) WO1985002039A2 (en)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8521672D0 (en) * 1985-08-30 1985-10-02 Univ Southampton Data processing device
AU6244686A (en) * 1985-09-17 1987-03-19 Codex Corporation Multiple task control
US4853849A (en) * 1986-12-17 1989-08-01 Intel Corporation Multi-tasking register set mapping system which changes a register set pointer block bit during access instruction
US4965716A (en) * 1988-03-11 1990-10-23 International Business Machines Corporation Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a multiprogrammed data processor
US5193196A (en) * 1988-04-04 1993-03-09 Hitachi, Ltd. Process request arbitration system which preferentially maintains previously selected process request upon receipt of a subsequent request of identical priority
US4961140A (en) * 1988-06-29 1990-10-02 International Business Machines Corporation Apparatus and method for extending a parallel synchronous data and message bus
US5163156A (en) * 1988-07-27 1992-11-10 At&T Bell Laboratories Method for distributing messages through a mapping table which includes for each originating device a sequential list of corresponding destination devices
EP0378398B1 (en) * 1989-01-13 1996-07-24 International Business Machines Corporation Data processing system with means for detecting status of data processing device receiving commands
US5261099A (en) * 1989-08-24 1993-11-09 International Business Machines Corp. Synchronous communications scheduler allowing transient computing overloads using a request buffer
NL8902726A (en) * 1989-11-06 1991-06-03 Oce Nederland Bv METHOD AND APPARATUS FOR EDITING DATA FROM IMAGES
US5452452A (en) * 1990-06-11 1995-09-19 Cray Research, Inc. System having integrated dispatcher for self scheduling processors to execute multiple types of processes
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5469571A (en) * 1991-07-15 1995-11-21 Lynx Real-Time Systems, Inc. Operating system architecture using multiple priority light weight kernel task based interrupt handling
US5247675A (en) * 1991-08-09 1993-09-21 International Business Machines Corporation Preemptive and non-preemptive scheduling and execution of program threads in a multitasking operating system
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
EP0636256B1 (en) 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
DE69308548T2 (en) 1992-05-01 1997-06-12 Seiko Epson Corp DEVICE AND METHOD FOR COMPLETING THE COMMAND IN A SUPER-SCALAR PROCESSOR.
US5353420A (en) * 1992-08-10 1994-10-04 Intel Corporation Method and apparatus for decoding conditional jump instructions in a single clock in a computer processor
JP3644959B2 (en) 1992-09-29 2005-05-11 セイコーエプソン株式会社 Microprocessor system
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
DE69330889T2 (en) 1992-12-31 2002-03-28 Seiko Epson Corp System and method for changing register names
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5379428A (en) * 1993-02-01 1995-01-03 Belobox Systems, Inc. Hardware process scheduler and processor interrupter for parallel processing computer systems
US5859981A (en) * 1995-07-12 1999-01-12 Super P.C., L.L.C. Method for deadlock-free message passing in MIMD systems using routers and buffers
DE19653429C2 (en) * 1996-12-20 1998-10-15 Siemens Ag Method for checking the functionality of a computing unit
TW405090B (en) * 1997-04-04 2000-09-11 Ibm Predictive cache loading by program address discontinuity history
US6219776B1 (en) * 1998-03-10 2001-04-17 Billions Of Operations Per Second Merged array controller and processing element
KR100617228B1 (en) * 1999-03-19 2006-08-31 엘지전자 주식회사 method for implementation of transferring event in real-time operating system kernel
US7424712B1 (en) * 1999-04-30 2008-09-09 Sun Microsystems Inc System and method for controlling co-scheduling of processes of parallel program
US6442631B1 (en) 1999-05-07 2002-08-27 Compaq Information Technologies Group, L.P. Allocating system resources based upon priority
US6760337B1 (en) * 1999-08-17 2004-07-06 Conexant Systems, Inc. Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels
US6559783B1 (en) * 2000-08-16 2003-05-06 Microchip Technology Incorporated Programmable auto-converting analog to digital conversion module
US6772300B1 (en) * 2000-08-30 2004-08-03 Intel Corporation Method and apparatus for managing out of order memory transactions
US6751711B1 (en) * 2000-10-27 2004-06-15 Nortel Networks Limited Methods and systems for process rollback in a shared memory parallel processor computing environment
JP3610915B2 (en) * 2001-03-19 2005-01-19 株式会社デンソー Processing execution apparatus and program
US6874054B2 (en) * 2002-12-19 2005-03-29 Emulex Design & Manufacturing Corporation Direct memory access controller system with message-based programming
WO2006051004A2 (en) * 2004-11-11 2006-05-18 International Business Machines Corporation Concurrent flashing of processing units by means of network restructuring
US20060143415A1 (en) * 2004-12-29 2006-06-29 Uday Naik Managing shared memory access
US7386642B2 (en) * 2005-01-28 2008-06-10 Sony Computer Entertainment Inc. IO direct memory access system and method
US7680972B2 (en) * 2005-02-04 2010-03-16 Sony Computer Entertainment Inc. Micro interrupt handler
JP2006216042A (en) * 2005-02-04 2006-08-17 Sony Computer Entertainment Inc System and method for interruption processing
JP5079342B2 (en) * 2007-01-22 2012-11-21 ルネサスエレクトロニクス株式会社 Multiprocessor device
JP2009048306A (en) * 2007-08-15 2009-03-05 Tokyo Metropolitan Univ Parallel process architecture and parallel processor using the same
JP6029553B2 (en) * 2013-08-22 2016-11-24 日立オートモティブシステムズ株式会社 Vehicle control device
DE102017204894A1 (en) * 2017-03-23 2018-09-27 Airbus Operations Gmbh Passenger seat with an expandable seat element and passenger cabin area
DE102017204886A1 (en) 2017-03-23 2018-09-27 Airbus Operations Gmbh Passenger seat with a manually expandable seat element and passenger cabin area

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3564504A (en) * 1967-11-22 1971-02-16 Us Air Force Method and system for program linkage and communication mechanism for computers
GB1345950A (en) * 1970-12-22 1974-02-06 Int Standard Electric Corp Digital electric data processing system
US3805247A (en) * 1972-05-16 1974-04-16 Burroughs Corp Description driven microprogrammable multiprocessor system
FR2253420A5 (en) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
FR2253428A5 (en) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
US3978452A (en) * 1974-02-28 1976-08-31 Burroughs Corporation System and method for concurrent and pipeline processing employing a data driven network
FR2269150B1 (en) * 1974-04-25 1977-10-28 Honeywell Bull Soc Ind
US4060849A (en) * 1975-10-28 1977-11-29 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull Data input and output controller
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
US4047161A (en) * 1976-04-30 1977-09-06 International Business Machines Corporation Task management apparatus
DE2659662C3 (en) * 1976-12-30 1981-10-08 Ibm Deutschland Gmbh, 7000 Stuttgart Priority level controlled interrupt device
US4177513A (en) * 1977-07-08 1979-12-04 International Business Machines Corporation Task handling apparatus for a computer system
US4387427A (en) * 1978-12-21 1983-06-07 Intel Corporation Hardware scheduler/dispatcher for data processing system
US4318173A (en) * 1980-02-05 1982-03-02 The Bendix Corporation Scheduler for a multiple computer system
JPS57768A (en) * 1980-06-04 1982-01-05 Hitachi Ltd Message transmission and reception system between processor
JPS5798062A (en) * 1980-12-12 1982-06-18 Hitachi Ltd Communication system between processors
US4680698A (en) * 1982-11-26 1987-07-14 Inmos Limited High density ROM in separate isolation well on single with chip
JPS59146346A (en) * 1983-02-10 1984-08-22 Fujitsu Ltd Communication system between processes

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984004188A1 (en) * 1983-04-11 1984-10-25 Inmos Ltd Microcomputer with interprocess communication

Also Published As

Publication number Publication date
US4783734A (en) 1988-11-08
EP0145244A3 (en) 1985-09-25
EP0141660B1 (en) 1990-09-26
WO1985002037A2 (en) 1985-05-09
EP0149311A2 (en) 1985-07-24
WO1985002039A3 (en) 1985-07-18
EP0145244B1 (en) 1990-02-21
WO1985002038A2 (en) 1985-05-09
EP0145244A2 (en) 1985-06-19
EP0141660A3 (en) 1985-10-02
DE3483306D1 (en) 1990-10-31
GB8329509D0 (en) 1983-12-07
WO1985002037A3 (en) 1985-07-18
US4758948A (en) 1988-07-19
JPS61500385A (en) 1986-03-06
JP2664662B2 (en) 1997-10-15
JP2664664B2 (en) 1997-10-15
WO1985002038A3 (en) 1985-07-18
US4794526A (en) 1988-12-27
EP0149311B1 (en) 1990-04-11
EP0141660A2 (en) 1985-05-15
JPS61500387A (en) 1986-03-06
DE3481389D1 (en) 1990-03-29
DE3481946D1 (en) 1990-05-17
EP0149311A3 (en) 1985-09-25
JPS61500386A (en) 1986-03-06
JP2664663B2 (en) 1997-10-15

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Legal Events

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Designated state(s): JP US

CR1 Correction of entry in section i

Free format text: IN PAT.BUL.11/85,UNDER PUBLISHED REPLACE THE KIND OF DOCUMENT A1 BY A2

AK Designated states

Designated state(s): JP US