WO1985004780A1 - Multilayer hybrid integrated circuit - Google Patents
Multilayer hybrid integrated circuit Download PDFInfo
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- WO1985004780A1 WO1985004780A1 PCT/US1985/000422 US8500422W WO8504780A1 WO 1985004780 A1 WO1985004780 A1 WO 1985004780A1 US 8500422 W US8500422 W US 8500422W WO 8504780 A1 WO8504780 A1 WO 8504780A1
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- weight percent
- triazine
- acrylate
- metallized
- resin
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/027—Non-macromolecular photopolymerisable compounds having carbon-to-carbon double bonds, e.g. ethylenic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0133—Elastomeric or compliant polymer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S430/00—Radiation imagery chemistry: process, composition, or product thereof
- Y10S430/1053—Imaging affecting physical property or radiation sensitive material, or producing nonplanar or printing surface - process, composition, or product: radiation sensitive composition or product or process of making binder containing
- Y10S430/1055—Radiation sensitive composition or product or process of making
- Y10S430/114—Initiator containing
- Y10S430/12—Nitrogen compound containing
- Y10S430/121—Nitrogen in heterocyclic ring
Definitions
- This invention relates to multilayer hybrid integrated circuits having novel dielectric layer employed as part of the circuit.
- the polymer layer must act as a dielectric material between layers containing thin film circuitry and must meet many other stringent requirements including a high T g , a high thermal stability and hybrid process compatibility. It would also be preferred if such a polymeric material were photodefinable.
- a multilayer circuit device comprising a substrate having a metallized pattern thereon and a plurality of polymeric dielectric film layers each having a metallized circuit pattern thereon with metallized microvias interconnecting the metallized patterns of one layer with that of at least one other metallized layer thereunder, said polymeric dielectric layer being formed from a photodefinable triazine base mixture including a photosensitive acrylate moiety.
- the Figure is a cross-sectional elevational view representing processing steps, A to E, in forming a device in accordance with the invention.
- DETAILED DESCRIPTION It should be understood that the novel device as summarized above is suitable for use as a multilayer printed circuit board employing substrates which are commonly used and are well known in the printed circuit board industry. Also, because of the characteristics of the triazine based dielectric layer employed, the device is especially suited for use in what is known as a multilayer hybrid integrated circuit device generally employing a ceramic substrate.
- a multilayer hybrid integrated circuit must be capable of employing a high number of I/O pin-out devices with high speed interconnections. Due to the heat developed and the electrical requirements, minimum requirements for the dielectric material employed to separate conductor layers include a glass transition temperature (T_) of at least 140°C and good thermal stability to about 220°C, a dielectric constant of no greater than 3.5 and preferably, the material should be capable of being imaged by means of actinic radiation so as to be able to achieve fine line features and an aspect ratio approaching 1.
- T_ glass transition temperature
- the dielectric materials must be tough enough to withstand thermal cycling specifications with severe mismatch in dimensional stability between the ceramic substrates and the dielectric materials; the dielectric must be compatible with typical ceramic resistors and conductors under accelerated life testing and the surface of the dielectric must be metallizible so as to form at an adherent circuit pattern thereon.
- the dielectric material must have chemical resistance to all chemicals used in further processing steps and should be in a form that can be coated reproducibly and efficiently.
- the polymeric dielectric material must also have good high voltage breakdown characteristics and be compatible with all other components and materials employed. Preferably, for commercial purposes, good shelf stability and shelf life of the uncured polymer is required.
- polymeric dielectric materials meeting these requirements were not available.
- a polymeric mixture having a triazine resin as its primary constituent and including a photosensitive acrylate moiety crosslinking agent can be used to achieve the necessary " goals.
- the acrylate moiety can be on a separate compound or on the trizine itself.
- a suitable polymeric dielectric formulation giving the ranges of its constituents in weight percent is as follows: triazine, 40-65%; rubber resin, 0-30%; an epoxy-acrylate hybrid resin or individual epoxy and acrylate resins totaling from 0- 50%; a hardener, 0-12%; a crosslinking agent, 0-8%; a coupling agent, 0-5%; and a photoinitiator, 1/2-3%.
- the preferred rubber resins are acrylonitrile butadiene resins. It is preferred that a hybrid epoxy- acrylate resin be employed rather than individual separate epoxy resin and acrylate resin. Such hybrid resin may be epoxy terminated or vinyl terminated. For example, the half acrylate of the diglycidyl ether of bisphenol-A is suitable. A particularly suitable hardener is N- vinylpyrrolidone. Further, a particularly suitable crosslinking agent is trimethylolpropanetriacrylate. Also a particularly suitable coupling agent to enhance the adhesion of the polymeric dielectric material to the underlying material is a silane coupling agent such as glycidoxypropyltrimethoxy-silane.
- Coupling agents and in particular silane coupling agents, are well known in the art for enhancing adhesion between dissimilar layers.
- a suitable photoinitiator is 2,2-dimethoxy-2- phenylacetophenone.
- Such additives are generally included, if desired, in amounts of up to about 1%.
- Generally preferred formulations of the triazine mixture are as follows:
- Suitable photodefinable resin mixtures utilized to form the polymeric dielectric are as follows:
- FIG. 1A shows the bare substrate 10 such as an alumina ceramic substrate.
- FIG. IB is a representation of the substrate 10 after a conductor pattern 12 has been placed on one surface thereof.
- This metallized pattern can be formed by any of the well known techniques including thin film technology, thick film technology, vacuum evaporation and electroless plating techniques.
- the layer is shown to be patterned to form a circuit one may employ a blanket metallized layer which may be used as a ground plane or power plane for the devices to be attached.
- FIG. 1A shows the bare substrate 10 such as an alumina ceramic substrate.
- FIG. IB is a representation of the substrate 10 after a conductor pattern 12 has been placed on one surface thereof.
- This metallized pattern can be formed by any of the well known techniques including thin film technology, thick film technology, vacuum evaporation and electroless plating techniques.
- the layer is shown to be patterned to form a circuit one may employ a blanket metallized layer which may be used as a ground plane or power
- IC depicts the substate 10 and first metallized layer 12 with a photodefinable dielectric 14 applied thereover.
- This dielectric 14 may be applied by any of the well known techniques including screen printing, brushing, spraying, dipping or the like.
- the photodefinable dielectric 14 is subjected to actinic radiation so as to define microvias 16 which, upon development, are formed therethrough.
- These microvias 16 allow additional metallization 18 as shown in FIG. 1E to form a contact between adjacent metallized layers. In this way, any desired portions of a top metallized layer may be made to electrically contact any lower metallized layer.
- Steps IC to IE can be repeated to build as many levels as needed or desired.
- Discrete devices such as integrated circuit chips, resistors, capacitors or the like can be • mounte»d such as by surface mounting techniques or any other available techniques known in the art to any of the metallized layers or preferentially to the top layer.
- a complete hybrid integrated circuit package is formed.
- the polymeric dielectric material should have the property requirements tabulated hereinbelow. Where, however, the use is not so stringent and a high number of I/O pin counts is not necessary and lower power is to be used, the requirements may be relaxed.
- the various requirements and the performance of the photodefinable triazine mixtures as set forth herein with respect to those requirements are given in the table below. Specific Material Requirements
- EXAMPLE IV This example sets forth the essential steps in preparing a multilayer integrated circuit employing one of the novel triazine mixtures as the photosensitive dielectric layer.
- a substrate is first sputter metallized to form a very thin base metal layer thereon.
- a photoresist such as Dupont Riston is then applied to the surface and the Riston is exposed and developed so as to form an image of the desired conductor pattern thereon.
- the exposed metallized layer is then electroplated such as with copper followed by nickel and gold and thereafter the Riston is stripped from the surface and the substrate is etched so as to remove the initially applied sputtered layer.
- the photodefinable dielectric triazine mixture is applied to the surface of the substrate by any of the known coating techniques, e.g., spray coating and is warmed so as to prevent bubble formation.
- the triazine mixture is then imaged by exposing to actinic radiation in a desired pattern and then developed so as to create microvias in the triazine dielectric layer.
- the dielectric is cured, e.g., by heating at temperatures from 100°C to 210°C.
- the surface of the dielectric layer is then treated such as by means of an argon etch so as to enhance the adhesion of that surface for subsequent metallization.
- a metal layer is sputtered onto the surface of the triazine dielectric layer, another layer of Riston is applied over the sputtered layer and the Riston is imaged in a desired pattern and a second metallization layer is built up by electroplating techniques.
- the Riston is thereafter stripped such as with methylene chloride and the underlying thin sputtered metal layer over which there is no electroplate is removed by etching.
- circuit devices such as capacitors, resistors and the like can be mounted or formed so as to interconnect with the top conductive layer or pattern. Further, where desired, the pattern may include a ground plane or power plane or both.
Abstract
A multilayer circuit device comprises a substrate having a plurality of metallized patterns (e.g., 12, 18) thereon said patterns being separated by a photodefined polymeric dielectric film (14) formed from a polymeric photodefinable triazine base mixture including a photosensitive acrylate moiety. The various circuit patterns are interconnected by means of microvias (16) through the polymeric film or film layers.
Description
MULTILAYER HYBRID INTEGRATED CIRCUIT
TECHNICAL FIELD
This invention relates to multilayer hybrid integrated circuits having novel dielectric layer employed as part of the circuit. BACKGROUND OF THE INVENTION
In the evolution of hybrid integrated circuits for switching systems and high performance processes as well as other electronic devices one of the most critical system packaging needs is the capability of utilizing effectively high I/O pin-out devices with high speed interconnections. To meet this goal multilayer ceramic hybrid integrated circuits have been developed. However, the currently available multilayer ceramic circuits require a complex manufacturing system and are relatively expensive. Consequently, in order to meet the packaging needs of such hybrid integrated circuits while retaining quality, reliability and performance demands, especially in conjunction with the use of very large scale integrated circuit chips, in a cost competitive package, further improvements are necessary.
To meet this goal, I believe that a multilayer polymer hybrid integrated circuit configuration is one approach to solving the problem. The polymer layer must act as a dielectric material between layers containing thin film circuitry and must meet many other stringent requirements including a high Tg, a high thermal stability and hybrid process compatibility. It would also be preferred if such a polymeric material were photodefinable. SUMMARY OF THE INVENTION
A multilayer circuit device comprising a substrate having a metallized pattern thereon and a plurality of polymeric dielectric film layers each having a metallized circuit pattern thereon with metallized microvias interconnecting the metallized patterns of one layer with
that of at least one other metallized layer thereunder, said polymeric dielectric layer being formed from a photodefinable triazine base mixture including a photosensitive acrylate moiety. BRIEF DESCRIPTION OF THE DRAWINGS
The Figure is a cross-sectional elevational view representing processing steps, A to E, in forming a device in accordance with the invention. DETAILED DESCRIPTION It should be understood that the novel device as summarized above is suitable for use as a multilayer printed circuit board employing substrates which are commonly used and are well known in the printed circuit board industry. Also, because of the characteristics of the triazine based dielectric layer employed, the device is especially suited for use in what is known as a multilayer hybrid integrated circuit device generally employing a ceramic substrate.
To meet the requirements of advancing technology involving hybrid integrated circuits for switching systems and high performance processes, a multilayer hybrid integrated circuit must be capable of employing a high number of I/O pin-out devices with high speed interconnections. Due to the heat developed and the electrical requirements, minimum requirements for the dielectric material employed to separate conductor layers include a glass transition temperature (T_) of at least 140°C and good thermal stability to about 220°C, a dielectric constant of no greater than 3.5 and preferably, the material should be capable of being imaged by means of actinic radiation so as to be able to achieve fine line features and an aspect ratio approaching 1. In addition, the dielectric materials must be tough enough to withstand thermal cycling specifications with severe mismatch in dimensional stability between the ceramic substrates and the dielectric materials; the dielectric must be compatible with typical ceramic resistors and conductors under
accelerated life testing and the surface of the dielectric must be metallizible so as to form at an adherent circuit pattern thereon. In addition, the dielectric material must have chemical resistance to all chemicals used in further processing steps and should be in a form that can be coated reproducibly and efficiently. The polymeric dielectric material must also have good high voltage breakdown characteristics and be compatible with all other components and materials employed. Preferably, for commercial purposes, good shelf stability and shelf life of the uncured polymer is required. Heretofore, polymeric dielectric materials meeting these requirements were not available.
In accordance with the present invention, a polymeric mixture having a triazine resin as its primary constituent and including a photosensitive acrylate moiety crosslinking agent, can be used to achieve the necessary" goals. The acrylate moiety can be on a separate compound or on the trizine itself. More particularly, a suitable polymeric dielectric formulation giving the ranges of its constituents in weight percent is as follows: triazine, 40-65%; rubber resin, 0-30%; an epoxy-acrylate hybrid resin or individual epoxy and acrylate resins totaling from 0- 50%; a hardener, 0-12%; a crosslinking agent, 0-8%; a coupling agent, 0-5%; and a photoinitiator, 1/2-3%.
The preferred rubber resins are acrylonitrile butadiene resins. It is preferred that a hybrid epoxy- acrylate resin be employed rather than individual separate epoxy resin and acrylate resin. Such hybrid resin may be epoxy terminated or vinyl terminated. For example, the half acrylate of the diglycidyl ether of bisphenol-A is suitable. A particularly suitable hardener is N- vinylpyrrolidone. Further, a particularly suitable crosslinking agent is trimethylolpropanetriacrylate. Also a particularly suitable coupling agent to enhance the adhesion of the polymeric dielectric material to the underlying material is a silane coupling agent such as
glycidoxypropyltrimethoxy-silane. Coupling agents, and in particular silane coupling agents, are well known in the art for enhancing adhesion between dissimilar layers. A suitable photoinitiator is 2,2-dimethoxy-2- phenylacetophenone. In addition to the above, one may also add small amounts of pigment, surfactant and copper chelate thermal stabilizer, e.g., copper benzylacetonate. Such additives are generally included, if desired, in amounts of up to about 1%. Generally preferred formulations of the triazine mixture are as follows:
(A) triazine 50-60 weight percent; epoxy acrylate hybrid 20-30 weight percent, hardener 5-12 weight percent, crosslinking agent 2-6 weight percent, coupling agent 2-5 weight percent, photoinitiator 1-3 weight percent; or
(B) triazine 50—60 weight percent; acrylated rubber 10-25 weight percent, epoxy acrylate hybrid 5-15 weight percent, hardener, crosslinking agent and photoinitiator as in (A); or (C) triazine 50-55 weight percent; acrylated rubber 20-30 weight percent and the remainder of the ingredients as in (B) plus pigment, surfactant and stabilizer up to 1 weight percent.
More specific examples of suitable photodefinable resin mixtures utilized to form the polymeric dielectric are as follows:
EXAMPLE I Component Weight percent
Triazine 56%
Half acrylate of the diglycidyl ether of bisphenol-A
(Celanese) 25%
N-vinylpyrrolidone 9%
Trimethylolpropanetriacrylate 4%
Glycidoxypropyltrimethoxysilane 4%
2-2-dimethoxy-2-phenylacetophenone 2%
EXAMPLE II
Component Weight Percent
Triazine 52%
Acrylated acrylonitrile butadiene rubber 16%
Half acrylate of the diglycidyl ether of bisphenol-A 9%
N-vinylpyrrolidone 9%
Epoxy propylacrylate 3.5%
Trimethylolpropanetriacrylate 4%
Glycidoxypropyltrimethoxysilane 4.5%
2,2-dimethoxy-2-phenylacetophenone 2%
EXAMPLE III
The basic formulation of this example is as follows:
Component Weight percent
Triazine 50%
Acrylated acrylonitrile butadiene rubber 26%
Half acrylate of the diglycidyl ether of bisphenol-A 9%
N-vinylpyrrόlidone 9%
Trimethylolpropanetriacrylate 4%
Glycidoxypropyltrimethoxysilane 2%
Added to this basic formula is the following:
2r2-dimethoxy-2-phenylacetophenone 2%
Magenta pigment 0.5%
Surfactant 0.2%
Copper benzyl acetonate 0.5%
The various photodefinable triazine resin mixtures as set above are employed, as previously indicated, in the manufacture of multilayer circuit devices such as multilayer hybrid integrated circuits. A typical multilayer fabrication process is shown with reference to FIG. 1 A-E. FIG. 1A shows the bare substrate 10 such as an alumina ceramic substrate. FIG. IB is a representation of the substrate 10 after a conductor pattern 12 has been placed on one surface thereof. This metallized pattern can be formed by any of the well known techniques including thin film technology, thick film technology, vacuum evaporation and electroless plating techniques. Further, while the layer is shown to be patterned to form a circuit one may employ a blanket metallized layer which may be used
as a ground plane or power plane for the devices to be attached. FIG. IC depicts the substate 10 and first metallized layer 12 with a photodefinable dielectric 14 applied thereover. This dielectric 14 may be applied by any of the well known techniques including screen printing, brushing, spraying, dipping or the like. Subsequent to application of the photodefinable dielectric 14, as shown in FIG. ID, the photodefinable dielectric 14 is subjected to actinic radiation so as to define microvias 16 which, upon development, are formed therethrough. These microvias 16 allow additional metallization 18 as shown in FIG. 1E to form a contact between adjacent metallized layers. In this way, any desired portions of a top metallized layer may be made to electrically contact any lower metallized layer. Steps IC to IE can be repeated to build as many levels as needed or desired. Discrete devices such as integrated circuit chips, resistors, capacitors or the like can be • mounte»d such as by surface mounting techniques or any other available techniques known in the art to any of the metallized layers or preferentially to the top layer. Upon completion, a complete hybrid integrated circuit package is formed. In order to achieve a commercially feasible hybrid integrated circuit for high density packaging of integrated circuit devices and a large number of I/O pin counts, the polymeric dielectric material should have the property requirements tabulated hereinbelow. Where, however, the use is not so stringent and a high number of I/O pin counts is not necessary and lower power is to be used, the requirements may be relaxed. The various requirements and the performance of the photodefinable triazine mixtures as set forth herein with respect to those requirements are given in the table below.
Specific Material Requirements
Photodefined
Triazine
Parameter Requirement Performance
Tg >130°C 150-190°C
Thermal stability
Long term 100°C 180°C
Short term 125°C 210°C
Spikes 300°C-10-15 sec. Passes
Dielectric constant <4.0 3.4-3.6
Resistor compatibility
Thin film Yes Yes
-3 -3
Via-resolution 7.6x10 cm 7.6x10 cm
(3 mil) minimum (3 mil) min.
Chemical resistance Not sensitive to Passes any of the process chemicals
Leakage current <1 micro amp <1 micro amp
Thermal cycle 5 cycles Pass
140°C-40°C
EXAMPLE IV This example sets forth the essential steps in preparing a multilayer integrated circuit employing one of the novel triazine mixtures as the photosensitive dielectric layer. In accordance with this process, which is just one example of many variations of processes which can be used for preparing a multilayer integrated circuit
employing the novel photodefinable dielectric, a substrate is first sputter metallized to form a very thin base metal layer thereon. A photoresist such as Dupont Riston is then applied to the surface and the Riston is exposed and developed so as to form an image of the desired conductor pattern thereon. The exposed metallized layer is then electroplated such as with copper followed by nickel and gold and thereafter the Riston is stripped from the surface and the substrate is etched so as to remove the initially applied sputtered layer. Thereafter the photodefinable dielectric triazine mixture is applied to the surface of the substrate by any of the known coating techniques, e.g., spray coating and is warmed so as to prevent bubble formation. The triazine mixture is then imaged by exposing to actinic radiation in a desired pattern and then developed so as to create microvias in the triazine dielectric layer. The dielectric is cured, e.g., by heating at temperatures from 100°C to 210°C. Preferably, the surface of the dielectric layer is then treated such as by means of an argon etch so as to enhance the adhesion of that surface for subsequent metallization. Thereafter a metal layer is sputtered onto the surface of the triazine dielectric layer, another layer of Riston is applied over the sputtered layer and the Riston is imaged in a desired pattern and a second metallization layer is built up by electroplating techniques. The Riston is thereafter stripped such as with methylene chloride and the underlying thin sputtered metal layer over which there is no electroplate is removed by etching. By this technique, interconnections between the first and second pattern layers of electroplated conductors are made through the microvias in the triazine dielectric layer. These steps can then be repeated as many times as required to build as many layers as is necessary. Also interconnections can be made between any lower and any upper layer skipping any middle layer if desired. Such techniques would be obvious to one skilled in the art. Subsequent to completing the
last layer, circuit devices such as capacitors, resistors and the like can be mounted or formed so as to interconnect with the top conductive layer or pattern. Further, where desired, the pattern may include a ground plane or power plane or both.
The utilization of these materials will also be important in other circuit material applications, such as encapsulants, cover coats and for single polymer layer circuits.
Claims
1. A multilayer cirucit device comprising a substrate having a metallized pattern thereon and a plurality of polymeric dielectric film layers each having a metallized circuit pattern thereon with metallized microvias interconnecting the metallized patterns of one layer with that of at least one other metallized layer thereunder,
CHARACTERIZED IN THAT said polymeric dielectric layer being formed from a photodefinable triazine base mixture including a photosensitive acrylate moiety.
2. The device according to claim 1, CHARACTERIZED IN THAT the triazine mixture comprises 40 to 65 weight percent triazine, 0 to 30 weight percent rubber resin, 0 to 50 weight percent of a member of a group consisting of an epoxy acrylate hybrid resin and a combination of an epoxy resin and an acrylate resin, JO to 12 weight percent of a hardener, 0 to 8 weight percent of a crosslinking agent, 0 to 5 weight percent of a coupling agent and 1/2 to 3 weight percent of a photoinitiator.
3. The device according to claim 2, CHARACTERIZED IN THAT the rubber resin is an acrylonitrile butadiene rubber, the epoxy and acrylate is in the form of a hybrid epoxy-acrylate resin which is carboxy or vinyl terminated and the coupling agent is a silane coupling agent.
4. The device according to claim 3, CHARACTERIZED BY including N-vinylpyrrolidone as the hardener, and 2,2-dimethoxy-2-phenylacetophenone as the photoinitiator.
5. The device according to claim 2, CHARACTERIZED BY including a surfactant and a copper chelate thermostabilizer.
6. The device according to claim 1, CHARACTERIZED IN THAT the triazine mixture comprises: triazine - 50-60 weight percent; half acrylate of the diglycidyl ether of bisphenol-A - 20-30 weight percent;
N-vinylpyrrolidone - 5-12 weight percent; trimethylolpropanetriacrylate - 2-6 weight percent; glycidoxypropyltrimethoxysilane - 2-5 weight percent; and
2,2-dimethoxy-2-phenylacetophenone - 1-3 weight percent.
7. The device according to claim 1, CHARACTERIZED IN THAT the triazine mixture comprises: triazine - 50-60 weight percent; acrylated acrylonitrile butadiene rubber - 10-25 weight perce*nt; half acrylate of the diglycidyl ether of bisphenol-A - 5-15 weight percent;
N-vinylpyrrolidone - 5-12 weight percent; epoxy propylacrylate - 1-5 weight percent; trimethylolpropanetriacrylate - 2-6 weight percent; glycidoxypropyltrimethoxysilane - 2-5 weight percent; and
2,2-dimethoxy-2-phenylacetophenone - 1-3 weight percent.
8. The device according to claim 1,
CHARACTERIZED IN THAT the triazine mixture comprises: triazine - 50-55 weight percent; acrylated acrylonitrile butadiene rubber - 20-30 weight percent; half acrylate of the diglycidyl ether of bisphenol-A - 5-15 weight percent;
N-vinylpyrrolidone - 5-12 weight percent; trimethylolpropanetriacrylate - 2-4 weight percent; glycidoxypropyltrimethoxysilane - 1-5 weight percent;
2,2-dimethoxy-2-phenylacetophenone - 1-3 weight percent; pigment - 0.25-1 weight percent; surfactant - 0.1-1 weight percent; and stabilizer - 0.2-1 weight percent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE8585901751T DE3566767D1 (en) | 1984-04-06 | 1985-03-12 | Multilayer hybrid integrated circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/597,626 US4554229A (en) | 1984-04-06 | 1984-04-06 | Multilayer hybrid integrated circuit |
US597,626 | 1984-04-06 |
Publications (1)
Publication Number | Publication Date |
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WO1985004780A1 true WO1985004780A1 (en) | 1985-10-24 |
Family
ID=24392283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/US1985/000422 WO1985004780A1 (en) | 1984-04-06 | 1985-03-12 | Multilayer hybrid integrated circuit |
Country Status (6)
Country | Link |
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US (1) | US4554229A (en) |
EP (1) | EP0176555B1 (en) |
JP (1) | JPS61501806A (en) |
CA (1) | CA1254789A (en) |
DE (1) | DE3566767D1 (en) |
WO (1) | WO1985004780A1 (en) |
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Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4601972A (en) * | 1984-04-06 | 1986-07-22 | At&T Technologies, Inc. | Photodefinable triazine based composition |
US4600736A (en) * | 1985-03-11 | 1986-07-15 | Phillips Petroleum Company | Pigment concentrates for resins |
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Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3397204A (en) * | 1962-05-07 | 1968-08-13 | Monsanto Co | Production of halohydrocarbyloxysym-triazines |
US3632861A (en) * | 1969-03-19 | 1972-01-04 | American Cyanamid Co | Vinyl ester resins from epoxides and isomerized hydroxy alkyl acrylates-aleic anhydride reaction product |
US3900594A (en) * | 1971-12-17 | 1975-08-19 | Grace W R & Co | Photocurable triazine containing polyene-polythiol lacquer composition |
US4060656A (en) * | 1973-04-02 | 1977-11-29 | Teijin Limited | Support for photosensitive resin |
US4054483A (en) * | 1976-12-22 | 1977-10-18 | E. I. Du Pont De Nemours And Company | Additives process for producing plated holes in printed circuit elements |
JPS5651735A (en) * | 1979-10-03 | 1981-05-09 | Asahi Chem Ind Co Ltd | Photoreactive composition |
US4329384A (en) * | 1980-02-14 | 1982-05-11 | Minnesota Mining And Manufacturing Company | Pressure-sensitive adhesive tape produced from photoactive mixture of acrylic monomers and polynuclear-chromophore-substituted halomethyl-2-triazine |
US4357219A (en) * | 1980-06-27 | 1982-11-02 | Westinghouse Electric Corp. | Solventless UV cured thermosetting cement coat |
JPS5797970U (en) * | 1980-12-08 | 1982-06-16 | ||
US4456712A (en) * | 1982-06-14 | 1984-06-26 | International Business Machines Corporation | Bismaleimide triazine composition |
-
1984
- 1984-04-06 US US06/597,626 patent/US4554229A/en not_active Expired - Lifetime
-
1985
- 1985-03-12 WO PCT/US1985/000422 patent/WO1985004780A1/en active IP Right Grant
- 1985-03-12 JP JP60501373A patent/JPS61501806A/en active Granted
- 1985-03-12 DE DE8585901751T patent/DE3566767D1/en not_active Expired
- 1985-03-12 EP EP85901751A patent/EP0176555B1/en not_active Expired
- 1985-03-25 CA CA000477379A patent/CA1254789A/en not_active Expired
Non-Patent Citations (2)
Title |
---|
Electronic Components, 31st Conference, 11-13 May 1981, (Atlanta, US) J.R. GASKKILL et al.: "Kovar Large area Hybrid Module" see page 456 - 464 * |
IBM Technical Disclosure Bulletin, Volume 8, Nr. 11, (New-York, US) April 1966 M.M. HADDAD: "Additive Multilayer Circuit" page 1482, see page 1482 * |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0211180A2 (en) * | 1985-08-02 | 1987-02-25 | Shipley Company Inc. | Method for manufacture of multilayer circuit board |
EP0211180A3 (en) * | 1985-08-02 | 1989-08-09 | Shipley Company Inc. | Method for manufacture of multilayer circuit board |
WO1988005252A1 (en) * | 1987-01-12 | 1988-07-14 | Allied Corporation | Method for the manufacture of multilayer printed circuit boards |
EP0281807A2 (en) * | 1987-03-09 | 1988-09-14 | Siemens Nixdorf Informationssysteme Aktiengesellschaft | Additive technique for multilayer wirings |
EP0281807A3 (en) * | 1987-03-09 | 1990-06-27 | Siemens Aktiengesellschaft | Additive technique for multilayer wirings |
US5552503A (en) * | 1993-12-22 | 1996-09-03 | At&T Corp. | Photodefinable dielectric layers comprising poly(aromatic diacetylenes) |
EP0659782A1 (en) * | 1993-12-22 | 1995-06-28 | AT&T Corp. | Photodefinable dielectric layers |
EP0735809A2 (en) * | 1995-03-28 | 1996-10-02 | Macdermid Incorporated | Photodefinable dielectric composition useful in the manufacture of printed circuits |
EP0735809A3 (en) * | 1995-03-28 | 1997-06-04 | Macdermid Inc | Photodefinable dielectric composition useful in the manufacture of printed circuits |
EP1067406A1 (en) * | 1999-07-01 | 2001-01-10 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Thermosetting plastics as substrate materials for optical systems |
WO2001002878A1 (en) * | 1999-07-01 | 2001-01-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Thermosetting plastics as substrate materials for optical systems |
EP1359792A1 (en) * | 2002-04-22 | 2003-11-05 | Hueck Folien GmbH | Substrate with non-visible electrically conducting layers |
WO2019065129A1 (en) * | 2017-09-27 | 2019-04-04 | 富士フイルム株式会社 | Photosensitive resin composition, flexographic printing plate precursor, and flexographic printing plate |
Also Published As
Publication number | Publication date |
---|---|
EP0176555A1 (en) | 1986-04-09 |
US4554229A (en) | 1985-11-19 |
EP0176555B1 (en) | 1988-12-07 |
DE3566767D1 (en) | 1989-01-12 |
JPH0447475B2 (en) | 1992-08-04 |
JPS61501806A (en) | 1986-08-21 |
CA1254789A (en) | 1989-05-30 |
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