WO1986006540A2 - Memory cell for use in a read only memory - Google Patents
Memory cell for use in a read only memory Download PDFInfo
- Publication number
- WO1986006540A2 WO1986006540A2 PCT/US1986/000775 US8600775W WO8606540A2 WO 1986006540 A2 WO1986006540 A2 WO 1986006540A2 US 8600775 W US8600775 W US 8600775W WO 8606540 A2 WO8606540 A2 WO 8606540A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- threshold
- devices
- gate
- alterable
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Definitions
- This invention relates to memory devices of the kind including a memory cell comprising a first, alterable threshold memory device having a channel structure and a charge storage memory gate which includes a ga h electrode and a dielectric structure between the gate electrode and the channel structure, the memory gate structure having charge storage capability suitable for controlling the device threshold to a first, relatively low level and a second, relatively high level.
- the invention has a particular application to memory devices configured as a read-only memory.
- CMOS Stacked Transistors CMOS (ST-MOS), an NMOS Technology Modified to CMOS, IEEE Transactions on Electron Devices, Vol. ED-29, pp. 585-589 (1982) discloses a stacked CMOS inverter configuration.
- ST-MOS Stacked Transistors CMOS
- NMOS NMOS Technology Modified to CMOS
- IEEE Transactions on Electron Devices, Vol. ED-29, pp. 585-589 (1982) discloses a stacked CMOS inverter configuration.
- the Colinge et al. structure starts with a conventional NMOS structure formed in a silicon substrate 10, uses the NMOS gate 11 for both transistors, and adds a selectively implanted, laser-recrystallized polycrystalline silicon layer 12 which forms the PMOS source/drain (S/D) regions 13 and 15 together with intermediate channel region 14.
- S/D PMOS source/drain
- the PMOS S/D 15 is formed in contact with NMOS S/D 16 to provide electrical interconnection for the stacked inverter.
- the Colinge et al. structure eliminates isolation cells, decreases latchup and provides decreased wire routing complexity.
- a memory device of the kind specified characterized in that said memory cell further includes a second, fixed threshold device having a channel structure and a gate structure, in that said second device is formed in adjacent relationship to said first device and in that said first device and said second device have a common functional element.
- a memory device is suitable for implementation in a ROM structure.
- the common functional element of the two devices is a common gate electrode.
- the common functional element of the two devices is a common channel.
- the alterable threshold device and the fixed threshold device may be formed in stacked relationship or in side-by-side relationship in the same active area.
- a bit-selectable, two bit per cell memory device includes a nonvolatile, alterable threshold memory device which shares a gate electrode structure in common with a fixed threshold device.
- the word "device” as used here and throughout the present patent document includes conventional field effect transistors as well as gate structures such as gated capacitive devices which may be devoid of source and/or drain.
- the channel region of the nonvolatile, alterable threshold memory device may comprise a source-channel-drain structure or simply a channel/electrode.
- the memory device includes a charge storage memory gate structure which includes a gate electrode, and a gate dielectric formed between the gate electrode and the channel, such that the memory device can be written to first and second, low voltage and high voltage threshold states.
- the non- memory, fixed threshold device is formed either in stacked relationship with the memory device (in which case the two devices share a common recrystallized polychannel or a common gate electrode), or in side- by-side relationship to the memory device (in which case the two devices share the same active region and can have an electrically common gate electrode structure and common source/drain regions).
- the fixed threshold device is fabricated to have a threshold voltage which is intermediate the low (erased) and high (written) states of the NV, alterable threshold memory device.
- the logic state of the NV alterable threshold memory device can be determined by applying an Erase sequence to the NV alterable threshold memory device, followed by the application of a Read voltage the magnitude of which is between the erased threshold voltage (VTO) of the NV alterable threshold memory device and the threshold voltage of the fixed threshold device.
- VTO erased threshold voltage
- the logic state of the fixed threshold voltage device is read by applying a Write sequence to the NV alterable threshold memory device, followed by the application of a Read voltage the magnitude of which is between the threshold voltage of the fixed threshold device and the written threshold voltage (VTI) of the NV alterable threshold memory device.
- VTI written threshold voltage
- a logic "1" or "0" is provided at a particular ROM device address by manufacturing or programming the device to be inoperable/operable.
- devices are rendered inoperable by the use of very heavy implants or thick gate oxide to elevate the device threshold voltage well above the operating voltage range for the particular integrated circuit.
- the ROM structure uses this standard inoperable/operable programming to provide logic 0/1 states.
- An ROM array incorporating the cell structure of the invention has the advantage of permitting an ROM array to function electrically as two separate arrays.
- the two bit per device construction of the present invention can be implemented in various combinations of SOI, MNOS (MNOS includes SNOS), and MOS (MOS includes SOS) configurations.
- MNOS includes SNOS
- MOS includes SOS
- Fig. 1 is a schematic cross-sectional representation through one portion of a prior art, stacked CMOS integrated circuit
- Figs. 2 and 3 are schematic cross-sectional representations through portions of respective stacked integrated circuit structures which are alternative embodiments of the present invention
- Figs. 4 and 5 are schematic plan view outlines of shared active region integrated circuit structures which are alternative embodiments of the present invention.
- Figs. 6 and 7 are cross-sections taken along the lines 6-6 and 7-7 through devices in Fig. 5;
- Figs. 8 and 9 are cross-sections taken along lines 8-8 and 9-9, respectively, through devices in Fig. 6; and Fig. 10 schematically illustrates a memory array circuit.
- a first embodiment 30 of a twobit per cell structure in the form of an inverted, NVAT (non-volatile, alterable threshold) SOI memory transistor 31 and an overlying fixed threshold transistor 32.
- the transistors 31 and 32 have a common recrystallized polysilicon source- channel-drain structure.
- the SOI NVAT memory transistor 31 is constructed in accordance with the SOI structure and fabrication sequence which are described in detail in the above-identified, international patent application No. WO 84/04418.
- the SOI structure includes a silicon substrate 33, an insulator dielectric layer 34, and the inverted trigate -memory configuratidn including ' polysilicon gate electrode 35 (poly I), nitride layer 36, oxide layer 37 and the recrystallized polysilicon layer 38 (poly II) which forms the source and drain 39-39 and channel region 41.
- the fixed threshold transistor 32 comprises the gate electrode 42 which is formed from a third layer of polysilicon (poly III), gate oxide layer 43 and the underlying source 39-channel 41-drain 39 which is common to device 31 as well.
- the trigate SOI configuration of device 31 includes a very thin memory oxide section 37M (about 1-4 nanometers) formed central to the channel and the thicker sections 37 which flank memory oxide 37M at the source and drain sides thereof to eliminate the instabilities and threshold shifts described in U.S. Patent No. 3,719,866.
- a very thin memory oxide section 37M about 1-4 nanometers
- the thicker sections 37 which flank memory oxide 37M at the source and drain sides thereof to eliminate the instabilities and threshold shifts described in U.S. Patent No. 3,719,866.
- the starting material is a wafer or substrate 33 of material having a low coefficient of thermal expansion which is comparable to that of the dielectric material such as silicon dioxide or silicon nitride which is used in the device.
- Suitable materials include silicon, high temperature glass, and ceramics such as alumina (aluminum oxide) .
- Insulator 34 electrically isolates the memory device from the substrate 33 and the peripheral circuitry and typically comprises silicon dioxide (or silicon nitride) formed to a thickness of about 1,000 nanometers by chemical vapor deposition or, where the substrate 33 is silicon, by high temperature oxidation of the silicon.
- the first layer of polysilicon (poly I) is formed about 300 nanometers thick by conventional process techniques such as low pressure chemical vapor deposition (LPCVD) followed by delineation and patterning using conventional photolithographic and etching techniques to form the gate electrode 35.
- the polysilicon gate electrode can be doped in situ or by subsequent ion implantation.
- the nitride layer 36 is conformally deposited to a thickness of about 40 nanometers using a conventional LPCVD (silane/ammonia system; 750°C; 400 T) operation, followed by deposition of the oxide layer 37 to a thickness of about 70-80 nanometers using low temperature LPCVD (silane/oxygen system; 420°C; 300 mT) operation. Thereafter, the central memory oxide section is removed using conventional photolithographic and etching techniques, and a new oxide is thermally grown or deposited to ensure that section 37 M has thickness of about 1-4 nanometers. Suitable techniques include chemical vapor deposition. or conversion of the exposed region of nitride 36 by oxidation (wet oxygen; 1000°C; 30 minutes) into the oxide section 37 M.
- a second polysilicon layer 38 (polysilicon II) is formed to a thickness of about 450-500 nanometers, again using conventional techniques such as LPCVD.
- the poly II layer 38 is then lightly doped by ion implantation (for example, with boron at 35keV and a dose of 1E12-2E13 ions/sq cm.) to provide the requisite channel conductivity.
- the poly II layer 38 is then capped with an anti-reflective coating of nitride (not shown) which is formed about 40-45 nanometers thick by conventional processing such as LPCVD.
- the poly II layer 38 is exposed to a laser beam (for example, a continuous wave argon laser having an effective beam diameter of 45 micrometers, a beam power of 5 watts, and a scanning speed 200 cm per/sec.) to convert the polysilicon to device-quality material comprising a recrystallized matrix of crystallites having various crystal orientations.
- a laser beam for example, a continuous wave argon laser having an effective beam diameter of 45 micrometers, a beam power of 5 watts, and a scanning speed 200 cm per/sec.
- the nitride cap (not shown) is then removed using concentrated hydrofluoric acid and the recrystallized poly II layer is patterned to the source 39-channel 41-drain-39 configuration shown in Fig. 2.
- the fixed threshold transistor 32 is formed by depositing an oxide layer 43 to a typical thickness of 50 nanometers.
- a silane/oxygen LPCVD technique of the type described previously can be used here as well.
- the polysilicon gate 42 layer (poly III) is formed, typically to a thickness of approximately 300 nanometers using the same formation technique (LPCVD) and the same implantation doping techniques described relative to poly gate electrode 35.
- the structure is photolithographically processed to mask polysilicon gate 42 so that successive etching of gate 42 and oxide 43 provides for self-aligned implanting of source and drain regions 39-39 with n-type impurity.
- a low temperature oxide layer 44 about 900-1,000 nanometers thick is blanket deposited over the structure and is densified at a temperature of about 900°C in nitrogen.
- the densification step is also used to activate the ions implanted in the source and drain regions.
- the device can be completed, for example, by making contact cuts to the source and drain 39-39 and the gates 35, 42 through the oxide 44, followed by contact enhancement using phosphorus oxychloride (POCI3) deposition and thermal diffusion, followed by metallization and the formation of a passivation layer.
- POCI3 phosphorus oxychloride
- the resulting metal contacts and passivation layer are not shown in Fig. 2, but electrode connec ⁇ tions are illustrated schematically by vertical lines connecting to the drain 39-39 and the gates 35 and 42.
- the cell 30 shown in Fig. 2 is thus a non- alterable-over-an-alterable transistor configuration with a common source/channel/drain structure.
- One of the key aspects of this design and the associated operation is the dual function of the SOI nonvolatile alterable threshold device 31. That is, device 31 acts first as a switch to select between the alterable threshold device 31 and the fixed threshold device 32 for reading and, secondly, functions as a memory location to provide a logic 0/1 output.
- the threshold voltages of the transistor 31 is conveniently adjusted to an inoperatively high threshold (logic 0) or to an operative threshold (logic 1) by adjusting the gate oxide thickness or by implantation.
- the binary state represented by fixed threshold device 32 is adjusted by implant to provide an erased threshold voltage of -1 volt (VTO) and a written threshold voltage of +4 volts (VT1) .
- VTO erased threshold voltage
- VT1 written threshold voltage
- two bits of information can be obtained from the single cell 30 by a simple addressing scheme, which is summarized in Table 1.
- Table 1 assumes that logic 1/0 for each device 31 and 32 is determined by an operative/inoperative device at that location.
- the first sequence is designed to select the alterable threshold transistor 31 for reading and involves (a) an Erase operation which is designed to write the memory transistor 31 (if operative) to a low threshold, VTO state, followed by (b) a sense operation using a 0 volt Read voltage.
- the device 31 conducts current, and this can be sensed as logic 1 by a standard sensing amplifier circuit.
- cell 30 does not conduct current, which is sensed as logic 0 at the cell 30 address. Note that with VTf at +l/volt, no conduction would be sensed even if gate electrodes 35 and 42 were made common.
- the fixed threshold transistor 32 location is selected by the application of (a) a Write program operation which is designed to write the alterable threshold memory transistor 31 to the high, VT1 threshold state, followed by (b) a Read voltage such as +2 volts, which voltage lies between VTf and VT1. Using this Write plus +2 volt Read sequence, the alterable threshold transistor 31 does not conduct current. (The binary state of the two transistor cell 30 is determined by whether or not transistor 31 is operative.) Logic 1/0 is then determined by the existence/nonexistence at the particular address location of an operative fixed threshold transistor 32 having a +4 volt threshold voltage.
- the transistor 31 is erased to VTO, for example, by applying a large (20-25 volts; 1-100 ms pulse duration) negative program voltage to the gate electrode 35 with respect to the channel to drive to the channel electrons which are trapped in the gate dielectric at the oxide-nitride interface and in the nitride bulk.
- the transistor 31 is written to the high threshold, VT1 state, by applying a large (20-25 volts; 1-100 ms pulse width) positive program voltage between the gate 35 and the channel (with the source and drain being maintained at ground potential) to tunnel electrons into the gate dielectric for storage.
- Electrode connections for writing and erasing the transistor 31 are illustrated schematically at 35P and 39P, Fig. 2. " Of course, the other NV alterable threshold devices described herein are written/erased similarly.
- Another version 50 of the alterable threshold transistor-fixed threshold transistor cell is shown in Fig. 3, in the form of a trigate SNOS transistor 51 having an upside down SOI fixed threshold transistor 52 formed thereon. This SNOS/SOI cell 50 is configured with a single gate electrode 55 and separate source-channel-drain structures.
- the SNOS alterable threshold device 51 is formed using a ⁇ 100> silicon substrate 53.
- the trigate dielectric comprises trigate memory oxide 57 and silicon nitride layer 56.
- the silicon dioxide layer can be formed to a thickness of about 70-80 nanometers using, for example, the same process which is used to form the memory silicon dioxide 37, Fig. 2.
- the oxide is then selectively removed from the central, memory region, for example, by etching with buffered hydrofluoric acid, and the memory oxide 57M is grown or deposited to a thickness of about 1-4 nanometers.
- This memory oxide layer can be grown by dry thermal oxidation of the silicon substrate, or can be formed on the substrate 53 by chemical vapor deposition using the same process that was used for the oxide layer 57.
- the silicon nitride layer 56 is deposited to a thickness of about 40 nanometers by conventional LPCVD.
- the polysilicon gate electrode 55 is then formed to a thickness of about 300 nanometers, typically using the same process which was used to deposit, delineate, pattern, and implant the gate 42 of Fig. 3.
- the oxide 57 and nitride 56 are removed from the regions outside the gate region. This can be done prior to the gate implant, using the same etching mask which is used to delineate and pattern the gate 55, or separately after the gate implant.
- the polysilicon electrode 55 is used as an implant mask and the source and drain 54-54 are formed self-aligned with the gate 55. This completes the SNOS device 51.
- the gate silicon dioxide layer 58 for the SOI fixed threshold device 52 can be formed to a thickness of about 50-55 nanometers using the same process which was used to form the fixed threshold oxide 43 of device 32, Fig. 2.
- a polysilicon layer 59 (polysilicon II) is formed over the existing structure to contact the source and drain 54-54, and is recrystallized using a laser beam as described ' previously for poly layer 38 (Fig. 2).
- the source 60-channel 61-drain 60 for the fixed threshold device 52 is selectively implanted, the source-drain 60.-60 being implanted with same conductivity type impurity as the source-drain 54-54.
- the same formation, patterning, * recrystallization and implant technique that was used for the recrystallized poly layer 38 of Fig. 2, can be used.
- the cell 50 is then completed, for example, by forming and densifying an intermediate silicon dioxide isolation layer, making contact cuts, and defining metallization, followed by the application of a passivation layer.
- the contacts (shown schematically extending downwards for reasons of clarity) are made to the single polysilicon gate electrode 55 and to source/drain electrodes 54.
- FIG. 4 Two additional alternative versions 70 and 90 of the two bit/cell structure are shown in schematic top views, in Figs. 4 and 5, respectively.
- the two bit/cell 70 of Fig. 4 contains NV alterable threshold device 31A and fixed threshold device 31F.
- the MOS/MNOS two bit/cell 90 of Fig. 5 contains NV alterable threshold device 51A and fixed threshold device 51F.
- devices 31A and 31F are similar to device 31 of Fig. 2 and devices 51A and 51F are similar to device 51 of Fig. 3, except that, preferably, devices 31F and 51F do not use a nitride layer such as 36 (Fig. 2) or 56 (Fig. 3).
- transistors 31A or 31F Figs. 4, 6, 7 and transistors 51A or 51F (Figs. 5, 8, 9) which are identical to those for devices 31 (Fig. 2) and 51 (Fig. 3) are designated by the same reference numerals used for devices 31 and 51. Modified components are indicated by the respective suffix A or F in transistors 31A or 31F and 51A or 51F.
- the fixed threshold transistors 31F or 51F and the alterable threshold transistor 31A or 51A are formed side-by-side in a common active area 65 of the integrated circuit.
- the source (and the drain) 39 or 54, respectively, of both devices is part of the same diffusion region or is connected in common.
- the same gate line serves both devices of the cell.
- the operation of the cells 70 and 90 is identical to that of devices 30 and 50, described above.
- the NV alterable threshold transistor 31A of cell 70 has the same construction as the NV alterable transistor 31 of Fig. 2.
- the fixed threshold transistor 31F preferably has the same construction as transistor 31 of Fig. 2, with the exception that the gate oxide 37F of fixed threshold device 31F is of a uniform non-memory thickness and the gate nitride is omitted.
- the basic fabrication sequence for the upside down device 31A was described for the corresponding device 31 of Fig. 2.
- the fixed threshold device 31F and the memory device 31A can be formed using a sequence in which the nitride 36 is formed everywhere then removed from the non-memory device areas 31F; the non-memory oxide 37F is formed everywhere; then the non-memory oxide is etched away in the memory regions of devices 31A, and memory oxide 37M is grown.
- the alterable threshold device 51A shown in Figs. 5 and 8 can have the same SNOS construction as the alterable threshold device 51 of Fig. 3.
- the fixed threshold device 51F shown in Figs. 5 and 9 can have essentially the same SNOS construction as the transistors 51 (with the exception that the threshold of device 51F is non-alterable).
- the basic fabrication sequence for the alterable threshold device 51 of Fig. 3 can be used to form the alterable threshold device 31A of Fig. 8 and the fixed threshold device 51F of Fig. 9.
- the dielectric sequence is basically the reverse of that used for side-by-side devices 31A and 31F, described above.
- the cells 30, 50, 70, and 90 can be formed into a memory pattern such as a ROM (read-only memory) array, as alluded to previously.
- a ROM read-only memory
- a dual ROM array built with the piggyback devices 30 (Fig. 2), or 50 (Fig. 3), or the side-by-side devices 70 (Fig. 4), or 90 (Fig. 5), in which each ROM array forms a separate pattern, such as a ROM pattern used to effect a different ROM code.
- the channels of the alterable threshold transistors can be implanted selectively in the particular 1/0 pattern of a code 1 in which the operable logic 1 devices can be electrically written to either VTO or VTl, whereas the logic 0 device sites are programmed to inoperatively high threshold voltages.
- the versatility of the present bit-selectable concept is further exemplified by the program selectable AND-OR.ROM circuit 80 which is shown in Fig. 10..
- the " figure illustrates the location of the NV alterable threshold devices, device location A, and the fixed threshold devices, device location B, as well as various examples of threshold voltage combinations for the devices.
- the notation "-1, +4" indicates that an operable memory device exists at that location which is switchable between VTO and VTl. That location is binary "1" in the NV alterable threshold code pattern. See, for example, device location A at address gate line 1-sense line 1 (i.e., address 1-1). In contrast, the notation "+4" in the A location at address 1-2 indicates there is no operable memory device at that location. Instead, device A has a fixed threshold of +4 volts. That location is binary "0" in the NV alterable threshold code pattern; the A pattern.
- the notation "+1” denotes the existence of an operable fixed threshold device (operable at the selected operating voltage conditions) which has an exemplary threshold of +1 volts, and binary "1". See, for example, addresses 1-1 and 2-2. Conversely, the notation "+4" at device locations B indicates an inoperable/non-existent fixed threshold device, and binary "0" in the B code pattern.
- Program selection and reading are also accomplished as described previously. For example, to read location 1-1 (gate line 1, sense line 1), device location -A, an erase sequence is applied to erase an operable device to VTO (-1 volt), then the address is read by grounding the gate line 1 (0 volts) with gate lines 2-4 at +5 volts and sense line 1 at the appropriate system voltage such as +5 volts. As described previously, the READ sequence turns on an operable memory device, * which is at VTO, (binary 1), but not an inoperable one (binary 0).
- the alterable threshold device could be a volatile device which has been coded by the transfer of charge to the threshold altering element of the device in a cell.
- the volatile alterable threshold device so coded is subject to change by selective transfers of charge.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/725,039 US4667217A (en) | 1985-04-19 | 1985-04-19 | Two bit vertically/horizontally integrated memory cell |
US725,039 | 1985-04-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1986006540A2 true WO1986006540A2 (en) | 1986-11-06 |
WO1986006540A3 WO1986006540A3 (en) | 1986-12-18 |
Family
ID=24912898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1986/000775 WO1986006540A2 (en) | 1985-04-19 | 1986-04-16 | Memory cell for use in a read only memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US4667217A (en) |
EP (1) | EP0218697A1 (en) |
JP (1) | JP2503219B2 (en) |
WO (1) | WO1986006540A2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0469554A2 (en) * | 1990-07-30 | 1992-02-05 | Nec Corporation | Non-volatile programmable read only memory device having a plurality of memory cells each implemented by a memory transistor and a switching transistor stacked thereon |
GB2291255A (en) * | 1994-07-12 | 1996-01-17 | Mosel Vitelic Inc | ROM coding by implant |
EP0908954A2 (en) * | 1997-10-07 | 1999-04-14 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
US6169308B1 (en) | 1996-11-15 | 2001-01-02 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
US6642574B2 (en) | 1997-10-07 | 2003-11-04 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4727044A (en) * | 1984-05-18 | 1988-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of making a thin film transistor with laser recrystallized source and drain |
US5210045A (en) * | 1987-10-06 | 1993-05-11 | General Electric Company | Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
US5268870A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Flash EEPROM system and intelligent programming and erasing methods therefor |
US5293560A (en) * | 1988-06-08 | 1994-03-08 | Eliyahou Harari | Multi-state flash EEPROM system using incremental programing and erasing methods |
US5268319A (en) * | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Highly compact EPROM and flash EEPROM devices |
US5043940A (en) * | 1988-06-08 | 1991-08-27 | Eliyahou Harari | Flash EEPROM memory systems having multistate storage cells |
JPH0263163A (en) * | 1988-08-29 | 1990-03-02 | Nec Corp | Nonvolatile semiconductor storage device |
US5196912A (en) * | 1988-10-28 | 1993-03-23 | Casio Computer Co., Ltd. | Thin film transistor having memory function and method for using thin film transistor as memory element |
US5079606A (en) * | 1989-01-26 | 1992-01-07 | Casio Computer Co., Ltd. | Thin-film memory element |
DE69033438T2 (en) | 1989-04-13 | 2000-07-06 | Sandisk Corp | Exchange of faulty memory cells of an EEprom matrix |
US5057885A (en) * | 1989-07-28 | 1991-10-15 | Casio Computer Co., Ltd. | Memory cell system with first and second gates |
KR950011026B1 (en) * | 1990-06-28 | 1995-09-27 | 가시오 게이상기 가부시끼가이샤 | Thin film memory cell |
JP2959066B2 (en) * | 1990-07-11 | 1999-10-06 | 日本電気株式会社 | Nonvolatile semiconductor memory device and driving method thereof |
JP3114229B2 (en) * | 1991-04-05 | 2000-12-04 | ソニー株式会社 | Non-volatile storage device |
US5212399A (en) * | 1991-08-15 | 1993-05-18 | Micron Technology, Inc. | Low cost polysilicon active p-channel load |
JP2817500B2 (en) * | 1992-02-07 | 1998-10-30 | 日本電気株式会社 | Nonvolatile semiconductor memory device |
JPH0883855A (en) * | 1994-09-13 | 1996-03-26 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory and fabrication thereof |
JPH08153879A (en) * | 1994-11-26 | 1996-06-11 | Semiconductor Energy Lab Co Ltd | Fabrication of semiconductor device |
JP3424427B2 (en) * | 1995-07-27 | 2003-07-07 | ソニー株式会社 | Nonvolatile semiconductor memory device |
US5687114A (en) * | 1995-10-06 | 1997-11-11 | Agate Semiconductor, Inc. | Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
US6487116B2 (en) | 1997-03-06 | 2002-11-26 | Silicon Storage Technology, Inc. | Precision programming of nonvolatile memory cells |
US5870335A (en) | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US6297096B1 (en) * | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US5822243A (en) * | 1997-09-09 | 1998-10-13 | Macronix International Co., Ltd. | Dual mode memory with embedded ROM |
US6004848A (en) * | 1997-09-09 | 1999-12-21 | Macronix International Co., Ltd. | Method of forming a multi-level memory array with channel bias algorithm |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6348711B1 (en) | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6282145B1 (en) * | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6429063B1 (en) | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
US6396741B1 (en) * | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6928001B2 (en) | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6396742B1 (en) | 2000-07-28 | 2002-05-28 | Silicon Storage Technology, Inc. | Testing of multilevel semiconductor memory |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US7098107B2 (en) | 2001-11-19 | 2006-08-29 | Saifun Semiconductor Ltd. | Protective layer in memory device and method therefor |
US6583007B1 (en) | 2001-12-20 | 2003-06-24 | Saifun Semiconductors Ltd. | Reducing secondary injection effects |
US6885585B2 (en) * | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
US6975536B2 (en) | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US6700818B2 (en) | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US7221591B1 (en) | 2002-05-06 | 2007-05-22 | Samsung Electronics Co., Ltd. | Fabricating bi-directional nonvolatile memory cells |
US6914820B1 (en) | 2002-05-06 | 2005-07-05 | Multi Level Memory Technology | Erasing storage nodes in a bi-directional nonvolatile memory cell |
US6747896B2 (en) | 2002-05-06 | 2004-06-08 | Multi Level Memory Technology | Bi-directional floating gate nonvolatile memory |
US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US6826107B2 (en) * | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US6992932B2 (en) | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
US6963505B2 (en) * | 2002-10-29 | 2005-11-08 | Aifun Semiconductors Ltd. | Method circuit and system for determining a reference voltage |
US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
US6967896B2 (en) * | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US7142464B2 (en) * | 2003-04-29 | 2006-11-28 | Saifun Semiconductors Ltd. | Apparatus and methods for multi-level sensing in a memory array |
US7123532B2 (en) | 2003-09-16 | 2006-10-17 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
US6954393B2 (en) * | 2003-09-16 | 2005-10-11 | Saifun Semiconductors Ltd. | Reading array cell with matched reference cell |
US20050110114A1 (en) * | 2003-11-25 | 2005-05-26 | Texas Instruments, Incorporated | Capacitor formed on a recrystallized polysilicon layer and a method of manufacture therefor |
WO2005094178A2 (en) * | 2004-04-01 | 2005-10-13 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
US7317633B2 (en) | 2004-07-06 | 2008-01-08 | Saifun Semiconductors Ltd | Protection of NROM devices from charge damage |
US7095655B2 (en) | 2004-08-12 | 2006-08-22 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
US7527994B2 (en) * | 2004-09-01 | 2009-05-05 | Honeywell International Inc. | Amorphous silicon thin-film transistors and methods of making the same |
US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
US7535765B2 (en) | 2004-12-09 | 2009-05-19 | Saifun Semiconductors Ltd. | Non-volatile memory device and method for reading cells |
CN1838328A (en) | 2005-01-19 | 2006-09-27 | 赛芬半导体有限公司 | Method for erasing memory cell on memory array |
US8053812B2 (en) * | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
US8400841B2 (en) * | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
US7184313B2 (en) * | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
EP1746645A3 (en) | 2005-07-18 | 2009-01-21 | Saifun Semiconductors Ltd. | Memory array with sub-minimum feature size word line spacing and method of fabrication |
US20070036007A1 (en) * | 2005-08-09 | 2007-02-15 | Saifun Semiconductors, Ltd. | Sticky bit buffer |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US7221138B2 (en) * | 2005-09-27 | 2007-05-22 | Saifun Semiconductors Ltd | Method and apparatus for measuring charge pump output current |
US20070087503A1 (en) * | 2005-10-17 | 2007-04-19 | Saifun Semiconductors, Ltd. | Improving NROM device characteristics using adjusted gate work function |
US7352627B2 (en) | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7638835B2 (en) * | 2006-02-28 | 2009-12-29 | Saifun Semiconductors Ltd. | Double density NROM with nitride strips (DDNS) |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US7605579B2 (en) | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |
US8680601B2 (en) | 2007-05-25 | 2014-03-25 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US9299568B2 (en) | 2007-05-25 | 2016-03-29 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US8614124B2 (en) | 2007-05-25 | 2013-12-24 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US9716153B2 (en) * | 2007-05-25 | 2017-07-25 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region |
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US9431549B2 (en) | 2007-12-12 | 2016-08-30 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
US20100130918A1 (en) * | 2008-11-21 | 2010-05-27 | Baxter International Inc. | Systems and methods for removing air from supply containers and associated fill tubing |
WO2014008160A2 (en) * | 2012-07-01 | 2014-01-09 | Cypress Semiconductor Corporation | Sonos ono stack scaling |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2418750A1 (en) * | 1974-04-18 | 1975-10-30 | Siemens Ag | Metal nitride-oxide semiconductor memory transistor - with decoder and memory in one chip in simple single-channel technique |
US4258378A (en) * | 1978-05-26 | 1981-03-24 | Texas Instruments Incorporated | Electrically alterable floating gate memory with self-aligned low-threshold series enhancement transistor |
EP0051158A1 (en) * | 1980-10-27 | 1982-05-12 | International Business Machines Corporation | Electrically alterable double dense memory |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5263686A (en) * | 1975-11-20 | 1977-05-26 | Toshiba Corp | Non-voltatile semiconductor memory device |
JPS5556662A (en) * | 1978-10-20 | 1980-04-25 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
JPS55156371A (en) * | 1979-05-24 | 1980-12-05 | Toshiba Corp | Non-volatile semiconductor memory device |
IL61671A (en) * | 1979-12-13 | 1984-04-30 | Energy Conversion Devices Inc | Diode and rom or eeprom devices using it |
DE3037744A1 (en) * | 1980-10-06 | 1982-05-19 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING A MONOLITHICALLY INTEGRATED TWO-TRANSISTOR MEMORY CELL IN MOS TECHNOLOGY |
JPS5854668A (en) * | 1981-09-29 | 1983-03-31 | Fujitsu Ltd | Electrically erasable read-only memory and manufacture thereof |
JPS58154273A (en) * | 1982-03-10 | 1983-09-13 | Seiko Instr & Electronics Ltd | Non-volatile semiconductor memory |
US4554570A (en) * | 1982-06-24 | 1985-11-19 | Rca Corporation | Vertically integrated IGFET device |
JPS6178169A (en) * | 1984-09-26 | 1986-04-21 | Hitachi Ltd | Semiconductor memory |
-
1985
- 1985-04-19 US US06/725,039 patent/US4667217A/en not_active Expired - Lifetime
-
1986
- 1986-04-16 JP JP61502384A patent/JP2503219B2/en not_active Expired - Fee Related
- 1986-04-16 WO PCT/US1986/000775 patent/WO1986006540A2/en not_active Application Discontinuation
- 1986-04-16 EP EP86902724A patent/EP0218697A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2418750A1 (en) * | 1974-04-18 | 1975-10-30 | Siemens Ag | Metal nitride-oxide semiconductor memory transistor - with decoder and memory in one chip in simple single-channel technique |
US4258378A (en) * | 1978-05-26 | 1981-03-24 | Texas Instruments Incorporated | Electrically alterable floating gate memory with self-aligned low-threshold series enhancement transistor |
EP0051158A1 (en) * | 1980-10-27 | 1982-05-12 | International Business Machines Corporation | Electrically alterable double dense memory |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0469554A2 (en) * | 1990-07-30 | 1992-02-05 | Nec Corporation | Non-volatile programmable read only memory device having a plurality of memory cells each implemented by a memory transistor and a switching transistor stacked thereon |
EP0469554A3 (en) * | 1990-07-30 | 1993-01-07 | Nec Corporation | Non-volatile programmable read only memory device having a plurality of memory cells each implemented by a memory transistor and a switching transistor stacked thereon |
GB2291255A (en) * | 1994-07-12 | 1996-01-17 | Mosel Vitelic Inc | ROM coding by implant |
US6169308B1 (en) | 1996-11-15 | 2001-01-02 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
US6825527B2 (en) | 1996-11-15 | 2004-11-30 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method |
EP0908954A2 (en) * | 1997-10-07 | 1999-04-14 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
EP0908954A3 (en) * | 1997-10-07 | 1999-07-14 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
US6642574B2 (en) | 1997-10-07 | 2003-11-04 | Hitachi, Ltd. | Semiconductor memory device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
EP0218697A1 (en) | 1987-04-22 |
WO1986006540A3 (en) | 1986-12-18 |
US4667217A (en) | 1987-05-19 |
JP2503219B2 (en) | 1996-06-05 |
JPS62502644A (en) | 1987-10-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4667217A (en) | Two bit vertically/horizontally integrated memory cell | |
US6888750B2 (en) | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication | |
US5496756A (en) | Method for forming a nonvolatile memory device | |
US4373248A (en) | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like | |
US5892709A (en) | Single level gate nonvolatile memory device and method for accessing the same | |
US6214666B1 (en) | Method of forming a non-volatile memory device | |
US6282123B1 (en) | Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell | |
US4686558A (en) | CMOS memory cell having an electrically floating storage gate | |
US5960265A (en) | Method of making EEPROM having coplanar on-insulator FET and control gate | |
KR920011046B1 (en) | Semiconductor memory cell and manufacture method | |
EP0320231B1 (en) | Erasable programmable memory | |
US5751037A (en) | Non-volatile memory cell having dual gate electrodes | |
US6191459B1 (en) | Electrically programmable memory cell array, using charge carrier traps and insulation trenches | |
JP3710082B2 (en) | How to make a memory transistor | |
JP3096401B2 (en) | Semiconductor random access memory cell on SOI having dual control gate and method of manufacturing the same | |
US5760435A (en) | Use of spacers as floating gates in EEPROM with doubled storage efficiency | |
US4558344A (en) | Electrically-programmable and electrically-erasable MOS memory device | |
US7326991B2 (en) | Nonvolatile semiconductor memory and method of operating the same | |
US4493057A (en) | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like | |
JPH0685274A (en) | Trench-type eeprom | |
US6458656B1 (en) | Process for creating a flash memory cell using a photoresist flow operation | |
US5262985A (en) | Nonvolatile semiconductor memory device | |
US5929478A (en) | Single level gate nonvolatile memory device and method for accessing the same | |
US5394002A (en) | Erasable programmable memory | |
US6696723B2 (en) | Electrically erasable, programmable, non-volatile memory device compatible with a CMOS/SOI production process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): DE GB NL |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1986902724 Country of ref document: EP |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): DE GB NL |
|
WWP | Wipo information: published in national office |
Ref document number: 1986902724 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1986902724 Country of ref document: EP |