WO1987001509A1 - Manufacture of a hybrid electronic or optical device - Google Patents

Manufacture of a hybrid electronic or optical device Download PDF

Info

Publication number
WO1987001509A1
WO1987001509A1 PCT/GB1986/000538 GB8600538W WO8701509A1 WO 1987001509 A1 WO1987001509 A1 WO 1987001509A1 GB 8600538 W GB8600538 W GB 8600538W WO 8701509 A1 WO8701509 A1 WO 8701509A1
Authority
WO
WIPO (PCT)
Prior art keywords
solder
chip
confronting
pads
substrate
Prior art date
Application number
PCT/GB1986/000538
Other languages
French (fr)
Inventor
David John Pedder
Andrew Duncan Parsons
Richard Antony Charles Bache
Original Assignee
Plessey Overseas Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Limited filed Critical Plessey Overseas Limited
Publication of WO1987001509A1 publication Critical patent/WO1987001509A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/048—Self-alignment during soldering; Terminals, pads or shape of solder adapted therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

In a flip chip bonding operation, a chip (1) is required to be accurately aligned over a pattern of electrical connector pads (5) on a substrate body (7). Electrical connections between the chip (1) and the pads (5) on the body are formed by solder bumps (3) which are fused to make the connections permanent. The method of the invention provides means for accurately aligning the chip (1) by using surface tension forces which arise in the solder portions when these are fused. A solder bump (3) having a diameter of at least 40 micrometres provides adequate force for the alignment and it allows solder bonds having a lesser diameter to be accurately aligned between the two components. The method can also be used to align the components of an optical device.

Description

MANUFACTURE OF A HYBRID ELECTRONIC OR OPTICAL DEVICE
The present invention concerns the manufacture of a hybrid electronic or optical device and in particular to method of alignment capable of being employed in the manufacture of for example solder bonded hybrid electronic devices.
The fabrication of certain types of flip-chip bonded hybrid electronic devices, for example 2-dimensional ther detector arrays and certain electro-optic devices, can require the use of very small solder bonds in the flip-ch structure. For example solder bond diameters as low as 1 to 20 micrometres are envisaged in particular devices now under development. The successful alignment and bonding flip-chip devices with such small solder bonds requires extremely accurate mechanical alignment of the two components. This can present practical problems, both in providing suitable alignment features on the chip accurat registered to the array of solder bonds which are, of course, hidden beneath the chip during bonding, and in achieving the required alignment accuracy in the bonding equipment itself. In other devices the accurate alignmen of micro-optical devices to an integrated optics substrat is required.
Flip-chip bonding is now a well established techniqu In this technique it is conventional to provide an electronic semiconductor chip and a co- operative substrate with mirror image patterns of bonding pads. Equi-sized solder bumps are deposited on either the chip or substrate, or in some cases upon both, the chip is then flipped over and registered above the substrate, and the solder reflowed. Provided the chip and substrate have been registered within tolerable accuracy, the two are then self-aligned.
The natural self-aligning nature of the flip-chip solder bonding process is effective provided that the mass of the chip component is not excessive, and provided good solder wetting is assured. The self-alignment process will come into play provided the solder bump on the chip (after it collapses on first melting to give a shape close to that of a truncated sphere with a contact angle equal to that of the non-wettable area of the substrate) contacts and overlaps the wettable pad on the substrate. This, to a first approximation, requires that the two components be aligned to a better than one wettable pad diameter distance. A practical lower limit on alignment of flip-chip devices employing a single solder bump size has been found to be at about a 40 micrometre solder bump and pad diameter. A more useful figure for a rapid alignment and solder bonding cycle on the manually controlled precision alignment equipment employed is 70 micrometres diameter. An automated pitch-and-place method for placing and aligning flip-chip components would ''probably require a still larger bump and pad diameter for example 100-150 micrometres. Practical problems may arise when solder bump and pad diameters below about 40 micrometres are required.
The present invention was devised to provide a solution to the problems aforesaid.
There is herein provided a method for achieving natural and highly accurate alignment of small diameter solder bonds in a flip-chip device, for aligning small optical components on an integrated optic substrate.
In accordance with the present invention there is provided a method of manufacture of a hybrid, solder-bonded electronic device where a substrate portion of the device is required to have a chip portion electronically connected thereto with confronting connection pads on the two portions being joined by solder bonds, the method comprising the steps of providing solder wettable contact pads on the substrate portion in a required pattern for forming the neccesary electrical connections, providing a corresponding pattern on the chip portion, depositing a separate solder portion onto each respective contact pad of a least one of the substrate portion and the chip portion, fusing said solder portions so as to form a solder bump from each sclder portion on its contact pad, positioning said chip portion on said substrate portion so that, each said solder bump is brought near to a corresponding solder wettable contact pad, heating said substrate and chip portions so that the said solder bumps became fused, the consequent flowing of the said solder portions acting to wet the respective confronting contact pads to form separate solder joints, surface tension forces then causing adjustment of the position of the said chip with respect to said substrate such that an accurate alignment of said confronting patterns of pads is effected, cooling the fused portions to form solder joints connecting the patterns of pads thereby uniting the chip portion to said substrate portion and establishing the required electrical connections. The said solder bumps may include at least one bump of diameter between 40 and 150 micrometres. The said solder bumps may include at least one bump of diameter 70 micrometres or greater. The solder bumps may include two or more bumps of diameter 40 micrometres or greater, with further bumps of a smaller diameter.
According to a further aspect, the invention comprises a method of aligning co-operating areas of confronting parts of an electronic or optical device, the method comprising the steps of providing solder wettable contact pads on each portion onto each respective contact pad of at least one of the said confronting parts, fusing
Figure imgf000007_0001
said solder portion so as to form a solder bump from each -.--solder portion on its contact pad, positioning the confronting parts together such that each solder bump is brought near to a corresponding solder wettable contact pad, heating said confronting parts such that the said solder bumps become fused, the consequent flowing of the said solder portions acting to wet the respective confronting contact pads to form separate solder joints, surface tension forces then causing adjustment of the position of one confronting part with respect to the other part such that an accurate alignment of said co-operating areas is effected, cooling the fused portions to form solder joints connecting the contact pads thus joining the confronting parts and providing accurate alignment of the said co-operating areas.
The invention also comprises an electronic or optical device when manufactured by the disclosed alignment method.
The solution thus is to provide a number of relatively large diameter solder bumps on a chip or substrate, whose function is to provide surface tension self-alignment of an array of smaller solder bumps or other cooperative device features. The large bumps exten the alignment tolerances during the bonding operation and are designed to physically contact the substrate first so as to align the chip to the substrate prior to the for ation of any smaller bonds.
The 'major' and 'minor' solder bumps in the array on
-_ ~* the chip are generally defined by applying solder over an area larger than that of the wettable metallisation and then reflowing (or fusing) the solder to form the bumps. The heights of the major and minor bumps may be controlled by varying the dewetting ratio (the solder deposition area to wettable pad area ratio) in the appropriate manner to ensure that the final bonds, once made, are of equal equilibrium height, whilst, prior to bonding, the major bumps are the greater in height.
The solder itself may be applied by electro deposition or by a thermal deposition technique, for example electron beam deposition using a thick resist mask Thermal deposition is the preferred process.
For low mass chips the mass acting on each solder bond in the array may generally be neglected, and thus, for the usual case of equal wettable pad diameters on chip and substrate, the solder bond shape closely approximates, for circular pads, to a truncated sphere. The use of circular pad geometries is preferred, for this allows a simple calculation of solder bump and joint dimensions, de-wet ratios, etc. to be made for different device configurations. BRIEF INTRODUCTION OF THE DRAWINGS
In the drawings accompanying this specification:- Figure 1 is a schematic view of a flip-chip and substrate, showing solder bump and bonding pad patterns; Figures 2(a) to (d) are cross-section at views of a flip-chip and substrate at successive stages during a bonding process;
Figures 3 and 4 are cross-sectional views showing the relative size of solder bumps and bonding pads as applied to align small diameter solder bonds for a flip-chip device; and, Figure 5 is a cross-sectional view showing the relative size of solder bonds and device features as applied to align small optical components on an integrated optic substrate. DESCRIPTION OF EMBODIMENTS So that the invention may be better understood, details of embodiments of this invention will now be described, by way of example only, and with particular reference to the accompanying drawings.
A schematic diagram of a conventional 'flip-chip1 device structure is shown in Figure 1. A device chip 1, which possesses an array of solder bumps 3 defined on solder wettable metallisation pads at appropriate points on the device, is flipped over to mate with a corresponding (mirror-imaged) array of solderable metal pads 5 on substrate 7 (in general solder may be present on either or both components, the choice depending upon the particular device and materials of interest). The chip 1 may be, for example, a thermal detector array, an optoelectronic device, a silicon or gallium arsenide circuit or a thin film circuit or component. The substrate 7 may be, for example, a thick or thin film circuit, or a second integrated circuit. The flip-chip hybrid device may comprise for example a 16x16 element pyroelectric detector array interfaced to a charge coupled device silicon integrated circuit device, which acts as a compact, uncooled solid state thermal imaging device. The flip-chip structure and process allows very large numbers of electrical connections between two components or devices to be made in a.highly space-efficient manner in a single, simple bonding operation. For example in a recent flip-chip bonded test device more than a thousand solder bonds were successfully made in a single operation on a chip 3.5mm square. Bonding is achieved by placing the components in contact, with the solder bumps 3 on the chip 1 overlapping the solder wettable pads 5 on the substrate 7, and then raising the assembly above the liquidus temperature of the particular solder employed. The solder then melts and wets onto the wettable pads. The high surface tension of the solder (200-600 mJ.m-^ depending on composition and environment) then acts to align the. components, as illustrated in Figures 2(a) to (d). As can be seen from these figures, provided the solder bump 3 is in close proximity to the bonding pad 5, the solder, on melting, touches the pad 5-Fig.2(b). Surface tension effects then cause the solder to wet the remaining portion of the pad 5 and to pull the chip 1 in a direction towards alignment-Fig.2(c) , until ultimately accurate alignment is achieved-Fig.2(d) .
A variety of solder compositions and wettable metallisation formulations may be employed. The 95 wt% lead : 5 wt% tin solder (solidus 310°C, liquidus
314°C) and the 37 wt% lead : 63 wt% tin solder (eutectic composition temperature 183°C) are commonly employed in flip-chip devices. Wettable metallisation formulations are invariably multi-layer metallic coatings, comprising an adhesion and diffusion barrier layer (for example chromium), a solderable layer (for example nickel or copper), and a tarnish prevention layer (for example gold). If copper is employed as the solderable metal then it is important to ensure that there is a region of alloying between the barrier layer and the copper to prevent total dissolution of the copper when soldering, which would then result in de-wetting. The wettable pads 5 may be rectangular, square or circular, the latter geometry greatly simplifying the calculation of solder bump and bond geometries. This surface tension alignment process is he-rein utilised to align smaller scale solder bonds or small device features as shown in Figures 3 and 4 respectively.
As shown in Figures 3 and 4,a pattern of bonding pads 5, 5' is defined upon the surface of a chip 1. A mirror image pattern is likewise defined on the surface of a supportive substrate 7. A particular feature of these patterns is that they each include relatively large size key pads 5 compared with those pads 5' for which alignment is required. The smaller size pads 5' are of diameter 2x' , typically less than 40 micrometres. The key pads 5 are chosen to be of a size facilitating registration, typically in the range 40 micrometres to 150 micrometres diameter (corresponding . to diameter 2x).
Solder has been deposited upon one of the pad patterns and melted to form bumps. The amount of solder deposited has been regulated to ensure that the height h of each key pad solder bump 3 is somewhat in excess of the height h' of the smaller scale bumps 3". This height difference is represented by the symbol 'z' in Figure 3. This ensures that when the chip 1 is flipped over and located in register upon the substrate 7, contact is first made between the key pads 5 and the key solder bumps 3. Initially, the target pads 5' and the target solder bumps 3' are held out of contact. During subsequent solder reflov or fusion, the target pads 5' and bumps 3' are pulled into accurate alignment by surface tension forces. An example of the foregoing flip-chip structure is given below:-
SOLDER BUMP GEOMETRIES FOR COMPATIBLE 10 & 70 MICRON DIA.B
MINOR MAJOR
WETTABLE RADIUS (x',x) 5 35 micrometres DEPOSITION RADIUS (-) 10 52.429 H REFLOW HEIGHT (h' ,h) 12.698 20.197 " BOND HEIGHT (S) 11.036 11.036 " CONTACT ANGLE (0 ) 155.628° 107.502°
SOLDER APPLICATION THICKNESS " : 5.000
DIFFERENCE IN REFLOW HEIGHTS (z) : 7.499
DIFFERENCE IN MAJOR BOND TO MINOR REFLOW : 1.662 DIFFERENCE IN BOND HEIGHTS : -0.000 n
The technique described may be used not only for aligning small scale size solder bumps, but also for aligning optical components. As shown in Figure 5, two small size optic device features 9, 9' have been aligned. These are separated by a bond height S of 25 micrometres, using 100 micrometre diameter bonding pads and solder bumps with a reflow height h of about 40 micrometres. The foregoing description of embodiments of the invention has been given by way of example only and a number of modifications may be made within the scope of the invention as defined in the appended claims. For instance, it is not essential that the method of the invention should be restricted to align small components which are only electronic devices. The method could be used alternatively to align other small components such as integrated optical components, pyroelectric elements and the like.

Claims

1. A method of manufacture of a hybrid, solder bonded electronic device where a substrate portion of the device is required to have a chip portion electrically connected thereto with confronting connection pads on the two portions being joined by solder bonds, the method comprising the steps of providing solder wettable contact pads on the substrate portion in a required pattern for forming the necessary electrical connections, providing a corresponding pattern on the chip portion, depositing a separate solder portion onto each respective contact pad of at least one of the substrate portion and the chip portion, fusing said solder portions so as to form a solder bump from each solder portion on its contact pad, positioning said chip portion on said substrate portion so that each said solder bump is brought near to a corresponding solder wettable contact pad, heating said substrate and chip portions so that the said solder bumps become fused, the consequent flowing of the said solder portions acting to wet the respective confronting contact pads to form separate solder joints, surface tension forces then causing adjustment of the position of the said chip with respect to said substrate such that an accurate alignment of said confronting patterns of pads is effected, cooling the fused portions to form solder joints connecting the patterns of pads thereby uniting the chip portion to said substrate portion and establishing the required electrical connections.
2. A method as claimed in Claim 1, in which the said solder bumps include at least one bump of diameter between 40 and 150 micrometres.
3. A method as claimed in Claim 2, in which the said solder bumps include at least one bump of diameter 70 micrometres or greater.
4. A method as claimed in Claim 1 or 2, in which the said solder bumps include two or more bumps of diameter 40 micrometres or greater, with further bumps of a smaller diameter.
5. A method of aligning cooperating areas of confronting parts of an electronic or optical device the method comprising the steps of providing solder wettable contact pads on each of said confronting parts depositing a separate solder portion onto each respective contact pad of at least one of the said confronting parts, fusing said solder portion so as to form a solder bump from each solder portion on its contact pad, positioning the confronting parts together such that each solder bump is brought near to a corresponding solder wettable contact pad, heating said confronting parts such that the said solder bumps became fused, the consequent flowing of the said solder portions acting to wet the respective confronting contact pads to form separate solder joints, surface tension forces then causing adjustment of the position of one confronting part with respect to the other part such that an accurate alignment of said cooperating areas is effected, cooling the fused portions to form solder joints connecting the contact pads thus joining the confronting parts and providing accurate alignment of the said cooperating areas.
6. A method of manufacture of an electronic or optical device substantially as hereinbefore described with reference to any one of Figures 1 to 4 of the accompanying drawings.
7. An electronic or optical device when manufactured by a method as claimed in any one of Claims 1 to 6.
8. An electronic or optical device substantially as hereinbefore described with reference to any one of Figures 2 to 5 of the accompanying drawings.
PCT/GB1986/000538 1985-09-10 1986-09-10 Manufacture of a hybrid electronic or optical device WO1987001509A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB858522429A GB8522429D0 (en) 1985-09-10 1985-09-10 Alignment for hybrid device
GB8522429 1985-09-10

Publications (1)

Publication Number Publication Date
WO1987001509A1 true WO1987001509A1 (en) 1987-03-12

Family

ID=10584973

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1986/000538 WO1987001509A1 (en) 1985-09-10 1986-09-10 Manufacture of a hybrid electronic or optical device

Country Status (4)

Country Link
EP (1) EP0236410A1 (en)
AU (1) AU6336286A (en)
GB (1) GB8522429D0 (en)
WO (1) WO1987001509A1 (en)

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0304118A2 (en) * 1987-08-19 1989-02-22 Gec-Marconi Limited Alignment of fibre arrays
WO1989008926A1 (en) * 1988-03-16 1989-09-21 Plessey Overseas Limited Vernier structure for flip chip bonded devices
EP0370663A2 (en) * 1988-11-22 1990-05-30 Gec-Marconi Limited Optical coupling of optical fibres and optical devices
EP0398485A1 (en) * 1989-05-16 1990-11-22 Gec-Marconi Limited A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
US4983840A (en) * 1989-04-28 1991-01-08 Commissariat A L'energie Atomique Measuring system constituted by a radiation detection circuit, a reading circuit and a support such as a cryostat cold finger
EP0413639A1 (en) * 1989-08-18 1991-02-20 Commissariat A L'energie Atomique Assembly of parts forming a mutual angle and method for producing this assembly
GB2236217A (en) * 1989-08-23 1991-03-27 Itt Ind Ltd Improvement relating to electrical connectors
GB2239416A (en) * 1989-12-29 1991-07-03 Itt Ind Ltd Metal bonding method
WO1994000969A1 (en) * 1992-06-19 1994-01-06 Motorola, Inc. Self-aligning electrical contact array
EP0598006A1 (en) * 1991-08-05 1994-05-25 Motorola Inc Solder plate reflow method for forming a solder bump on a circuit trace.
WO1994017568A1 (en) * 1993-01-22 1994-08-04 Motorola, Inc. Self aligning surface mount electrical component
EP0490125B1 (en) * 1990-11-20 1996-03-13 Sumitomo Electric Industries, Ltd. Method of mounting semiconductor elements
EP0732736A2 (en) * 1991-09-02 1996-09-18 Fujitsu Limited Semiconductor package for flip-chip mounting process
WO1997007538A1 (en) * 1995-08-21 1997-02-27 Mitel Corporation Method of making electrical connections to integrated circuit
US5656507A (en) * 1992-01-28 1997-08-12 British Telecommunications Public Limited Company Process for self-aligning circuit components brought into abutment by surface tension of a molten material and bonding under tension
FR2748849A1 (en) * 1996-05-20 1997-11-21 Commissariat Energie Atomique HYBRIDER COMPONENT SYSTEM AND HYBRIDIZATION METHOD FOR AUTHORIZING THERMAL EXPANSION
DE19639938A1 (en) * 1996-09-27 1998-04-02 Siemens Ag Hybrid integrated circuit with heat sink, for power IGBT
WO1998029904A1 (en) * 1996-12-27 1998-07-09 Simage Oy Bump-bonded semiconductor imaging device
US5989937A (en) * 1994-02-04 1999-11-23 Lsi Logic Corporation Method for compensating for bottom warpage of a BGA integrated circuit
FR2864699A1 (en) * 2003-12-24 2005-07-01 Commissariat Energie Atomique ASSEMBLING A COMPONENT MOUNTED ON A REPORT SURFACE
WO2007054859A2 (en) * 2005-11-09 2007-05-18 Philips Intellectual Property & Standards Gmbh Miniature optical component
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US8535956B2 (en) 2012-02-14 2013-09-17 International Business Machines Corporation Chip attach frame
WO2013182763A1 (en) * 2012-06-08 2013-12-12 Société Française De Détecteurs Infrarouges - Sofradir Cooled detection device with improved cold plate
US8742582B2 (en) 2004-09-20 2014-06-03 Megit Acquisition Corp. Solder interconnect on IC chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3486223A (en) * 1967-04-27 1969-12-30 Philco Ford Corp Solder bonding
US3997963A (en) * 1973-06-29 1976-12-21 Ibm Corporation Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
DE2909370A1 (en) * 1978-03-14 1979-09-20 Citizen Watch Co Ltd Semiconductor device with plastics, heat resistant substrate - has soldered integrated circuit chip and connecting solder beads, chip and substrate spacing being more than 60 microns
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3486223A (en) * 1967-04-27 1969-12-30 Philco Ford Corp Solder bonding
US3997963A (en) * 1973-06-29 1976-12-21 Ibm Corporation Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
DE2909370A1 (en) * 1978-03-14 1979-09-20 Citizen Watch Co Ltd Semiconductor device with plastics, heat resistant substrate - has soldered integrated circuit chip and connecting solder beads, chip and substrate spacing being more than 60 microns
GB2062963A (en) * 1979-11-12 1981-05-28 Hitachi Ltd Semiconductor chip mountings
EP0147576A1 (en) * 1983-11-25 1985-07-10 International Business Machines Corporation Process for forming elongated solder connections between a semiconductor device and a supporting substrate

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0304118A3 (en) * 1987-08-19 1989-11-15 Plessey Overseas Limited Alignment of fibre arrays
EP0304118A2 (en) * 1987-08-19 1989-02-22 Gec-Marconi Limited Alignment of fibre arrays
WO1989008926A1 (en) * 1988-03-16 1989-09-21 Plessey Overseas Limited Vernier structure for flip chip bonded devices
US5022580A (en) * 1988-03-16 1991-06-11 Plessey Overseas Limited Vernier structure for flip chip bonded devices
EP0370663A3 (en) * 1988-11-22 1991-05-08 Gec-Marconi Limited Optical coupling of optical fibres and optical devices
EP0370663A2 (en) * 1988-11-22 1990-05-30 Gec-Marconi Limited Optical coupling of optical fibres and optical devices
US4983840A (en) * 1989-04-28 1991-01-08 Commissariat A L'energie Atomique Measuring system constituted by a radiation detection circuit, a reading circuit and a support such as a cryostat cold finger
EP0398485A1 (en) * 1989-05-16 1990-11-22 Gec-Marconi Limited A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
US5119240A (en) * 1989-08-18 1992-06-02 Commissariat A L'energie Atomique Assembly of parts forming an angle between them and process for obtaining said assembly
FR2651025A1 (en) * 1989-08-18 1991-02-22 Commissariat Energie Atomique ASSEMBLY OF WORKPIECES BETWEEN THEM AND METHOD OF OBTAINING THE ASSEMBLY
EP0413639A1 (en) * 1989-08-18 1991-02-20 Commissariat A L'energie Atomique Assembly of parts forming a mutual angle and method for producing this assembly
GB2236217A (en) * 1989-08-23 1991-03-27 Itt Ind Ltd Improvement relating to electrical connectors
GB2239416A (en) * 1989-12-29 1991-07-03 Itt Ind Ltd Metal bonding method
EP0490125B1 (en) * 1990-11-20 1996-03-13 Sumitomo Electric Industries, Ltd. Method of mounting semiconductor elements
EP0598006A1 (en) * 1991-08-05 1994-05-25 Motorola Inc Solder plate reflow method for forming a solder bump on a circuit trace.
EP0598006A4 (en) * 1991-08-05 1994-07-06 Motorola Inc Solder plate reflow method for forming a solder bump on a circuit trace.
EP0732736A3 (en) * 1991-09-02 1996-10-30 Fujitsu Limited Semiconductor package for flip-chip mounting process
EP0732736A2 (en) * 1991-09-02 1996-09-18 Fujitsu Limited Semiconductor package for flip-chip mounting process
US5656507A (en) * 1992-01-28 1997-08-12 British Telecommunications Public Limited Company Process for self-aligning circuit components brought into abutment by surface tension of a molten material and bonding under tension
WO1994000969A1 (en) * 1992-06-19 1994-01-06 Motorola, Inc. Self-aligning electrical contact array
US5381307A (en) * 1992-06-19 1995-01-10 Motorola, Inc. Self-aligning electrical contact array
WO1994017568A1 (en) * 1993-01-22 1994-08-04 Motorola, Inc. Self aligning surface mount electrical component
US5989937A (en) * 1994-02-04 1999-11-23 Lsi Logic Corporation Method for compensating for bottom warpage of a BGA integrated circuit
US6088914A (en) * 1994-02-04 2000-07-18 Lsi Logic Corporation Method for planarizing an array of solder balls
WO1997007538A1 (en) * 1995-08-21 1997-02-27 Mitel Corporation Method of making electrical connections to integrated circuit
FR2748849A1 (en) * 1996-05-20 1997-11-21 Commissariat Energie Atomique HYBRIDER COMPONENT SYSTEM AND HYBRIDIZATION METHOD FOR AUTHORIZING THERMAL EXPANSION
EP0818813A1 (en) * 1996-05-20 1998-01-14 Commissariat A L'energie Atomique Component system for bonding and method of bonding enabling thermal dilatations
US6170155B1 (en) 1996-05-20 2001-01-09 Commissariat A L'energie Atomique System of components to be hybridized and hybridization process allowing for thermal expansions
DE19639938A1 (en) * 1996-09-27 1998-04-02 Siemens Ag Hybrid integrated circuit with heat sink, for power IGBT
DE19639938C2 (en) * 1996-09-27 2001-06-13 Siemens Ag Hybrid integrated circuit with a glued heat sink
US5952646A (en) * 1996-12-27 1999-09-14 Simage Oy Low temperature bump-bonding semiconductor imaging device
WO1998029904A1 (en) * 1996-12-27 1998-07-09 Simage Oy Bump-bonded semiconductor imaging device
FR2864699A1 (en) * 2003-12-24 2005-07-01 Commissariat Energie Atomique ASSEMBLING A COMPONENT MOUNTED ON A REPORT SURFACE
WO2005064676A1 (en) * 2003-12-24 2005-07-14 Commissariat A L'energie Atomique Assembly of a component mounted on a transfer surface
JP2007519234A (en) * 2003-12-24 2007-07-12 コミツサリア タ レネルジー アトミーク Assembly of elements on the transfer surface
US8198729B2 (en) 2004-07-16 2012-06-12 Megica Corporation Connection between a semiconductor chip and a circuit component with a large contact area
US8742582B2 (en) 2004-09-20 2014-06-03 Megit Acquisition Corp. Solder interconnect on IC chip
WO2007054859A2 (en) * 2005-11-09 2007-05-18 Philips Intellectual Property & Standards Gmbh Miniature optical component
WO2007054859A3 (en) * 2005-11-09 2007-10-18 Philips Intellectual Property Miniature optical component
US8535956B2 (en) 2012-02-14 2013-09-17 International Business Machines Corporation Chip attach frame
US9686895B2 (en) 2012-02-14 2017-06-20 International Business Machines Corporation Chip attach frame
US10056346B2 (en) 2012-02-14 2018-08-21 International Business Machines Corporation Chip attach frame
WO2013182763A1 (en) * 2012-06-08 2013-12-12 Société Française De Détecteurs Infrarouges - Sofradir Cooled detection device with improved cold plate

Also Published As

Publication number Publication date
AU6336286A (en) 1987-03-24
EP0236410A1 (en) 1987-09-16
GB8522429D0 (en) 1985-10-16

Similar Documents

Publication Publication Date Title
WO1987001509A1 (en) Manufacture of a hybrid electronic or optical device
EP0398485B1 (en) A method of making a Flip Chip Solder bond structure for devices with gold based metallisation
US5075965A (en) Low temperature controlled collapse chip attach process
US6184062B1 (en) Process for forming cone shaped solder for chip interconnection
US5406701A (en) Fabrication of dense parallel solder bump connections
US6251766B1 (en) Method for improving attachment reliability of semiconductor chips and modules
US5873512A (en) Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier
EP0354114B1 (en) Method of building solder bumps and resulting structure
JP2813109B2 (en) Automatic solder matching method
US3869787A (en) Method for precisely aligning circuit devices coarsely positioned on a substrate
US6454159B1 (en) Method for forming electrical connecting structure
US5276754A (en) Optoelectronic mount and method for making
US6121062A (en) Process of fabricating semiconductor unit employing bumps to bond two components
JPH06112463A (en) Semiconductor device and mounting method thereof
US6762119B2 (en) Method of preventing solder wetting in an optical device using diffusion of Cr
US6170155B1 (en) System of components to be hybridized and hybridization process allowing for thermal expansions
US6413849B1 (en) Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor
JP4429564B2 (en) Mounting structure and method of optical component and electric component
EP0440615A1 (en) Uses of uniaxially electrically conductive articles
Pedder Flip chip solder bonding for microelectronic applications
JPH05175275A (en) Method of mounting semiconductor chip and mounting structure
Oppermann The role of Au/Sn solder in packaging
JP3001053B2 (en) Bump forming method and electronic device
Koopman et al. Fluxless no-clean assembly of solder bumped flip chips
JP2002111191A (en) Solder joining method and electronic circuit device using the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE FR GB IT LU NL SE

WWW Wipo information: withdrawn in national office

Ref document number: 1986905359

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1986905359

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1986905359

Country of ref document: EP