WO1987003687A1

WO1987003687A1 - Ion-selective field effect transistor and fabrication process

Info

Publication number: WO1987003687A1
Application number: PCT/FR1986/000420
Authority: WO
Inventors: Pierre Lacombe; Bernard Michaux; Jean-Paul Couput; Augustin Martinez; François CHAUVET
Original assignee: Societe Nationale Elf Aquitaine
Priority date: 1985-12-05
Filing date: 1986-12-04
Publication date: 1987-06-18
Also published as: FR2591389B1; EP0250476A1; FR2591389A1; JPS63501738A

Abstract

The field effect transistor comprises a T-shaped substrate wherein are executed in a grid zone (2) close to the extremity of the leg of the T two N-type diffusions to form the source (3) and the drain (4) and a grid opening (14) in a grid zone (2), said N-type diffusions extending and diverging towards the zone of the substrate where the leg of the T joins the transverse bar, the field deflect transistor being characterized in that the source (3) and drain (4) diffusions are surrounded by a P-type diffusion forming a guard ring (6) at the zone of the grid (2), in that between the grid zone (2) and the junction zone of the bar of the T with its leg, a P-type diffusion zone surrounds on each side the drain (4) and the source (3) diffusions and in that the length of the leg of the T is reduced and the N-type diffusions stop at immediate proximity of the junction of the leg with the transverse bar of the T.

Description

ION SELECTIVE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD

The present invention relates to an ion selective field effect transistor and the method of manufacturing this transistor.

Ion selective field effect transistors are known from the article by A. SIBBALD. "Chimical-sensitive field-effect transistors" I.E.E. Proceedings. Flight. 130. Pt. 1. N 5. Oct 1983 which gathers the bibliography (130 references) on the ISFET since the work of BERGVELD. 1970 to the present day.

Such field effect transistors are known, in particular from British patent 2,010,011, as well as their manufacturing process. Such a device of the prior art has the drawback of not being able to avoid the formation of parasitic or parallel channels elsewhere than at the level of the P-type channel produced in the region of the grid. In addition, the length of the drain and source diffusion is such that they bring additional resistances and thereby reduce the amplification of the field effect transistor.

A first object of the invention is to propose a field effect transistor which overcomes the above drawbacks.

This first object is achieved by the fact that the ion selective field effect transistor, comprising a T-shaped substrate in which are executed, in a grid area (2) close to the end of the leg of the T, two N-type diffusions to constitute the source (3) and the drain (4) in the grid area (2), said N-type diffusions extending away from the area of substrate (1) where the leg of the T joins the crossbar, is characterized in that the source diffusions (3) and drain (4) are surrounded by a diffusion ^'P type constituting a guard ring (6) level of the grid area (2), in that, between the grid area (2) and the junction area of the T bar with its leg, a P-type diffusion zone surrounds on each side the diffusions of drain (4) and source (3) and in that the length of the leg of the T is reduced and the N-type diffusions stop in the immediate vicinity of the junction of the leg and the transverse bar of the T.

According to another characteristic, N-type diffusion is carried out to a depth of 5 microns while P-type diffusion is carried out to a depth of 10 microns.

According to another characteristic, N-type diffusions are extended at the surface of the T bar by metallizations (30, 40) which are in contact with these diffusions by openings (31, 41).

According to another characteristic, the field effect transistor includes a contact pad (5) for polarizing the substrate.

A second object of the invention is to propose a method of manufacturing this transistor which makes it possible to obtain elements of better quality, that is to say with a low dispersion of the characteristics of the components and greater reliability in the manufacturing, that is to say a high manufacturing yield.

This object is achieved by the fact that the manufacturing process comprises, after a step of cleaning a silicon wafer (1), the following steps: formation of a guard ring (6) by a P-type diffusion

- formation of the source (3) and drain (4) electrodes by an N-type diffusion;

- passivation of the component by nitriding;

- chemical cutting according to a profile in ~ ~;

- formation of the gate electrode (14);

- passivation of all components and cutting edges;

- production of contact openings (31, 41, 50) and contact metallizations (30, 40, 5);

- cutting of each component (1A, 1B).

Other characteristics and advantages of the present invention will appear more clearly on reading the description below made with reference to the appended drawings in which:

- Figure 1 shows a perspective view in partial section of the component;

- Figure 2a shows a top view of the component and before cutting along the line DD '.

- Figure 2b shows a sectional view of Figure 2a along the section line AA ';

- Figures 3a, 3c, 3d, 4a, 4c, 5, 6a, 6c, 7, 8a, 9, 10, 11a, 12, 13a, show, in a sectional view of the component, the different stages of the manufacturing process ; - Figures 3b, 4b, 6b, 8b, 11b, 13b, show the top views of the masks used in the component manufacturing process.

FIG. 1 represents an ion selective field effect transistor (ISFET). This transistor has substantially the shape of a T whose narrow zone (1B) forms the central leg of the T and the wide zone (1A) forms the transverse bar of the T. This transistor consists of a P-type silicon substrate (1) with a concentration of 5.10 atm / cm3 and an orientation in the plane (100) of the substrate. In the above substrate, we will define by means of the manufacturing process which we will explain below, a grid area (2), drain diffusions (3), a source (4) of type N and drain (30), source (40) metallizations and a so-called substrate contact metallization (5). The metallizations (30, 40) end, at one end by contact pads (32, 42) and at the other end, come into contact in the openings of the substrate (31, 41) with the respective diffusions (3, 4) the drain and the source. This makes it possible to reduce the length of the drain and source diffusions as much as possible and consequently to proportionally decrease the additional resistances provided by these diffusions which reduce the amplification of the field effect transistor. The metallization (5), constituting a central stud, provides contact in the volume of the silicon constituting the substrate (1). This contact is made by means of a metallization in an opening (50, FIG. 2a) as will be seen in the rest of the manufacturing process. This central contact pad (5) which provides contact with the substrate (1) optionally makes it possible to adjust the threshold voltage V _τ of the ISFET by adjusting the value of the source-substrate voltage V _j g, in accordance to the following relationship:

where V _TQ represents the threshold voltage of the ISFET at source-substrate voltage V _BS zero, k being a constant and Coχ the gate capacity per unit area.

FIGS. 2a, 2b, 2c make it possible to better discern another advantage and improvement of the ISFET transistor of the present invention compared to the prior art. FIG. 2a represents a top view of the transistor in which the shape taken by the N-type, source (3) and drain (4) diffusions, the metallizations (30, 40) and the metallization (5) has been represented. as well as the shape taken by the openings (31, 41 and 50) for engaging the contacts of the metallizations (30, 40, and 5) on, respectively, the source (3), the drain (4) and the substrate (1). Also shown in hatching in this figure, a guard ring (6) constituted by a P-type diffusion which completely surrounds the N-type diffusions of source and drain (3, 4). As can be seen in FIG. 2c, which is a representation along the section AA ′ of the substrate (1), in the zone of junction of the bar of the T with the grid zone (2) situated at the end of the leg of the T, the P-type diffusion comprises a central zone (6) located between the two N-type diffusions of source (3) and drain (4) and two external zones located on either side of the source diffusions (3) and drain (4). On the other hand, in Figure 2b, which is a sectional representation along BB '(corresponding to the grid area (2)), of the substrate (1), it can be seen that the P-type diffusion is only located on the side and on the other of the two source (3) and drain (4) diffusions and that there exists between each of the diffusions P, N a zone of substrate (1) whose thickness is maintained at a given minimum, so lowering the breakdown voltage of the source-substrate diode and of the drain-substrate diode. In addition, the 7/0

6 diffusion of the drain and source zones and the creation of a separation zone between these two diffusions lead to better reproducibility of the general characteristics of the source-substrate and drain-substrate diodes, in particular of their breakdown voltage, which is essential for the functioning of IFSET.

Compared to a prior art known by British patent 2,010,011, in which a P + type layer is used to delimit the channel zone, this layer being diffused on the surface of the component above the drain and source diffusions, or everywhere on one face, with the exception of the channel zone and the contacting zone, the guard ring diffused on either side of the N-type diffusions constituting the source and the drain has two advantages:

- it prevents the formation of parasitic or parallel channels elsewhere than at the level of the channel:

- It plays an electrical role, by improving the characteristics of the source-substrate and drain-substrate diodes.

The fabrication of the transistor described according to FIGS. 1, 2 will now be explained by the manufacturing method described with the help of FIGS. 3 to 13. After initial cleaning of the substrate board (1) having in order the aim to degrease the wafer, to remove metallic impurities and organic products, we proceed to a first oxidation step by heating the wafer at 1100 ° C for 45 minutes with steam, then for 15 minutes with dry oxygen and finally for 10 minutes with argon. In this oxidation step, a silicon oxide (S. O) is grown over a thickness of 5000 A ° represented by the layer (10) in FIG. 3a. A third photogravure step using the mask of FIG. 3b makes it possible to remove the layer of silica

(10) in areas where P ⁺ type diffusion must take place. These areas are represented by the reference (6) in FIG. 3b. This photoetching and etching of the silica layer step is followed by a cleaning step to remove traces of resin and remove organo-metallic compounds.

A fourth step consisting in pre-depositing the P + type layer is obtained by heating boron impurities constituted by BBr,. heated at 1080 * C in a stream of nitrogen and oxygen for 7 minutes to transform it into B CL. This step makes it possible to obtain the P-type diffusion zones (6) shown in FIG. 3c.

This pre-deposition step is followed by a fifth step known as the redistribution of the diffusion of P ⁺ impurities carried out by heating the substrate to 1150 ° C. in a stream of nitrogen for 30 minutes, then a stream of wet oxygen for 30 minutes. and finally for 10 minutes in a stream of argon. This step is performed in order to increase the depth of diffusion, as shown in Figure 3d, and to calibrate the square surface resistance.

After a sixth stage of total deoxidation and a seventh stage of reoxidation of the substrate so as to increase the silica layer (11), the eighth stage of photogravure of the N + type diffusion zones is carried out in which, as shown in FIG. 4a attacks the diffusion of the source and the drain (3, 4). This photoengraving operation is carried out using the mask shown in FIG. 4b, a figure in which the zones (113) and (114) in which the silica layer has been represented

(11) is under attack. A ninth step of pre-deposition and redistribution of the N-type impurities, diffused in the substrate is carried out in a conventional manner for the skilled person, so as to diffuse the N-type impurities up to a depth of 5 microns and thus form the source (3) and the drain (4), as shown in Figure 4c.

It will be noted that the diffusion of type P impurities in the process of the invention is carried out to a depth of 10 microns, a depth greater than the depth of type N impurities. Compared to the process of the prior art known by British Patent 2,010,011, in which the N-type diffusion must reach a depth of 10 microns to subsequently allow the P-channel to be diffused, the method of the invention saves time. Furthermore, the "redistribution which follows the pre-deposit of doping impurities from the drain and source zones only causes a deep diffusion of the ring, which is not troublesome whereas the reverse, as well as does KURARAY.

This ninth step is followed by a tenth step of protective nitriding for the next V-attack step. This nitriding acts as a masking agent and passivator whose electrical properties are analogous to silicon oxide S. 0_, while having the qualities of resistance to attack by chemical agents. In this step consisting of a chemical deposition in the vapor phase under low pressure, a layer of silicon nitride (12), S ^ N- is deposited on the entire substrate, as shown in FIG. 5. The deposition of chemical vapor under low pressure is carried out by introducing dichlorosilane (S ^ H CI ^) and ammonia (NH,) in an oven maintained at a temperature of 750 ° C and in which a primary vacuum has been carried out. This low pressure chemical vapor deposition (LPCVD) chemical vapor deposition operation provides a better passivation quality than in a so-called CVD operation at atmospheric pressure. This nitride deposition step is carried out until a nitride thickness of 0.1 micron is obtained.

An eleventh photogravure step of the chemical cutting zone to be carried out is represented in FIGS. 6a, 6b and 2a by the reference (13), this reference represents a form of cutting in -O- inside which after photogravure, we will carry out a plasma attack of silicon nitride (12). The plasma consists of freon (CF.) mixed with 8% oxygen (Cλ>). This plasma attack is followed by an attack of the silicon oxide which has formed in the zone (13) so as to expose the silicon of the substrate (1) in the zone (13) in, visible in Figure 2a. It goes without saying that this attack and these steps are first carried out on one face, as shown in FIG. 6a, then repeated so as to obtain, as shown in FIG. 6c, an attack on both sides of the substrate (1 ). This shape in -O- (13) allows, when cutting several transistors on the same wafer, as shown in Figure 2a, where we see several cutting areas (13) belonging respectively to adjacent transistors, to keep to the wafer greater rigidity than when the latter is cut according to a so-called comb shape. Furthermore, this type of cutting also makes it possible, during the separation of the various transistors by cutting the element (1A), to absorb a positioning error of the cutting tool without damaging one or more transistors of the brochure. This measurement is important because, during the mechanical cutting of the components on the wafer, the manufacturing yield can decrease enormously because of the difficulty of positioning the diamond without damaging the needles (1B). In order to overcome this drawback, the anisotropic attack masks have at the bottom of each needle (1B) "shoulders" forming the end of the ".Ti." which allow the cutting tool to be positioned without damaging the needle, hence even better reliability.

This eleventh step is followed by a twelfth anisotropic attack step shown in FIG. 7. This attack is carried out in a manner well known to the skilled person and also makes it possible to obtain, in a well known manner, lateral faces of the substrate. (1) cut into a V in the area (13) in the form of -T this so as to give the transistor the shape visible on the sides of the part (1B), in the shape of a needle in FIG. 1. This anisotropic cut is carried out with ethylene diamine, the attack speed of which has been increased by proceeding at a temperature of 110 ^β C with the following proportions, 125 cc of ethylene diamine, 40 cc of water and 20 grams of pyrocathechol.

In a thirteenth step, the layer (12) of silicon nitride visible ^' in FIG. 7 is attacked by plasma, to arrive after this step at a wafer covered with a layer of silicon oxide (11) shown in FIG.

8a.

By a fourteenth step, the gate opening (14) is practiced by means of a photoetching, using the mask shown in FIG. 8b, mask in which the zone (114) represents the zone in which the oxide of silicon layer (11) will be attacked, so as to constitute on the substrate (1), at the desired location, the gate opening (14), as shown in Figure 8a.

By a fifteenth stage of dry oxidation, carried out at 1150 ° C., in a stream of dry oxygen gas and argon, a thickness of silica of 0.14 micron is represented, represented by the layer (15) on the figure 9. A sixteenth step of passivation of all the components and the cutting edges consists of depositing by

LPCVD a layer of nitride (16) on the components of the wafer, as shown in Figure 10.

The seventeenth step of the process consists of the photoengraving of the contact openings (31, 41, 50) using the mask shown in FIG. 11b. In this mask, the references (131, 141, 150) represent the places where the nitride and silica layers of the wafer are attacked to make room for the openings (31, 41, 50), as shown in Figures 11a and 2a. These openings will be carried out by means of a plasma attack.

An eighteenth step consisting of a metallization of the openings and of the plate is obtained by evaporating aluminum, so as to deposit a layer

(17) 5 microns thick on the wafer, as shown in Figure 12.

A nineteenth step consists of a photoengraving of the aluminum using the mask shown in FIG. 13b, in which the zones (130 to 132 and 140 to 142) represent the zones where the aluminum remains, that is to say - say at the location of the openings (31, 41, 50), as shown in FIG. 13a, and at the locations of metallization (30, 40, 32, 42), as shown in FIG. 1. Finally, a following cut the line DD ¹ makes it possible to separate each of the transistors from the wafer and to obtain the individual elements as shown in FIG. 1.

The process thus described makes it possible, by the simplifications and improvements made, on the one hand to the manufacturing process and on the other hand to the device, to obtain field effect transistors in a simpler, more economical and more reliable manner. selective for ions, such as those described by the prior art cited above. In in particular, the manufacturing process of the invention makes it possible to obtain a high manufacturing yield and a low dispersion of the characteristics of the components. One of the measures which contributes to this is that which consists in first carrying out the diffusion of the P-type channel, then the drain and source diffusions.

Other modifications within the reach of those skilled in the art also form part of the invention.

Claims

1) Ion selective field effect transistor comprising a T-shaped substrate in which two N-type diffusions are formed in a grid area (2) near the end of the T leg to constitute the source (3 ) and the drain (4) and a gate opening (14) in the gate area (2), said N-type diffusions extending away from the area of the substrate where the leg of the T joins the crossbar, characterized in that the source (3) and drain (4) diffusions are surrounded by a P-type diffusion constituting a guard ring (6) at the level of the grid area (2), in that between the grid zone (2) and the junction zone of the T bar with its leg, a type P diffusion zone surrounds on each side the drain (4) and source (3) diffusions and in that the length of the leg of the T is reduced and the N-type diffusions stop in the immediate vicinity of the junction of the leg and the transve bar T. rsale

2) Transistor according to claim 1, characterized in that the N-type diffusion is carried out to a depth of 5 microns while the P-type diffusion is carried out to a depth of 10 microns.

3) Transistor according to claim 1 or 2, characterized in that the N-type diffusions extend at the surface of the head of the T by metallizations which are in contact with these diffusions by openings (31, 41).

4) Transistor according to one of claims 1 or 2, characterized in that it comprises a contact pad (5) for polarizing the substrate (1) 5) Method for manufacturing the field effect transistor according to one of the preceding claims, characterized in that after a step of cleaning a silicon wafer (1), the following steps are carried out:

- formation of a guard ring (6) by a P-type diffusion;

- formation of the source and drain electrodes by an N-type diffusion;

- passivation of the component by nitriding;

- chemical cutting according to a _n_ profile;

- formation of the gate electrode (14);

- passivation of all components and the sides of the blanks;

- cutting of each component (1A, 1B).