WO1987004563A1 - Methods for fabricating transistors and mos transistors fabricated by such methods - Google Patents

Methods for fabricating transistors and mos transistors fabricated by such methods Download PDF

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Publication number
WO1987004563A1
WO1987004563A1 PCT/GB1987/000030 GB8700030W WO8704563A1 WO 1987004563 A1 WO1987004563 A1 WO 1987004563A1 GB 8700030 W GB8700030 W GB 8700030W WO 8704563 A1 WO8704563 A1 WO 8704563A1
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Prior art keywords
layer
insulating layer
seed
polycrystalline
amorphous
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PCT/GB1987/000030
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French (fr)
Inventor
Raymond Edward Oakley
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Plessey Overseas Limited
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Publication of WO1987004563A1 publication Critical patent/WO1987004563A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Definitions

  • This invention relates to methods for fabricating transistors, and to metal oxide silicon (MOS) transistors fabricated by such methods.
  • MOS metal oxide silicon
  • a conventional type of transistor structure comprises a positively doped bulk silicon structure which includes source and drain regions in the form of diffused N conductivity type regions spaced apart in a silicon substrate.
  • a gate electrode is formed over the silicon substrate between the source and drain regions. This structure has the disadvantage that undesirable capacitances exist between the source and drain regions and the substrate.
  • a silicon on saphire (SOS) transistor comprises a silicon layer having spaced apart source and drain regions on an insulating layer of saphire.
  • SOS silicon on saphire
  • Such a transistor attempts to reduce undesirable capacitances by putting the insulating layer under the device but this isolates the active channel region resulting in the device taking up an undefined potential which can modify the transistor action. Although this can be avoided by including a substrate contact on the top surface of the device, such a contact concerns that the device takes up more space.
  • a further conventional type of transistor which is subject to the same disadvantages as the SOS transistor is a silicon on insulator (SOI) transistor.
  • SOI silicon on insulator
  • Such a device comprises an insulating layer formed on a silicon 5 substrate.
  • a further silicon layer which includes source and drain regions is formed on the insulating layer.
  • a conventional method of fabricating the silicon on insulator (SOI) transistor structures comprises forming an insulating layer on a silicon substrate and etching seed
  • a layer of polysilicon is then formed over the insulating layer and over the seed window.
  • the polysilicon is then recrystallised (solid phase epitaxy) by way of a recrystallisation process, such as the one described in H. . Lam IEDM Technical Digest
  • Source and drain regions are then formed in the recrystallised polysilicon layer by, for example, an implant doping process and a gate is formed between the source and the drain. In this structure, the gate overlies the insulating layer.
  • the present invention is directed to a method for fabricating transistors which alleviates the afore mentioned disadvantages, and MOS transistors fabricated by such methods, which transistors have relatively low capacitances associated therewith.
  • a metal oxide silicon (MOS) transistor comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the other side of the seed window, and a gate between the source and the drain, the gate overlying the seed window.
  • MOS metal oxide silicon
  • the source and the drain may be diffused N type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insulator.
  • a method for fabricating a metal oxide silicon (MOS) transistor comprising: forming an insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the seed window(s); recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed window(s); isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining
  • amorphous or polycrystalline semiconductor layer forming a source on one side of the seed window over the insulating layer, a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed
  • the step of forming the insulating layer having one or more seed windows ? ay comprise forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed window(s), through the
  • recesses may be formed in the semiconductor substrate and the insulating layer may be formed in the recesses, the seed window(s) and the insulating layer thereby having a substantially flat
  • the isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window region(s) may be effected by etching away the non- recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or
  • the drain and the source may be formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
  • the step of recrystallising the amorphous or polycrystalline layer may be by solid phase epitaxy or by direct epitaxy.
  • direct epitaxy the amorphous polycrystalline layer recrystallises in the region of the seed window as the layer is deposited over the insulating layer and the seed window.
  • Embodiments of the present invention are advantageous in that they enable the fabrication of a novel MOS transistor structure having relatively low capacitances associated therewith. In addition, they provide for the elimination of the need to waste space due to adandonment of seed window regions by incorporating the seed window regions into the MOS transistor structures. This saving of space can lead to increased packing density.
  • Figures la to le show fabrication stages for a MOS transistor structure embodying the present invention.
  • FIGS 2a to 2e show fabrication stages of an alternative MOS transistor structure embodying the present invention.
  • silicon dioxide is formed on a single crystal semiconductor substrate 2 such as silicon.
  • a hole is etched through the insulating layer 1 to form a seed window 3; although only one seed window 3 is shown, a plurality of seed windows may be formed.
  • amorphous or polycrystalline semiconductor such as polysilicon 4
  • polysilicon 4 is- hen deposited over the insulating layer 1 and in the seed window 3 ⁇ as illustrated in Figure lb.
  • the polysilicon 4 may be subjected to, for example, furnace treatment to cause solid phase epitaxy which grows single crystal silicon regions in the polysilicon around the seed window
  • the substrate as a seed.
  • the single crystal silicon region so formed is illustrated in Figure lc by reference numeral 5.
  • the recrystallisation may be induced by laser treatments, electron beam treatments or quartz halogen lamps.
  • the seed window 3 is to correspond to an active region of a gate of a metal oxide silicon (MOS) transistor to be formed in the seed window 3 region.
  • MOS metal oxide silicon
  • the next stage in the method of fabrication of the MOS transistor is to etch away field regions 6 of the MOS transistor, the resulting structure being illustrated in Figure Id.
  • the field region 6 may be formed by converting the polysilicon layer in these regions into an insulator by oxidation.
  • Source and drain regions 7 and 8 are formed in the regions of the polysilicon layer which overlie the insulating layer 1, for example, by furnace doping or implant.
  • the source region 7 and the drain region 8 are formed on opposite sides of the seed window 3 and may be of N or P conductivity type.
  • a gate electrode, comprising a dielectric layer 9 and a conducting or semiconducting layer 10 is formed over, the seed window 3 as shown in Figure le. The gate electrode may be formed before the source and drain regions 7 and 8 are formed.
  • An MOS transistor formed in the above described way, such as the one illustrated in Figure le, is advantageous in that the benefits of silicon on insulator (SOI) technology (i.e. low capacitances) may be achieved for MOS transistors while using a simple fabrication process.
  • SOI silicon on insulator
  • the relatively low capacitance achievable in MOS transistors using the above described fabrication method exist since the fabrication method enables the MOS transistor to be formed in islands of good quality silicon which are connected to the substrate in the gate region, but have their source and drain regions over the initially formed oxide layer. Additionally, the transistors
  • the field oxide 5 fabricated in this way may have low field capacitance because the field oxide may be made up of the oxidised polysilicon plus the original oxide.
  • the insulating layer 1 is formed in recesses which have been etched in the single crystal semiconductor substrate 2,-vhich results in the seed window 3 and the insulating layer 1 having a substantially flat surface ( Figure 2a).
  • the polysilicon 4 is then formed on the
  • Source and drain regions 7 and 8 are then formed in a similar manner to that described earlier and the structure is then isolated, in this case, by converting the field regions to oxide 11 ( Figure 2d).
  • Source and drain electrodes S, D are connected to the respective source and
  • the steps for fabricating transistors, and the MOS transistors described above are intended to be examples and it is envisaged that variations may be adopted without departing from the scope of the present invention.
  • the step of recrystallisation by solid phase epitaxy may be combined with the isolation step which involves oxidation of the field regions.

Abstract

A metal oxide silicon (MOS) transistor comprises a semiconductor substrate (2), an insulating layer (1) on the substrate, and a seed window (3) in the insulating layer (1), which seed window (3) communicates with the semiconductor substrate. The MOS transistor also comprises a re-crystallised amorphous or polycrystalline semiconductor layer (4) which overlies the insulating layer (1) at least in the region of the seed window and contacts the semiconductor substrate (2). A source is formed in the re-crystallised amorphous or polycrystalline semiconductor layer (4) upon the insulating layer (1) on one side of the seed window (3), and a drain is formed in the re-crystallised amorphous or polycrystalline semiconductor layer (4) upon the other side of the seed window (3), and a gate electrode comprising a dielectric layer (9) and a conducting or semiconducting layer (10) is formed between the source and the drain.

Description

METHODS FOR FABRICATING TRANSISTORS AND MOS TRANSISTORS FABRICATED BY SUCH METHODS
This invention relates to methods for fabricating transistors, and to metal oxide silicon (MOS) transistors fabricated by such methods.
A conventional type of transistor structure comprises a positively doped bulk silicon structure which includes source and drain regions in the form of diffused N conductivity type regions spaced apart in a silicon substrate. A gate electrode is formed over the silicon substrate between the source and drain regions. This structure has the disadvantage that undesirable capacitances exist between the source and drain regions and the substrate.
Another conventional type of transistor structure, in this case a silicon on saphire (SOS) transistor, comprises a silicon layer having spaced apart source and drain regions on an insulating layer of saphire. Such a transistor attempts to reduce undesirable capacitances by putting the insulating layer under the device but this isolates the active channel region resulting in the device taking up an undefined potential which can modify the transistor action. Although this can be avoided by including a substrate contact on the top surface of the device, such a contact necesitates that the device takes up more space. A further conventional type of transistor which is subject to the same disadvantages as the SOS transistor is a silicon on insulator (SOI) transistor. Such a device comprises an insulating layer formed on a silicon 5 substrate. A further silicon layer which includes source and drain regions is formed on the insulating layer.
A conventional method of fabricating the silicon on insulator (SOI) transistor structures comprises forming an insulating layer on a silicon substrate and etching seed
10" windows in the insulating layer. A layer of polysilicon is then formed over the insulating layer and over the seed window. The polysilicon is then recrystallised (solid phase epitaxy) by way of a recrystallisation process, such as the one described in H. . Lam IEDM Technical Digest
IS 1980 paper 22.1. Source and drain regions are then formed in the recrystallised polysilicon layer by, for example, an implant doping process and a gate is formed between the source and the drain. In this structure, the gate overlies the insulating layer.
20) Such methods have the disadvantage that the seed window serves no further purpose after the recrystallisation process and so forms wasted space in the integrated circuit. Further, it is difficult to recrystallise the polysilicon over large areas,
25 particularly in areas distant from the seed window, which imposes restrictions on circuit layout and design.
The present invention is directed to a method for fabricating transistors which alleviates the afore mentioned disadvantages, and MOS transistors fabricated by such methods, which transistors have relatively low capacitances associated therewith.
According to the present invention there is provided a metal oxide silicon (MOS) transistor comprising a semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the other side of the seed window, and a gate between the source and the drain, the gate overlying the seed window. The source and the drain may be diffused N type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insulator. According to the present invention there is also provided a method for fabricating a metal oxide silicon (MOS) transistor, the method comprising: forming an insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the seed window(s); recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed window(s); isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining
5 amorphous or polycrystalline semiconductor layer; and forming a source on one side of the seed window over the insulating layer, a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed
10 window.
The step of forming the insulating layer having one or more seed windows? ay comprise forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed window(s), through the
15- insulating layer.
Alternatively, recesses may be formed in the semiconductor substrate and the insulating layer may be formed in the recesses, the seed window(s) and the insulating layer thereby having a substantially flat
20. surface. The isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window region(s) may be effected by etching away the non- recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or
25 by converting the non-recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field regions to an insulator.
The drain and the source may be formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
The step of recrystallising the amorphous or polycrystalline layer may be by solid phase epitaxy or by direct epitaxy. In direct epitaxy, the amorphous polycrystalline layer recrystallises in the region of the seed window as the layer is deposited over the insulating layer and the seed window.
Embodiments of the present invention are advantageous in that they enable the fabrication of a novel MOS transistor structure having relatively low capacitances associated therewith. In addition, they provide for the elimination of the need to waste space due to adandonment of seed window regions by incorporating the seed window regions into the MOS transistor structures. This saving of space can lead to increased packing density.
The invention will now be further described, by way of example with reference to the accompanying drawings, in which:
Figures la to le show fabrication stages for a MOS transistor structure embodying the present invention; and /00030
- 6 -
Figures 2a to 2e show fabrication stages of an alternative MOS transistor structure embodying the present invention.
In Figure la an insulating layer, for example,
5. silicon dioxide is formed on a single crystal semiconductor substrate 2 such as silicon. A hole is etched through the insulating layer 1 to form a seed window 3; although only one seed window 3 is shown, a plurality of seed windows may be formed. A layer of
10 amorphous or polycrystalline semiconductor, such as polysilicon 4, is- hen deposited over the insulating layer 1 and in the seed window 3~ as illustrated in Figure lb.
At least some of-the polysilicon 4 in the region of the seed window 3 spontaneously becomes recrystallised
15 using the substrate as a seed (direct epitaxy, that is, gas phase epitaxial deposition). However, the polysilicon 4 may be subjected to, for example, furnace treatment to cause solid phase epitaxy which grows single crystal silicon regions in the polysilicon around the seed window
20= 3 using the substrate as a seed. The single crystal silicon region so formed is illustrated in Figure lc by reference numeral 5. Alternatively, the recrystallisation may be induced by laser treatments, electron beam treatments or quartz halogen lamps.
25 The seed window 3 is to correspond to an active region of a gate of a metal oxide silicon (MOS) transistor to be formed in the seed window 3 region. The next stage in the method of fabrication of the MOS transistor is to etch away field regions 6 of the MOS transistor, the resulting structure being illustrated in Figure Id. Alternatively, the field region 6 may be formed by converting the polysilicon layer in these regions into an insulator by oxidation. Source and drain regions 7 and 8 are formed in the regions of the polysilicon layer which overlie the insulating layer 1, for example, by furnace doping or implant. In the arrangement illustrated in Figure le, the source region 7 and the drain region 8 are formed on opposite sides of the seed window 3 and may be of N or P conductivity type. A gate electrode, comprising a dielectric layer 9 and a conducting or semiconducting layer 10 is formed over, the seed window 3 as shown in Figure le. The gate electrode may be formed before the source and drain regions 7 and 8 are formed.
An MOS transistor, formed in the above described way, such as the one illustrated in Figure le, is advantageous in that the benefits of silicon on insulator (SOI) technology (i.e. low capacitances) may be achieved for MOS transistors while using a simple fabrication process. The relatively low capacitance achievable in MOS transistors using the above described fabrication method exist since the fabrication method enables the MOS transistor to be formed in islands of good quality silicon which are connected to the substrate in the gate region, but have their source and drain regions over the initially formed oxide layer. Additionally, the transistors
5 fabricated in this way may have low field capacitance because the field oxide may be made up of the oxidised polysilicon plus the original oxide.
An alternative series of fabrication stages for an MOS transistor structure is shown in Figures 2a to 2e. In
10. this case, the insulating layer 1 is formed in recesses which have been etched in the single crystal semiconductor substrate 2,-vhich results in the seed window 3 and the insulating layer 1 having a substantially flat surface (Figure 2a). The polysilicon 4 is then formed on the
15. surface of the insulating layer 1 and the seed window 3 as shown in Figure 2b. Recrystallisation of the polysilicon 4 in the region of the seed window 3 then takes place in a similar way to that described with reference to Figure lc t form a single crystal silicon region 5.
20? Source and drain regions 7 and 8 are then formed in a similar manner to that described earlier and the structure is then isolated, in this case, by converting the field regions to oxide 11 (Figure 2d). Source and drain electrodes S, D are connected to the respective source and
25 drain regions 7, 8 and a gate electrode G is formed over - 9 -
the seed window 3 (Figure 2e) in a similar manner to that described with reference to Figure le.
The methods for fabricating transistors, and the MOS transistors described above are intended to be examples and it is envisaged that variations may be adopted without departing from the scope of the present invention. For example, the step of recrystallisation by solid phase epitaxy may be combined with the isolation step which involves oxidation of the field regions.

Claims

-10- CLAIMS
1. A method for fabricating a metal oxide silicon (MOS) transistor, the method comprising: forming on insulating layer having one or more seed windows on a semiconductor substrate; depositing an amorphous or polycrystalline semiconductor layer on the insulating layer and on the one or more seed windows; recrystallising the amorphous or polycrystalline semiconductor layer at least in the region of the seed windows; isolating the recrystallised amorphous or polycrystalline semiconductor layer in the region of the seed window from the remaining amorphous or polycrystalline semiconductor layer; and forming a source on one side of the seed window over the insulating layer; a drain on another side of the seed window over the insulating layer, and a gate between the source and the drain, the gate being located over the seed window.
2. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in claim 1 wherein the step of forming the insulating layer having one or more seed windows comprises forming the insulating layer on the semiconductor substrate and then etching holes, corresponding to the seed windows through the insulating layer. -11-
3. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in claim 1 wherein recesses are formed in the semiconductor substrate and the insulating layer, the seed windows and the insulating layer thereby having a substantially flat surface.
4. A method of fabricating a metal oxide silicon (MOS) transistor wherein isolation of the recrystallised amorphous or polycrystalline semiconductor layer in the seed window regions is achieved by etching away the non-crystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field region or by converting the non-recrystallised and/or recrystallised amorphous or polycrystalline semiconductor layer in the field regions to an insulator.
5. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the drain is formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping of the polycrystalline layer after deposition.
6. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the the source is formed by doping the polycrystalline layer during deposition of the polycrystalline layer, by implanting or furnace doping the polycrystalline layer after deposition.
5.
7. A method of fabricating a metal oxide silicon (MOS) transistor as claimed in any preceding claim wherein the step of recrystallising the amorphous or polycrystalline layer is by solid phase epitaxy or direct epitaxy.
8. A metal oxide silicon (MOS) transistor comprising a 10 semiconductor substrate, an insulating layer on the semiconductor substrate, a seed window in the insulating layer which seed window communicates with the semiconductor substrate, and a recrystallised amorphous or polycrystalline semiconductor layer overlying the insulating layer at least in the region of the seed window 15 and contacting the semiconductor substrate, a source formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the insulating layer on one side of the seed window, a drain formed in the recrystallised amorphous or polycrystalline semiconductor layer upon the 20 other side of the seed window and a gate between the source and the drain, the gate overlying the seed window.
9. A metal oxide silicon (MOS) transistor as claimed in claim 8 wherein the source and the drain are diffused N-type regions formed in the part of the recrystallised amorphous or polycrystalline layer which overlies the insultor.
iσ
15
PCT/GB1987/000030 1986-01-25 1987-01-19 Methods for fabricating transistors and mos transistors fabricated by such methods WO1987004563A1 (en)

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GB08601830A GB2185851A (en) 1986-01-25 1986-01-25 Method of fabricating an mos transistor
GB8601830 1986-01-25

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US5021119A (en) * 1987-11-13 1991-06-04 Kopin Corporation Zone-melting recrystallization process
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4863877A (en) * 1987-11-13 1989-09-05 Kopin Corporation Ion implantation and annealing of compound semiconductor layers
US5021119A (en) * 1987-11-13 1991-06-04 Kopin Corporation Zone-melting recrystallization process
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process

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EP0258285A1 (en) 1988-03-09
GB2185851A (en) 1987-07-29
GB8601830D0 (en) 1986-02-26
JPS63502544A (en) 1988-09-22

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