WO1987004821A1 - Apparatus and method for execution of branch instructions - Google Patents
Apparatus and method for execution of branch instructions Download PDFInfo
- Publication number
- WO1987004821A1 WO1987004821A1 PCT/US1987/000178 US8700178W WO8704821A1 WO 1987004821 A1 WO1987004821 A1 WO 1987004821A1 US 8700178 W US8700178 W US 8700178W WO 8704821 A1 WO8704821 A1 WO 8704821A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- instruction
- execution
- sequence
- condition
- branch
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 65
- 230000000694 effects Effects 0.000 claims description 7
- 230000000977 initiatory effect Effects 0.000 claims 1
- 238000012360 testing method Methods 0.000 abstract description 17
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000001934 delay Effects 0.000 description 4
- 230000004044 response Effects 0.000 description 2
- 238000012956 testing procedure Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3846—Speculative instruction execution using static prediction, e.g. branch taken strategy
Abstract
In a pipelined data processing system using microinstructions from a control unit, the method of implementing a conditional branch macroinstruction involves the sequence of microinstructions in which the potential instruction sequence is prepared for execution while the original instruction sequence continues in execution even though the results of the condition testing are not determined. When the condition is determined to be false, the instruction sequence in execution is continued and the retrieved instruction sequence is not activated. When the condition is determined to be true, the new instruction sequence can be executed immediately and the results of the original (and erroneous) sequence can be discarded. In conditional branch macroinstructions where the probability of branching is large, an unconditional branch instruction is executed to place the most probable instruction sequence in immediate execution and the conditional branch instruction, described above, is executed to determine the result of the condition.
Description
APPARATUS AND METHOD FOR EXECUTION
OF BRANCH INSTRUCTIONS
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data
processing systems in which the implementation of instructions is divided into a plurality of suboperations permitting an overlap in the execution of consecutive instructions, and typically referred to as pipelining the execution of the instructions.
This technique is frequently used in the data processing unit subsystems to increase the rate of instruction execution. The present invention reduces the delays encountered in the execution of conditional branch instructions.
2. Description of the Related Art
Referring to Figure 1, a typical data processing system is shown. The data processing system includes at least one central processing unit 10 ( or 11), at least one input/output device 13 (or 14), a memory unit 15 and a system bus 19 coupling the plurality of subsystems or units of the data processing system.
The central processing unit processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed are typically stored in the memory unit 15.
A console unit 12 can be coupled to the central processing unit(s) and includes the apparatus and stored instructions to initialize the system and can function as a terminal during the operation of the data processing system. The input/output units provide the interface of the data processing system to terminal units, mass storage units, communication units, and any other units to be coupled to the data processing system that exchange logic signal groups with the system. The present invention relates to
the operation of the central processing unit, and provides an apparatus and method for more efficient execution of certain portions of the programs controlling the processing of data signal groups.
In a data processing system, such as is illustrated in Figure 1, the actual manipulation of data signal groups takes place under the control of a group of related instructions that is generally called a program. These instructions are executed in a sequence. Referring next to Figure 2a, the
execution of a series of instructions according to the related art is illustrated. During a first time interval, Tg, the instruction #1 is executed by a central processing unit subsystem.
After the first instruction is executed, a next instruction #2 in the sequence is executed by the central processing unit subsystem during the second time interval,T0. Upon completion of instruction #2, the data processing unit executes instruction #3 during the third time interval To In order to maintain an orderly execution of instructions, the interval for the execution of any instruction by the data processing unit requires a predetermined period of time. If the execution time for an instruction can have a variable length, complex apparatus must then be included in the central processing unit to coordinate the exchange of data signal groups between the central processing unit and the other subsystems of the data processing system.
Thus, the period for execution of the three instructions will generally be three times the basic time period. It will be clear that the basic time interval must be of sufficient duration to permit the execution of the lengthiest instruction in the instruction set unless the execution of instructions is implemented using a ' more sophisticated technique such as described below.
In order to provide for faster operation of the data processing system, a technique for dividing the execution of an instruction into the execution of a plurality of instruction segments has been devised.
The instruction segments are components of a microinstruction and a related group of
microinstructions implements a macroinstruction.
When the apparatus implementing the segments is organized appropriately, the execution of the instructions can be performed in an overlapping manner. This technique is referred to as "pipelining" the execution of an instruction set.
While the execution of each pipelined instruction can take a longer period of time than is required for the execution of a nonpipelined instruction, because of the additional apparatus required for the division of the instruction into the instruction segments, an instruction stream can be executed faster than is
possible for the nonsegmented instructions. In
Figure 2b, the division of an instruction into a plurality of segments is shown. It will be understood that each segment relates to a separate and independently operating group of components in
the central processing unit. Registers and gates, according to principles well-known in the art of data processing system design, can implement the operation of a group of components executing a particular segment.
The subinterval, t0, for each segment must be sufficiently long to permit the execution of all possible segments in each apparatus group.
Referring next to Figure 2c, the resulting increase in the rate of execution of a sequence of instructions possible through the use of pipelining
techniques is illustrated. Instruction #1 is now completed in the new (and possibly longer) time period of Tto equals n times t0, where t0 is the subinterval required for the execution of each instruction segment and where n is the number of instruction segments required for the execution of each instruction. The next instruction in the sequence, instruction #2, begins an interval t0 after the beginning of instruction #1. The third instruction in the sequence, instruction #3, then begins an interval t0 thereafter. Each instruction can take the increased amount of time for the
execution.
However, once the initial interval for the completion of the first instruction has passed, an instruction is completed after each interval to.
Thus, for a sequence of instructions, the execution of the sequence can be accelerated even though the individual instruction can take an increased length of time to execute.
Although the pipelining technique can provide for more rapid execution of an instruction sequence, this technique loses efficiency with the occurrence
of conditional "branch" instructions in an instruction sequence. The branch instruction involves the switching from one instruction sequence to a second instruction sequence. The conditional branch instruction involves the testing of a quantity against a predetermined condition. Depending on the result of the test, the instruction sequence can continue in the present sequence or the instruction sequence can jump or branch to a new instruction sequence. For the instruction sequence being executed as shown in Figure 2a, instruction #1 can be the instruction testing the condition, and the
particular next sequential instruction, illustrated by instruction #2, can be determined by the result of instruction #1.
In the case of the pipelined execution of the instruction set as illustrated in
Figure 2c, the result of the condition testing
procedure may not be available until instruction segment D of instruction #1. However, instruction #2 will, in normal operation, already have begun execution and instruction segments A and B of instruction #2 can have been completed.
In order to address the problem of branching in pipelined execution of instruction sequences, the typical approach has been to suspend the execution of the instruction sequence until the branch condition has been tested. Once the branch condition has been tested, then the execution of the correct instruction sequence, i.e. the original instruction sequence or the new instruction sequence, is initiated. This strategy provides an inefficient use of the central processing unit and results in delays in the instruction execution sequence. Not only is a delay incurred in waiting for the testing of the condition, but a further delay is encountered as the plurality of instruction segments is executed prior to the completion of the instruction, sometimes referred to as filling the pipeline.
A need has therefore been felt for apparatus and
method of operation for pipelined execution of an instruction sequence that would minimize the effect of a branch instruction on the system performance without requiring extensive additional apparatus and minimizing the compromise in improved instruction
execution resulting from the use of the pipelined instruction sequence execution.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved data processing system.
It is a further object of the present invention to provide an improved data processing unit for the execution of an instruction sequence.
It is a further object of the present invention to provide an improved data processing unit for the pipelined execution of an instruction sequence.
It is a more particular object of the present invention to provide a data processing unit having a pipelined instruction sequence execution in which either the original instruction sequence or the branch instruction sequence can be initiated before the determination of the occurrence of the condition has been completed.
The aforementioned and other objects are accomplished, according to the present invention, by providing a data processing unit with apparatus for recognizing the occurrence of a conditional branch
instruction. Upon recognition of the conditional branch instruction, the data processing unit initiates the retrieval of the first instruction in sequence to be executed when the branch condition is determined to be true. The next instruction executed by the data processing system is the instruction that would be executed if the branch condition is determined to be false, i.e. the original instruction sequence is continued. While this instruction (and any subsequent instructions in the original
instruction sequence) is being executed, the data processing system is preparing to execute the instruction sequence determined by the branch condition (if true).
When the determination is- made with respect to the branch condition, the data
processing unit can continue execution of the original instruction sequence already in execution if the condition is false. When the branch condition is true, then the activity of the data processing unit in preparing for the execution of the new instruction
sequence is utilized and the execution of the new instruction sequence replaces the execution of the original instruction sequence that is in progress.
For selected conditional branch instructions, for which there is a high probability that the branch condition will occur, the central processing unit executes an unconditional branch instruction to the
new sequence. After the preparation for the new instruction sequence is completed, the condition is tested.
If the condition (as originally interpreted) is true, the central processing unit continues to execute the new instruction sequence. Otherwise, the
instruction sequence execution reverts to the original instruction sequence.
These and other features of the present invention will be understood upon reading of the following description along with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the components of a data processing system capable of utilizing the present invention.
FIG. 2a is an illustration of the execution of an instruction sequence according to the related art;
FIG 2b is an illustration showing how an instruction can be divided into a plurality of instructions segments; and FIG 2c illustrates how a pipelined instruction execution can provide provide for increased performance by a central processing unit.
FIG. 3 is a block diagram of a data processing system implementing the pipelined execution of an instruction sequence.
FIG. 4 illustrates the execution of an unconditional branch instruction.
FIG. 5 illustrates the execution of a
conditional branch instruction in which the processing of further instructions is halted until the determination of the condition has been completed.
FIG. 6 illustrates the execution of a
conditional branch instruction according to the present invention.
FIG. 7 illustrates the execution of a conditional branch instruction, for which the branch to the new instruction sequence is highly probable, according to the present invention.
FIG. 8a is a block diagram of the central processing unit along with associated signals illustrating the operation of a portion of the implementation of a conditional branch macroinstruction.
FIG. 8b is a block diagram of the central processing unit along with associated signals illustrating the operation of the remainder of the conditional branch macroinstruction.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1. Detailed Description of the Figures
Figure 1 and Figure 2 have been described in relation to the related art.
Referring next to Figure 3, an organization for a central processing unit 10 implementing the pipelined execution of an instruction sequence is
shown. The central processing unit is divided into an instruction subunit 31 and associated control unit 32, an execution unit 33 and a cache (or local) memory unit 34. The cache memory unit 34 is coupled to the system bus 19 and exchanges groups of logic
signals with the other subsystems of the data processing system by means of the system bus under control of the control unit 32. The execution unit 33, again under control of the control unit 32, performs the manipulation of the data signal groups
that is defined by the instructions being executed.
The instruction unit receives the instructions to be executed and reformats the instructions in a manner that can be used to control the operation of the central processing unit. The reformatted instructions, or portions thereof, are applied to the control unit 32 to provide the configuration of the logic elements of the data processing unit to implement the operation defined by the instruction.
The structure defined above supports the use of
microinstructions to implement macroinstructions. A macroinstruction can be implemented by a single microinstruction or by a plurality of microinstructions depending on the complexity, the nature of the apparatus of the central processing unit, and similar parameters. It is the microinstructions that are divided into microinstruction segments, as shown in Fig. 2b. Each microinstruction includes "micro-orders" that control the groups of components.
Referring to the simplified division of the data processing unit shown in Figure 3 and for purposes of
illustrating the invention, the length of time for each unit of the central processing unit to complete its portion of an execution of an instruction will be taken to be equal. Thus, for an instruction to be executed by the data processing unit, the execution of a set of instructions is illustrated in Figure 2c.
The first instruction will be processed by the instruction unit during a first interval to. During the third interval t0, the cache memory unit can be processing instruction #1, the execution unit can be processing instruction #2, and the instruction unit can be processing instruction #3. This three level pipeline can continue as long as instructions are entered into the instruction unit.
It will be clear that the division of the data processing unit into the indicated functional units is, in general, not sufficient to provide an operable pipeline configuration. Each of the functional units described above can require a plurality of suboperations to complete the execution of each instruction. For purposes of illustration, a pipeline that includes four segments, instead of the three segments described with reference to Figure 3, will be used to describe the invention.
Referring next to Figure 4, the execution of an unconditional branch instruction is illustrated. The unconditional branch instruction forces the central processing unit to execute a new instruction sequence beginning at the instruction specified by the unconditional branch instruction. As indicated in
Figure 4, the unconditional branch macroinstruction 4010 is initiated, and the first of its corresponding microinstructions causes the apparatus of the central processing unit to retrieve the first macroinstruction of the target sequence of instructions. The next three instructions in the sequence instructions 4011, 4012, 4013, are "no operation" instructions in which the signals from the control unit do not result in activity that contributes to the execution of the instruction.
Microinstruction 4014 includes the "end instruction" micro-order completing the implementation of the unconditional branch macroinstruction and causing the central processing unit to begin execution of the target sequence of macroinstructions.
Referring next to Figure 5, the execution of a conditional branch macroinstruction instruction, in which the present invention is not used, is illustrated. In this process, the first
microinstruction implementing the macroinstruction can be condition testing microinstruction 5010. This instruction tests the condition of the conditional branch instruction. Because the result of the condition is not known until the end of the
instruction, execution of further processing is suspended until the results of the test have been determined. Thus, microinstructions 5011, 5012 and 5013 are "no operation" instructions. The conditional branch instruction determines a condition that can be true or false. If the condition is true, then the branch is made and the new instruction sequence is executed.
In the example of Figure 5, the unconditional branch instruction 5016 is executed and the instruction sequence of Figure 4 is
implemented. If the condition is false, then execution of the original instruct-ion sequence is continued. As illustrated in Figure 5, instructions 5015, etc. in the original instruction sequence are now executed.
Referring next to Figure 6, the execution of a conditional branch instruction according to the present invention is shown. Although this instruction sequence of the present invention implements a conditional branch macroinstruction, the individual microinstructions are not identical with the conditional branch instruction of Figure 4. The first microinstruction 6010 of the sequence includes the conditional branch micro-order. The instruction 6010, in addition to testing the condition, provides an address to the cache memory unit of the first instruction in the new sequence of instructions, in a
manner that the unconditional branch instruction would be implemented.
However, in distinction to the unconditional branch instruction in which three "no operation" instructions are found after the branch instruction, in the present invention, three microinstructions implementing original sequence are executed. By the end of the first segment of the third original sequence instruction, the determination of the truth or falsity of the condition has been determined, i.e. as indicated by the arrow in instruction 6010 in Figure 6. If the condition is false, the original microinstruction sequence continues as illustrated by instruction 6014. If the condition is true, then a one microinstruction branch trap routine 6015 is executed that changes the instruction sequence in execution to the new sequence as illustrated by instruction 6016.
In addition, the results of the instructions 6011, 6012 and 6013 are irrelevant and are discarded when the new sequence is selected by the condition.
Referring next to Figure 7, the execution of the conditional branch instruction, of the type having a high probability that the branch to the new sequence will be implemented, is illustrated This type of macroinstruction typically involves control of an instruction loop, where a multiplicity of macroinstructions will typically be executed
repeatedly before the macroinstruction sequence continues in a consecutive instruction sequence.
Instructions 7010 and 7011 are parameter determining microinstructions. Instruction 7012 determines the destination address if the condition is determined to
be true. Simultaneously with the determination of the destination address, instruction 7012 is also an unconditional branch instruction causing the execution of the new or target instruction sequence.
However, this conditional branch instruction provides
for the saving of the next address of the old sequence. As illustrated in Figure 4, the fourth instruction after the unconditional branch instruction 7013, instruction 7016, contains the end instruction micro-order. Then the next following instruction 7017 is the first instruction of the new sequence. Rather than three "no operation" instructions in the unconditional instruction branch sequence, one of the instructions, 7015, is a conditional branch instruction of the type illustrated in Figure 6. In addition, instructions 7013 and 7014 can be part of a microinstruction sequence implementing a macroinstruction.
It will be clear that the situation with respect to the condition will now be reversed, the unconditional branch instruction causing the potential new instruction sequence to be the active instruction
sequence. However, should the relatively rare situation, where the original sequence was to be continued, be identified by the conditional branch instruction, the address of that instruction was saved in instruction 7012. Also when the original instruction sequence is to be continued, the results of the executed new sequence instructions, 7017, 7018 and 7019, will not be used.
Referring next to Figure 8a, a block diagram of the apparatus executing a conditional branch macroinstruction is shown. The macroinstruction(s) are applied to instruction subunit 31. Each macroinstruction is decoded and the resulting address signals, implementing the macroinstruction, are applied to control unit 32. Based on the applied
address signals, microcode control signals from control unit 32 are applied to the execution subunit 33, the cache memory subunit 34 and the conditional branch logic 81. Conditional branch logic 81 is implemented to receive condition signals from the execution subunit 33 and, in response to the condition signals and the applied microcode control
signals, provide one of two output signals.
The microcode control signals cause the execution subunit 33 to process data signals and to produce condition signals that are applied to the conditional branch logic 81. As a result of the applied condition
signals and the microcode control signals, a resulting output signal (or signals) is generated from the conditional branch logic unit 81. In the present invention, when the condition is true (i.e.
the branch succeeds), a signal is applied to a selected portion of a microtrap logic unit 82. When the condition is false (i.e. the branch fails), signals are applied to the cache memory subunit 34 that cause the fetch operation, initiated by the control unit 32 in response to signals from the instruction sub unit 31, to be aborted.
Referring to Figure 8b, the result of the application of a signal to the microtrap logic, i.e.
the branch succeeds, is shown. The microtrap logic unit 82 sends a global trap signal to the instruction
subunit 31, the execution subunit 33, the cache subunit 34 and the control unit 32. The result of the global trap signal on the instruction subunit 31, the execution subunit 33 and the cache memory subunit 34 is to abort the results of the microinstructions for which execution was initiated after the conditional branch microinstruction. The effect of the global trap signal on the control unit 32 is to cause an address (trap vector), resulting from the "condition is true" signal being applied to the microtrap logic unit 82, from the microtrap logic to be used by the control unit 32.
The result of the trap vector is, inter alia, to provide a trap release signal to the microtrap logic unit 82 that terminates the routine being executed by the microtrap logic unit 82 as a result of the application of the "condition is true" signal.
2. Operation of the Preferred Embodiment
The delays involved in the conditional branch instruction are two-fold. First, the execution of the appropriate instruction sequence cannot be undertaken with certainty until a determination has been made as to the whether the condition is true or false. Second, even once the determination has been made with respect to the fulfillment of the condition, the various segments of the instruction must be processed, before the advantages of the rapid execution by a processor pipeline can be realized.
To avoid the delays that are involved with a conditional instruction in a pipeline type data processing environment, the present invention categorizes the conditional branch instruction into two groups.
In the first group of conditional branch instructions, the most probable result of the testing of the condition is unknown. The invention processes this type of conditional branch instruction by forcing the next instruction to be a retrieval of the data at the address that would be the result of an
actual branch in the program as a result of the instruction. Because this retrieval takes a plurality of microinstruction cycles to execute, the instructions that are executed in this time period are instructions from the original sequence that would be processed if a program branch did not take place as a result of the condition testing.
Thus, when the result of testing the condition is established, if the condition is false, i.e. the original program sequence is to be continued, then
the data in the process of being retrieved is cancelled and the original instruction sequence, already in execution, is continued. Indeed, according to the implementation in Figure 4, only one microinstruction cycle is used. If, on the other hand, the condition is true and the new sequence of instructions is to be executed, then the process of retrieving the first signal group of the new instruction sequence has been in progress for three microinstruction cycles, and the execution of this instruction sequence has improved with respect to waiting for result of the condition test prior to
further processor activity.
It will be clear that, if the codition is true, the results of the instruction execution sequence of the original program sequence taking place during the testing of the condition has become irrelevant and must be discarded. Thus, it will be clear that the speed of the conditional branch instruction of the present invention uses only one system clock cycle when the condition is false, and yet executes the instruction as fast as an unconditional branch instruction when the condition is true.
With respect to the second group of instructions illustrated in Figure 7, upon identification of a conditional branch instruction associated with this second group, the assumption is made that the branch to the new instruction sequence is the most probable result of the testing of the condition. As a result of this assumption, the conditional branch is interpreted as an unconditional branch instruction and the activity necessary for the performing the
branching operation is executed even though the condition has not been tested. After the new instruction sequence has been prepared for execution, then the instruction testing the condition is executed.
However, the condition testing procedure is now reversed, the condition for continuation has now become the condition for execution of a new
instruction sequence even though that instruction sequence is in fact the original instruction sequence. The execution of the conditional branch instruction takes place in the same manner as the execution of the conditional branch instruction illustrated in Figure 6. It will be clear that the assumption that the branch is the most probable result of the testing of the condition must in fact be true in a majority of cases. This result arises because, as will be apparent from Figure 7, two
alterations in the instruction sequence must take place when the original condition is false.
The conditional branch instruction improves the execution of the instruction by forcing an unconditional branch micro-order to be executed as soon as the second (branch) address is known and by using the previously described conditional branch instruction to minimize the impact of the (relatively unlikely) return to the original instruction sequence.
The foregoing description is included to illustrate the operation of the preferred embodiment and is not meant to limit the scope of the invention.
The scope of the invention is to be limited only by the following claims. From the foregoing description, many variations will be apparent to those skilled in the art that would yet be encompassed by the spirit and scope of the invention.
Claims
What is Claimed is:
1. The method for implementing a conditional branch program sequence comprising the steps of:
executing a first microinstruction that determines whether a condition is true;
implementing said first microinstruction to
begin a memory fetch for a branch instruction sequence;
continuing execution of a non-branch sequence of
instructions prior to a completion of said first microinstruction; and
upon completion of said first microinstruction,
executing a microinstruction causing execution of said new instruction sequence when said condition is true.
2. The method of implementing the conditional branch
program of Claim 1 further comprising the step of continuing said execution of said non-branch sequence when said condition is false.
3. The method of implementing a conditional branch in a macroinstruction sequence comprising the steps of:
executing an unconditional branch and
determining a destination address by a first microinstruction;
prior to completion of said first
microinstruction wherein execution of a new
instruction sequence is begun, executing a conditional branch instruction; and
continuing execution of said new instruction sequence when a condition is determined to be false.
4. The method of implementing a conditional branch in a macroinstruction sequence further including the
step of returning to said original instruction sequence when said condition is true.
5. In a microprogrammed data processing unit,
apparatus for implementing a conditional branch
macroinstruction in a central processing unit
including an instruction subunit, an execution subunit and a cache memory subunit, comprising:
logic means responsive to a first microinstruction and preselected data signal groups for determining condition signals and for initiating a fetch of a predetermined instruction sequence;
branch logic means responsive to said condition
signals and to said first microinstruction for
providing a one of a first signal and a second signal; and
trap logic means responsive to said first signal for aborting activity not related to said fetch of a
predetermined instruction sequence, in said instruction subunit, said execution subunit, and said cache memory subunit.
6. The conditional branch apparatus of Claim 5
further including means responsive to said first signal for enabling said trap logic means.
7. The conditional branch apparatus of Claim 5
further including means responsive to said second
signal for aborting said predetermined instruction sequence fetch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US82377686A | 1986-01-29 | 1986-01-29 | |
| US823,776 | 1986-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1987004821A1 true WO1987004821A1 (en) | 1987-08-13 |
Family
ID=25239679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1987/000178 WO1987004821A1 (en) | 1986-01-29 | 1987-01-29 | Apparatus and method for execution of branch instructions |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0290465A1 (en) |
| JP (1) | JPH01500066A (en) |
| AU (1) | AU7021387A (en) |
| CA (1) | CA1285657C (en) |
| WO (1) | WO1987004821A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2631471A1 (en) * | 1988-05-11 | 1989-11-17 | Nec Corp | MEMORY-BUFFER CONTROL CIRCUIT FOR DATA PROCESSING MACHINE |
| US4882701A (en) * | 1985-08-22 | 1989-11-21 | Nec Corporation | Lookahead program loop controller with register and memory for storing number of loop times for branch on count instructions |
| WO1999004335A2 (en) * | 1997-07-21 | 1999-01-28 | Telefonaktiebolaget Lm Ericsson (Publ) | A method and a processor adapted for the handling of conditional jumps |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4200927A (en) * | 1978-01-03 | 1980-04-29 | International Business Machines Corporation | Multi-instruction stream branch processing mechanism |
| EP0162778A2 (en) * | 1984-05-21 | 1985-11-27 | Digital Equipment Corporation | Instruction prefetch system for conditional branch instruction for central processor unit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56140445A (en) * | 1980-04-01 | 1981-11-02 | Hitachi Ltd | Information processing device |
| US4373180A (en) * | 1980-07-09 | 1983-02-08 | Sperry Corporation | Microprogrammed control system capable of pipelining even when executing a conditional branch instruction |
| JPS57153342A (en) * | 1981-03-19 | 1982-09-21 | Mitsubishi Electric Corp | Pipeline computer |
| JPS6049339A (en) * | 1983-08-30 | 1985-03-18 | Dainippon Screen Mfg Co Ltd | Editing device for copy image |
-
1987
- 1987-01-28 CA CA000528348A patent/CA1285657C/en not_active Expired - Fee Related
- 1987-01-29 EP EP19870901236 patent/EP0290465A1/en not_active Ceased
- 1987-01-29 WO PCT/US1987/000178 patent/WO1987004821A1/en not_active Application Discontinuation
- 1987-01-29 JP JP50122387A patent/JPH01500066A/en active Granted
- 1987-01-29 AU AU70213/87A patent/AU7021387A/en not_active Abandoned
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4200927A (en) * | 1978-01-03 | 1980-04-29 | International Business Machines Corporation | Multi-instruction stream branch processing mechanism |
| EP0162778A2 (en) * | 1984-05-21 | 1985-11-27 | Digital Equipment Corporation | Instruction prefetch system for conditional branch instruction for central processor unit |
Non-Patent Citations (2)
| Title |
|---|
| Computing Surveys, Volume 9, No. 1, March 1977, (New York, US) C.V. RAMAMOORTHY et al.: "Pipeline Architecture", pages 61-102, see page 81, left-hand column, lines 11-30 * |
| IBM Technical Disclosure Bulletin, Volume 22, No. 12, May 1980, (New York, US), J.J. LOSQ: "Asymmetric Double Decode Computer", pages 5536-5538, see page 5536 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4882701A (en) * | 1985-08-22 | 1989-11-21 | Nec Corporation | Lookahead program loop controller with register and memory for storing number of loop times for branch on count instructions |
| FR2631471A1 (en) * | 1988-05-11 | 1989-11-17 | Nec Corp | MEMORY-BUFFER CONTROL CIRCUIT FOR DATA PROCESSING MACHINE |
| WO1999004335A2 (en) * | 1997-07-21 | 1999-01-28 | Telefonaktiebolaget Lm Ericsson (Publ) | A method and a processor adapted for the handling of conditional jumps |
| WO1999004335A3 (en) * | 1997-07-21 | 1999-04-08 | Ericsson Telefon Ab L M | A method and a processor adapted for the handling of conditional jumps |
Also Published As
| Publication number | Publication date |
|---|---|
| AU7021387A (en) | 1987-08-25 |
| JPH0350295B2 (en) | 1991-08-01 |
| CA1285657C (en) | 1991-07-02 |
| EP0290465A1 (en) | 1988-11-17 |
| JPH01500066A (en) | 1989-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5235686A (en) | Computer system having mixed macrocode and microcode | |
| US4584640A (en) | Method and apparatus for a compare and swap instruction | |
| US4594659A (en) | Method and apparatus for prefetching instructions for a central execution pipeline unit | |
| US3736567A (en) | Program sequence control | |
| US5325495A (en) | Reducing stall delay in pipelined computer system using queue between pipeline stages | |
| US5628018A (en) | Data processing apparatus handling plural divided interruption | |
| US5008807A (en) | Data processing apparatus with abbreviated jump field | |
| US5095426A (en) | Data processing system for effectively handling exceptions during execution of two different types of instructions | |
| JPH0139132B2 (en) | ||
| CA1061910A (en) | Microprogrammable device | |
| US4679138A (en) | Microsequencer in a data processing system using stack storage for controlling the sequencing of microroutines | |
| EP0592404A1 (en) | Apparatus and method for providing a stall cache | |
| EP0279953B1 (en) | Computer system having mixed macrocode and microcode instruction execution | |
| WO1987004821A1 (en) | Apparatus and method for execution of branch instructions | |
| US4742449A (en) | Microsequencer for a data processing system using a unique trap handling technique | |
| EP0500193A1 (en) | Apparatus and method for execution of branch instructions | |
| US4794527A (en) | Microprogrammed data processing system using latch circuits to access different control stores with the same instruction at different times | |
| US7130988B2 (en) | Status register update logic optimization | |
| EP0290466B1 (en) | Method and apparatus for requeueing trapped microaddresses in a pipelined data processing system | |
| IE880818L (en) | Apparatus and method for synchronization of arithmetic¹exceptions in central processing units having pipelined¹execution units simultaneously executing instructions | |
| JP2000194556A (en) | Instruction look-ahead system and hardware | |
| US6360310B1 (en) | Apparatus and method for instruction cache access | |
| CA1233271A (en) | Cache disable for a data processor | |
| JPS5896345A (en) | Hierarchical arithmetic system | |
| JPH0561660B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): AU BR JP |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1987901236 Country of ref document: EP |
|
| WWP | Wipo information: published in national office |
Ref document number: 1987901236 Country of ref document: EP |
|
| WWR | Wipo information: refused in national office |
Ref document number: 1987901236 Country of ref document: EP |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 1987901236 Country of ref document: EP |