WO1987004854A3 - Liquid epitaxial process for producing three-dimensional semiconductor structures - Google Patents

Liquid epitaxial process for producing three-dimensional semiconductor structures Download PDF

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Publication number
WO1987004854A3
WO1987004854A3 PCT/EP1987/000064 EP8700064W WO8704854A3 WO 1987004854 A3 WO1987004854 A3 WO 1987004854A3 EP 8700064 W EP8700064 W EP 8700064W WO 8704854 A3 WO8704854 A3 WO 8704854A3
Authority
WO
WIPO (PCT)
Prior art keywords
monocrystalline
semiconductor structures
dimensional semiconductor
openings
epitaxial process
Prior art date
Application number
PCT/EP1987/000064
Other languages
German (de)
French (fr)
Other versions
WO1987004854A2 (en
Inventor
Elisabeth Bauser
Horst Paul Strunk
Original Assignee
Elisabeth Bauser
Horst Paul Strunk
Max Planck Gesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elisabeth Bauser, Horst Paul Strunk, Max Planck Gesellschaft filed Critical Elisabeth Bauser
Publication of WO1987004854A2 publication Critical patent/WO1987004854A2/en
Publication of WO1987004854A3 publication Critical patent/WO1987004854A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02625—Liquid deposition using melted materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Abstract

The process described enables the production of monocrystalline semiconductor layers having a high degree of crystal perfection in a multi-layer arrangement on intermediate layers of an insulating material and/or carbone and/or metal, in order to produce three-dimensional semiconductor structures which offer low mechanical stresses and load-bearing densities of between 1014 and 1021 per cm3. Very low manufacturing temperatures can be used, for exemple between 300 and 900°C. The seeding for each epitaxial layer is performed in the openings of the intermediate layer where a monocrystalline material is located in a free state. From these openings, the lateral and monocrystalline growth of the intermediate layers takes place. The repeated application of the liquid epitaxial process described allows three-dimensional integration in monocrystalline multilayer structures which are extremely devoid of defects.
PCT/EP1987/000064 1986-02-11 1987-02-11 Liquid epitaxial process for producing three-dimensional semiconductor structures WO1987004854A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3604260.9 1986-02-11
DE19863604260 DE3604260A1 (en) 1986-02-11 1986-02-11 LIQUID EPITAXIAL PROCEDURE

Publications (2)

Publication Number Publication Date
WO1987004854A2 WO1987004854A2 (en) 1987-08-13
WO1987004854A3 true WO1987004854A3 (en) 1988-03-24

Family

ID=6293866

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1987/000064 WO1987004854A2 (en) 1986-02-11 1987-02-11 Liquid epitaxial process for producing three-dimensional semiconductor structures

Country Status (4)

Country Link
EP (1) EP0255837A1 (en)
JP (1) JPS63502472A (en)
DE (1) DE3604260A1 (en)
WO (1) WO1987004854A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US4863877A (en) * 1987-11-13 1989-09-05 Kopin Corporation Ion implantation and annealing of compound semiconductor layers
FR2629636B1 (en) * 1988-04-05 1990-11-16 Thomson Csf METHOD FOR PRODUCING AN ALTERNATION OF LAYERS OF SINGLE-CRYSTAL SEMICONDUCTOR MATERIAL AND LAYERS OF INSULATING MATERIAL
JP3016432B2 (en) * 1989-09-21 2000-03-06 沖電気工業株式会社 Semiconductor substrate manufacturing method
US5796119A (en) * 1993-10-29 1998-08-18 Texas Instruments Incorporated Silicon resonant tunneling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028147A (en) * 1974-12-06 1977-06-07 Hughes Aircraft Company Liquid phase epitaxial process for growing semi-insulating GaAs layers
EP0143957A1 (en) * 1983-10-28 1985-06-12 Siemens Aktiengesellschaft Process for making A3B5 light-emitting diodes
US4551394A (en) * 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51126048A (en) * 1975-01-31 1976-11-02 Hitachi Ltd Hetero epitaxial growth method of iii-v group semi-conductors
JPS51138180A (en) * 1975-05-26 1976-11-29 Nippon Telegr & Teleph Corp <Ntt> Distributed feedback type semi-conductor laser and the method of manuf acturing it
JPS6040719B2 (en) * 1979-03-30 1985-09-12 松下電器産業株式会社 semiconductor laser equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4028147A (en) * 1974-12-06 1977-06-07 Hughes Aircraft Company Liquid phase epitaxial process for growing semi-insulating GaAs layers
EP0143957A1 (en) * 1983-10-28 1985-06-12 Siemens Aktiengesellschaft Process for making A3B5 light-emitting diodes
US4551394A (en) * 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
Applied Physics Letters, Band 38, Nr. 5, Marz 1981, (New York, US), P.C. CHEN et al.: "Embedded Epitaxial Growth of Low-Threshold GaInAsP/InP Injection Lasers", seiten 301-303 siehe das ganze dokument *
IBM Technical Disclosure Bulletin, Band 15. Nr. 3, August 1972, (New York, US), J.M. BLUM et al.: "Integrated Light Emitting pnpn and npn Devices", seiten 951-952 siehe das ganze dokument *
Japanese Journal of Applied Physics, Band 6, Nr. 7, Juli 1967, (Tokyo, JP), T. NAKANO: "Preparation and Properties of GaAs-Si Heterofunctions By Solution Growth Method", seiten 854-863 *
Journal of the Electrochemical Society, Band 12., Nr. 12, Dezember 1982, (Manchester, New Hampshire, US), B. Jayant Baliga: "Refilling Silicon Grooves by Liquid Phase Epitaxy", seiten 2819-2823 siehe seiten 2820-2822: "Experimental Procedure and results", abbildungen 1-10 *
Journal of the Electrochemical Society, Band 133, Nr. 1, Januar 1986, (Manchester, New Hampshire, US), B. JAYANT BALIGA: "Silicon Liquid Phase Epitaxy", Seiten 5C-14C siehe abschitt: "Apparatus and Experimental Procedure"; seite 9C; abschnitt: "Epixal Refill"; seiten 12C-13C; abbildungen 12-14 *
Solid State Technology, Band 27, Nr. 9, September 1984, (Port Washington, New York, US), L. JASTRZEBSKI: "Silicon CUD for SOI: Priciples and Possible Applications", seiten 239-243 *

Also Published As

Publication number Publication date
JPS63502472A (en) 1988-09-14
DE3604260A1 (en) 1987-08-13
WO1987004854A2 (en) 1987-08-13
EP0255837A1 (en) 1988-02-17

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