WO1987006060A1

WO1987006060A1 - Method for joining two or more wafers and the resulting structure

Info

Publication number: WO1987006060A1
Application number: PCT/US1987/000694
Authority: WO
Inventors: William I. Lehrer
Original assignee: Fairchild Semiconductor Corporation
Priority date: 1986-03-28
Filing date: 1987-03-27
Publication date: 1987-10-08

Abstract

A composite three dimensional electrically functioning integrated circuit semiconductor structure which achieves increased packing density of electrical components through the ability to form electrical circuits on at least two levels is provided by bonding together at least two semiconductor wafers (211) and (212a) or (212b) by a bonding means (216) having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the semiconductor wafers being bonded. The equality of the thermal expansion and contraction coefficients of the bonding means and the semiconductor wafers enables the composite semiconductor structure to withstand elevated processing temperatures and further protects epitaxial cells formed in said semiconductor wafers from thermal deformation and drift during heating of the composite structure to elevated temperatures such as are necessary for oxidation and annealing.

Description

-l-

METHOD FOR JOINING TWO OR MORE WAFERS AND THE RESULTING STRUCTURE

BACKGROUND OF THE INVENTION.

Field of the Invention. This invention relates to semiconductor devices and in particular to a semiconductor structure comprising at least one semiconductor wafer joined to another semiconductor wafer or to an appropriate substrate of a selected material such as insulation, by a material which withstands the temperatures to which the wafer is subjected during the processing of the wafer to form integrated circuits and which has a temperature coefficient of expansion and contraction which substantially matches that of the at least one semiconductor wafer.

Background of the Invention. Numerous techniques have been proposed to increase the packing density of integrated circuits and to increase the complexity of semiconductor structures. Thus, Peltzer in U.S. Patent No. 3,648,125 forms isolated pockets of semi- conductor material by forming an epitaxial layer of one conductivity type on a substrate of another conductivity type to create a laterally extending PN junction, forming grooves part way through the epitaxial layer in the pattern desired for the isolation and then thermally oxidizing the grooves through to the underlying laterally extending PN junction to thereby form a plurality of electrically isolated pockets of epitaxial semiconductor material. Another technique of increasing the packing density (Frescura et al. , U.S. Patent No. 3.489,961) forms grooves in epitaxial semiconductor material of one conductivity type through to an underlying semiconductor substrate of opposite conductivity type. The grooves laterally surround and isolate islands of semiconductor material. A third approach (Tucker and Barry, U.S. Patend No. 3,736,193) involves the formation of a grid of oxide (either doped or undoped) on a semiconductor substrate in the pattern desired for the isolation regions of the resulting integrated circuit, and then depositing silicon on the substrate from, for example, the decomposition of silane in a carrier gas. Epitaxial silicon forms over the exposed portions of the substrate while polycrystalline silicon forms over the oxide grid. The polycrystalline silicon is either doped simultaneously from dopant contained in the underlying oxide with an impurity selected to change the conductivity type of the polycrystalline silicon to be opposite to the conductivity type of the epitaxial silicon, or is subsequently doped with such an impurity. One of the disadvantages of the above structures is that while the circuitry extends in two dimensions over the wafer surface and includes active and passive regions forming diodes, transistors, resistors and/or capacitors in the underlying semiconductor material, only one layer of circuitry is formed. The combination of two semiconductor wafers to form an electrical circuit is disclosed in Wallia, U. S. Patent 3,764,950. Wallia forms an analog circuit on one semi- conductor wafer and forms cavities in an adjacent semicon- ductor wafer. The two wafers are then joined using a glass (disclosed in Wallia as a low-expansion, low-melting zinc phosphovanadate glass composition) to place the active circuitry on one wafer adjacent the cavities in the other wafer such that the resulting structure will function as a pressure transducer containing internal to the transducer the electrical circuits necessary to amplify the signals generated by changes in the pressure on the cavity. One portion of the silicon wafer formed over the cavity is processed to possess electrical characteristics which are dependent upon the pressure applied to the cavity. Again, however, the electrical circuitry in the Wallia structure is formed only on one of the silicon wafers. -^• Another defect of the Wallia patent lies in the

² decomposition of the zinc phosphovanadate system at

3 diffusion temperatures. Typically, vanadate systems tend to

4 break down at the elevated temperatures usually employed for

5 diffusion processing.

6 One of the problems of prior art structure such as

7 Wallia's is that the material used to join the two semi-

8 conductor wafers often has a different thermal expansion and

9 contraction coefficient from that of the silicon wafers. 0 Accordingly, temperature cycling of the structure creates 1 thermal stresses and hysteresis which degrades performance. 2 3 Summary of the Invention. 4 This invention overcomes the disadvantages of the prior 5 art and provides a structure which achieves both increased 5 packing density of electrical components through the ability 7 to form electrical components on more than one layer of the 8 resulting structure and which provides a material for the 9 joining of two or more wafers into a composite structure 0 which material has substantially the same thermal expansion i and contraction coefficient of the silicon wafers being^* 2 joined and is able to withstand diffusion temperatures. 3 The present invention resulted from experimental research which demonstrated that various binary combinations 5 atop one another do not mix, or show little diffusion even 5 when one of the layers is melted. The present invention 7 represents the ideal graded junction structure which can be _a conveniently fabricated by various processes. 9 In accordance with this invention, a special glass 0 which I denote as PVX/II but which comprises essentially a mixture of germanium oxide and silicon oxide (i.e. Geθ2 and Si0₂) is provided which has a thermal expansion and contraction coefficient substantially equal to the 3 corresponding coefficient for silicon. This material 4 comprises a semiconductor oxide binary system which is well 5 suited for elevated temperature cycling with no apparent 6 breakdown with proper processing in a neutral (i.e. non- 7 reactive) atmosphere. 8 In accordance with this invention, two or more wafers are capable of being joined using my unique glass material wherein each of the two or more wafers has formed in it selectively doped regions of semiconductor materials such that when these regions are interconnected a composite three dimensional electrically functioning structure is obtained. As a feature of this invention, isolated pockets of epitaxial silicon material are formed on an underlying substrate of selected conductivity. To achieve this, an epitaxial layer is grown on an underlying substrate of a selected conductivity and then covered with selected layers of glass or other materials. In one embodiment, the other materials can comprise a conductive plane of selectively doped polycrystalline silicon or of conductive ceramic. A bonding glass in accordance with this invention is then placed over the conductive plane or the epitaxial layer and the structure is bonded by means of this glass to another substrate, such as a wafer of semiconductor material of selected conductivity type. The structure is then etched to remove. the particular substrate on which the epitaxial layer was initially grown and the epitaxial layer is selectively masked and etched to leave isolated islands of epitaxial material formed over either the bonding glass or the con- ductive plane. If desired the conductive plane can be selectively patterned to allow electrical contact to be made through openings in the conductive plane to the semiconduc- tor material joined to the conductive plane by the bonding glass of this invention. In another embodiment, at least one wafer is bonded to an appropriate substrate of another material such as insula- tion by the bonding glass of this invention. This invention will be more fully understood in light of the following detailed description taken together with the drawings.

Description of the Drawings. Figures 1a through 1f illustrate a structure manufactured in accordance with this invention using the -_ bonding glass of this invention.

2 Figure 2 illustrates a structure produced in accordance

3 with this invention using the bonding glass of this

4 invention.

5 Figures 3 through 3d illustrate an alternative

6 embodiment of this invention wherein the epitaxial silicon

7 islands are secured on the bonding glass against relative 3 movement during subsequent heating of the device.

9 0 Detailed Description 1 Figures 1a through 1f illustrate a process for the 2 manufacture of a semiconductor substrate utilizing the 3 bonding glass or "glue" of this invention. While several 4 different structures utilizing the bonding glass of this 5 invention will be described, it should be understood that 5 these structures are illustrative only and are not meant to 7 limit the applications of the invention. Within the germanium oxide (GeOg) - silicon oxide ₉ (Si0₂) system of the present invention, a range of expansion 0 coefficients exist that can be sequentially deposited i forming a "graded junction". The gradient range extends 2 from approximately 0.5 x 10^"° (Si0₂) to approximately 3 8 x 10^"° (Ge0₂). Therefore, it would be feasible to 4 consider bonding silicon to any material within that 5 range. Accordingly, the materials listed in Table 1 are 5 suitable for bonding to silicon. 7 8 TABLE 1 9 Materials Expansion Coefficient 0 Diamond 1.18 10 ^•6

Iridium 5.71 10 ^■6 1 Molybdenum 5.5 x 10 -6 2 Nickel Steel 6.0 x 10^"6

Invar 0.9 X lθ^"D m 3 Various Ceramics 1.6 to 5.5 x 10~° 4 T Tuunnggsstteenn 4.6 x 10^"°

Silicon Carbide (SiC) 4.7 x 10^"° 5 6

However, the list of materials in Table 1 is not 7 exhaustive. The most interesting applications for bonding 8 various materials to silicon relate to the bonding of ceramic materials for packaging, and the bonding of molydbenum and tungsten for the formation of electrically conductive interconnects. Turning to Figures 1a through 1f, one process utilizing the bonding glass of this invention begins with a substrate 11 shown as N+ type semiconductor material. While substrate 11 and the subsequent layers of materials to be formed on substrate 11 to comprise wafer 10 will be described as having specific conductivity types, it should be recognized that other conductivity types than those illustrated can also be used, if desired and appropriate. An N type epitaxial layer 12 is then formed on N+ substrate 11 using standard well known techniques for the formation of epitaxial layers. Following the formation of N type epitaxial layer 12, a layer of oxide 13 (Figure 1b) is formed on the surface of epitaxial layer 12 typically by thermal oxidation methods. Then in accordance with this invention a layer of bonding glass 1 a is placed over oxide 13- In one embodiment, bonding glass 14a comprises a 45/55$ (percent by weight) mixture of Ge0₂ and Si0₂. Experiments using the well-known bending beam method showed no substantial difference in the temperature coefficient of expansion of this glass (denoted by me as PVX/II) to that of silicon. The temperature coefficient of expansion of this glass nominally matched that of silicon within experimental error. That is, by the "bending beam method" no difference could be found in the thermal coefficient of expansion of the glass and the underlying silicon wafer. In accordance with this invention, glass layer 1 a is formed to a selected thickness, in one embodiment 10 microns. Glass layer 14a can also be doped if desired with phosphorus (typically - % P2°5 ^Dy weight). Coating was carried out by melting standard phosphovapox glass 14a formed in a manner well known in the art at 1000°C atop oxide layer 13 on wafer 10. In addition, a wafer 15 (not shown in Figure 1b but shown in Figure 1c after being joined to wafer 10) has formed on it the bonding glass of this invention, PVX/II similarly doped with a nominally ~\% ^~ ~ ~ 5 to a thickness of 10 microns. The bonding glass of this invention comprising the 45/55 mole percent Ge0₂/Si0₂ is formed at about 750-850°C. The present invention utilizes a chemical vapor deposition (CVD) coating method. The coating can be accomplished by atmospheric chemical vapor deposition (ACVD) , plasma assisted chemical vapor deposition (PACVD), and possibly by low pressure chemical vapor deposition (LPCVD) for certain compositions. Other feasible coating methods include spin-^on or dip coating glass solutions or the sedimentation of glass powders. Both the CVD and the spin-on coating methods are useful to form submicron thicknesses, while the sedimentation method would be principally applicable at mil (thousandths of an inch) thicknesses. The wafers 10 and 15 are joined (Figure 1c) in air by facing the coating layers 14a and 1 b and remelting these layers at 1000°C in air for 30 minutes. The resulting structure appears as shown in Figure 1c. Next, the N+ substrate 11 is removed by use of a selective etch. The method of etching has been described in Muraoka et al., "Controlled Preferential Etching Technology" Semiconductor Silicon 1973, ECS, Princeton, New Jersey, pp. 327, 338. The etchant solution employed consists of one part HF, three parts HNO3, and eight parts CH3COOH. The result is to leave exposed the back side of N type epitaxial layer 12 (i.e. the side of layer 12 originally facing and joined to N+ substrate 11). This structure is shown in Figure 1d. Next the back side of epitaxial layer 12 is thermally oxidized and then epitaxial layer 12 is used to fabricate semiconductor devices in accordance with teachings of the prior art. The structure (Figure 1d) comprises an epitaxial layer 12 formed on an oxide layer 13 overlying the glass 14 of this invention and supported by a substrate 15 of selected material. Typically substrate 15 comprises selectively doped or intrinsic silicon, a ceramic substrate or any other appropriate material possessing the desired thermal expansion and contraction coefficient and electrical properties. In accordance with one embodiment of this invention, the silicon layer 12 is selectively etched to form isolated islands 12a, 12b and 12c (Figure 1e) of isolated epitaxial silicon material. The epitaxial layer is etched using a standard hydrazine or catechol-type anisotropic solution. This etch stops on oxide and thus the oxide layer 13 serves as an automatic etch stop and allows the etch to be continued slightly longer than otherwise necessary to ensure clean removal of all epitaxial silicon in the areas being etched. Thus isolated pockets of epitaxial silicon such as pockets or islands 12a, 12b and 12c (sometimes called "cells") are formed. These cells can be reoxidized before further processing. Figure 1f illustrates the structure of Figure 1e with each of the cells 12a, 12b and 12c thermally oxidized to form oxide layers 13a, 13b and 13c over the exposed surfaces of these cells. It should be understood that each of the cells 12a, 12b and 12c of Figure 1e is laterally surrounded on all lateral sides by a groove or a moat 16a, 16b formed by the removal of all epitaxial silicon in the moat area. Since the bonding glass 14 or "glue" of this invention is capable of withstanding semiconductor processing temperatures, complete dielectrically isolated structures are formed. Thus the cells 12a, 12b and 12c of epitaxial material illustrated in Figure 1f can be further processed to form active devices in each of the cells. The moats 16a, 16b between the cells can be left unfilled and electrical interconnections (not shown) deposited over the oxide 13 to interconnect through vias (not shown) formed in oxides 13a, 13b and 13c, electrical connections to the electrical devices formed in the cells 13^a» ¹3b and 13c. Alternatively, the moat areas 16a, 16b between the cells 13a, 13b and 13c can be filled with a selected material such as a polycrystalline silicon or a glass such as phosphovapox. Processing the binary glass of the invention in an oxidizing ambient will, under some circumstances cause formation of a volatile germanium monoxide (GeO) which will reduce the percentage concentration of germanium in the binary glass system. This, however, is not a problem in most circumstances of practical importance and under normal conditions afects only the surface of the glass. Embodiments other than the one shown in Figures 1a through 1f are also possible. Thus, as shown in Figure 2, a second embodiment makes use of the moats 25 between cells 212a and 212b formed on bonding glass 216 to an underlying silicon substrate 211 to form an electrical connection from the top surface of a particular cell such as cells 212a and 212b to an underlying region 216 (typically diffused or ion implanted) in semiconductor material 211. The diffused region 216 can represent a portion of an active device such as a transistor or a diode or alternatively a diffused conductive or resistive region in semiconductor material 211. Metal interconnect layer 215 is then formed to interconnect region 214a formed in cell 212a by means of electrical contact 215a formed in a window in oxide 213a to electrical contact 215c formed in a window formed in bonding glass 216. Moreover, electrical contact 215b to diffused region 214b in cell 212b is also connected by means of interconnect 215 to electrical contact 215c. Thus regions 214a, 216 and 214b are electrically interconnected by electrical contacts 215a, 215c and 215b respectively and electrical interconnect 215. The structure shown in Figure 2 makes use of the anisotropic etching of an epitaxial layer which yields a 60° angle a (alpha) as shown between the sloped sides of cells 212a and 212b and the top surface of semiconductor material 211. Because of this 60° angle, the deposition of contact interconnect material 215 (typically aluminum but any other appropriate conductive material including a conductive metal silicide or selectively doped polycrystalline silicon can be used) is without the shadowing effects which result in shorts or weaknesses in the interconnect structure. Step coverage is thus not a problem in accordance with this invention. Another advantage is the fact that a three dimensional geometry has now been achieved which saves valuable silicon space allowing a higher packing density. Thus in the structure of Figure 2, region 216 can be part of an active device formed in semiconductor substrate 211 which is then joined by bonding glass 216 to the cell regions 212a and 212b of a different semiconductor wafer. Thus a true three-dimensional structure containing circuits on at least two levels has been achieved using the bonding glass 216 of this invention. Figures 3a through 3d illustrate an alternative embodiment of this invention which prevents the physical drift of discrete epitaxial cells 312a, 312b, 312c and 312d atop the bonding glass 313 of this invention when the structure is heated. One of the problems associated with this technology is the possibility that one or more of cells 312a through 312d could undergo thermal deformation and drift during subsequent heating of the device to elevated temperatures such as are necessary for oxidation and annealing. In order to mitigate discrete cell drift during some portion of the high temperature processing, a lower temperature formulation process could be employed, using a phosphorus doping of the bonding glass and joining the wafers at a temperature of approximately 800-850°C. Instead of phosphorus, antimony, arsenic or boron could be used to dope the bonding glass. Discrete cell drift could also be mitigated by the deposition of a higher temperature melting film such as Si0₂ (Vapox) that would fix all the cells in proper alignment for photomasking purposes. As shown in Figure 3a, a plurality of cells of epitaxial silicon 312a, 312b, 312c and 312d have been formed on bonding glass 313 which is in turn formed on the semiconductor substrate of base wafer 311. Of course, wafer 311 could, if desired, be some other appropriate material such as aluminum oxide (Al₂0g) or beryllium ceramic. In accordance with this invention, islands 312a through 312d are then covered with a layer 314 of a chemical vapor deposited oxide typically Si0₂. The melting point of Si0₂ is about 1600°C. Alternatively, germanium oxide, Ge0₂ (melting point 1100°C) or titanium oxide Ti0₂, (melting point 1640°C) or aluminum oxide, A1₂0,, (melting point 2050°C) could be used as well as other appropriate glasses. Then, following the deposit of glass layer 314, typically to a thickness of between 500 Angstroms and one or more microns, the underlying silicon islands 312a through 312d are either thermally oxidized through a chemical vapor deposited oxide or windows are etched in the chemical vapor deposited oxide to expose the silicon cells 312a through 312d to the oxidizing ambient. The latter structure is shown in Figure 3c where glass 314 has been partly removed to expose the top surfaces of cells 312a through 312d. Following the exposure of the top surfaces of the cells 3.12a through 31 d, these surfaces are then thermally oxidized to form thermal oxide layers 315a, 315b, 315c or.315d on the exposed portions of cells 312a through 312d. Standard wafer semiconductor processing techniques are then applied to form active and passive regions within each of cells 312a through 312d. ^' The deposited CVD oxide firmly positions the cells 312a through 31 d in position relative to each other and allows subsequent multiple photolithographic processing to continue without these cells slipping or sliding relative to each other in the high temperature processes. An advantage of use of germanium oxide as the chemical vapor deposited oxide is that it can be dissolved off with water which may be beneficial in some situations.

Example 1 Four inch wafers were "marker grooved", that is a small rectangular pattern was etched in each wafer to a depth of 4 microns. This was done to enclose all four sides using an 1 ISO/KOH etch so that the groove would signal the thickness

2 of the remaining layer after removing the back side of the

3 wafer.

4 Twenty microns of the bonding glass (PVX-II) of this

5 invention were deposited on the marker surface of these

6 wafers and also on blank substrate wafers.

7 The marker surface wafer and the blank substrate wafer

8 were then pressed together (PVX-II coat to PVX-II coat),

9 weighted with several slabs of quartz glass and melted

10 together in a muffled furnace at 1000°C for thirty minutes

11 in air. This resulted in a very tight bond. Note that

12 previously 40 microns of PVX-II was melted on to a silicon

13 wafer at 1000°C without any sign of cracking indicating a

14 very good thermal match.

15 Following gluing, the wafers were mounted on a wafer 16. grinder and the back of the grooved wafer was ground,

17 polished and chemically polished down to the marker groove

13 indicating a film thickness of 4 microns. This film was

19 then oxidized at a 1000°C to a 1000 angstrom thickness. The

20 structure was patterned in BOE (a standard oxide etch) and

21 the 4 micron thick silicon film was etched in ISO/KOH down

22 to the PVX-II glass bond leaving discrete islands of single

23 crystal silicon on the glass layer. The single crystal

24 silicon glass cells or islands were then reoxidized at 5 ^'1000°C for thirty minutes to a thickness of 300 to 400

26 angstroms.

27 The above example gives a structure with deep grooves 8 in the silicon that propogate into the glass layer. The 9 structure illustrated the utility of the process. Electro- 0 chemical etching could be used after grinding to further 1 thin down the back of the grooved wafer. 2 While several embodiments of this invention have been 3 described other embodiments will be obvious to those skilled 4 in the art in view of the above description. 5 6 7 8

Claims

I Claim :

1. An integrated circuit semiconductor structure comprising: at least two semiconductor wafers; and bonding means joining one of said at least two semiconductor wafers to another of said at least two semiconductor wafers, said bonding means possessing a thermal expansion coefficient substantially the same as the thermal expansion coefficient of said semiconductor wafers.

2. The structure of Claim 1 wherein said bonding means comprises a mixture of germanium oxide and silicon oxide.

3- The structure of Claim 1 wherein said at least two semiconductor wafers comprise a first semiconductor wafer and a second semiconductor wafer, said first semiconductor wafer comprising a semiconductor substrate of a given conductivity type, an epitaxial layer formed on said semiconductor substrate, and an oxide layer formed on said epitaxial layer, and said second semiconductor wafer comprising at least a semiconductor substrate.

4. The structure of Claim 3 wherein said bonding means in part is coated over the surface of said oxide layer on said first semiconductor wafer and in part is coated over the surface of said second semiconductor wafer and wherein said first and said second semiconductor wafers are joined with the surfaces of said first and second wafers on which is coated the bonding means facing each other.

5. The structure of Claim 1 wherein said at least two semiconductor wafers comprise a first semiconductor wafer and a second semiconductor wafer and said first semiconductor wafer comprises an epitaxial layer on which is formed an oxide layer, and said second semiconductor wafer comprises a semiconductor substrate, said substrate being joined to said oxide layer by said bonding means, said epitaxial layer being selectively removed through to said oxide layer to form a plurality of electrically isolated epitaxial silicon cells on said oxide layer.

6. The structure of Claim 5 wherein said bonding means has a thermal expansion coefficient substantially equal to the thermal expansion coefficient of said first and second semiconductor wafers thereby to withstand semiconductor processing temperatures and to allow formation of active and passive devices in said epitaxial silicon ceils.

7. The structure of Claim 5 wherein said epitaxial layer is selectively removed through to the underlying silicon oxide so as to form a plurality of discrete epitaxial cells each surrounded laterally by a moat.

8. The structure as in Claim 7 including selected active and passive devices formed in at least two of said plurality of discrete epitaxial cells and electrically conductive interconnects selectively formed between said at least two of said plurality of epitaxial cells.

9. The structure of Claim 8 wherein at least one active or passive device is formed in said second semiconductor wafer and wherein a selected number of said plurality of discrete epitaxial cells are adapted to be connected to said at least one active or passive device by said electrically conductive interconnects to form a unitary three dimensional semiconductor structure.

10. The structure of Claim 9 wherein the moat surrounding each cell in said plurality of discrete epitaxial cells forms a sufficient angle with said surface of said second semiconductor wafer to thereby eliminate shadowing effects on electrically conductive interconnect material deposited over said moat.

11. The structure of Claim 1 wherein said first semiconductor wafer comprises a plurality of discrete electrically isolated epitaxial silicon cells formed on said bonding means placed over the surface of said second semiconductor wafer, said bonding means being adapted to securely hold said plurality of epitaxial cells so as to prevent thermal drift of said cells during semiconductor processing.

12. A method for producing a three-dimensional integrated circuit structure with circuits on at least two levels by bonding together at least two semiconductor wafers comprising the steps of: forming a first semiconductor wafer including a substrate of a given conductivity type, overlain by an epitaxial layer of a different conductivity type, overlain in turn by an oxide layer; forming a second semiconductor wafer including at least a semiconductor substrate of a given conductivity type with at least one region of opposite conductivity type formed therein and extending to a first surface thereof; bonding said first semiconductor wafer to said second semiconductor wafer using a bonding means to join said oxide layer in said first semiconductor wafer to the first surface of said second semiconductor wafer.

13- The method according to Claim 12 further comprising the step of coating said bonding means over the surface of said oxide layer of said first semiconductor wafer and coating said bonding means over the surface of said second semiconductor wafer.

14. The method according to Claim 13 further comprising the step of joining together said first and r> second semiconductor wafers by facing the surfaces of said

4 first and second wafers on which is coated said bonding

5 means. 6

7 15. The method according to Claim 14 further

8 comprising the step of remelting said bonding means to

9 thereby form a unitary bonded semiconductor structure. 0 1

16. The method according to Claim 15 further comprising the step of removing said substrate of said first 3 semiconductor wafer to thereby expose the subjacent back side of said epitaxial layer. 5 6

17. The method according to Claim 16 further 7 comprising the step of selectively etching said epitaxial layer through to said silicon oxide layer of said bonding means to form a plurality of electrically isolated epitaxial silicon cells, on said silicon oxide layer.

18. The method according to Claim 17 further comprising the step of forming active devices in selected ones of said plurality of electrically isolated epitaxial silicon cells.

19. The method according to Claim 18 further comprising the step of forming vias in the oxide layer on said first semiconductor wafer to expose said at least one region of opposite conductivity type in said substrate of said second semiconductor wafer.

20. The method according to Claim 19 further comprising the step of forming electrically conductive interconnects between the active regions in selected ones of said plurality of cells in said first semiconductor wafer and said at least one region of opposite conductivity type in said substrate of said second semiconductor wafer to thereby create a three dimensional structure having electrically connected semiconductor regions formed on at least two levels.

21. The method of Claim 13 including the step of adjusting the melting point of said bonding means by selectively doping said bonding means with phosphorous.

22. The method of Claim 13 including the step of forming said bonding means from a mixture of titanium oxide glass and aluminum oxide glass.

23. The method of Claim 13 including the step of selecting said bonding means to have a thermal expansion and contraction coefficient substantially equal to the thermal contraction and expansion coefficients of said semiconductor wafers being bonded such that the bonded semiconductor structure is capable of withstanding elevated temperatures during further processing.

24. An integrated circuit semiconductor structure comprising: at least one semiconductor wafer; a substrate of a selected material having a coefficient of thermal expansion and contraction matching within a selected tolerance the coefficient of thermal expansion and contraction of said at least one semiconductor wafer; and bonding means joining said at least one semiconductor wafer to said substrate of a selected material, said bonding means possessing a coefficient of thermal expansion and contraction substantially the same as the coefficients of thermal expansion and contraction of said at least one semiconductor wafer and of said substrate.