WO1988001060A1

WO1988001060A1 - Integrated circuits and method of testing same

Info

Publication number: WO1988001060A1
Application number: PCT/GB1987/000530
Authority: WO
Inventors: Ian Philips
Original assignee: Plessey Overseas Limited
Priority date: 1986-07-25
Filing date: 1987-07-25
Publication date: 1988-02-11
Also published as: GB8618210D0; EP0277167A1; JPH01500927A

Abstract

The invention provides, in the manufacture of integrated circuits, the inclusion in each of the replica circuits, of a test circuit which, on test, provides a test measurable indicative of the inherent performance of the replica circuit and the relation to the process and/or model, of the replica circuits enabling tighter control of the manufacture or specification of the integrated circuits so made.

Description

INTEGRATED CIRCUITS AND METHOD OF TESTING SAME

TECHNICAL FIELD

The present invention concerns the manufacture of integrated circuits and in particular is addressed to the problem of testing circuits for conformity to a defined inherent performance (i.e. speed) specification.

The inherent performance of each replica circuit produced on a semiconductor wafer will differ with the location of that circuit relative *to the wafer and will vary also in a stochastic manner from wafer to wafer. It is thus necessary to provide test techniques capable of measuring inherent performance and to use the same to enable the selection of those replica circuits that are in conformity to specification. Further, the measured inherent performance can be correlated with the model derived in CAD (computer aided design) work and to parameters of the process used to fabricate the circuits enabling changes to be made to the model and/or the process, to exercise tighter control of the manufacturing specification. BACKGROUND ART

Hitherto, inherent performance measurement and "chip" selection has been based upon wafer probe-test sampling techniques. A typical sampling technique is illustrated in Figure 1. This depicts a section of a semiconductor wafer 1 on which a large number of replica circuits 3 have been produced. The array of replica circuits 3 includes a small number of test-dedicated circuits 5 substituted at selected array sites. The number of test-dedicated circuits 5 is usually small, typically five or so per wafer. Probes are then applied to these test circuits 5 and the inherent performance at the substitution sample sites measured. The inherent performance of the surrounding replica circuits 3 is then deduced on the basis of statistical analysis and the chips selected accordingly.

With modern step-by-step replication techniques, the aforesaid technique is no longer suitable and as an alternative to the test-dedicated circuits 5_r "drop-ins" 5a_ have been positioned not at substitute sites but at intermediate positions, lying thus in the scribe lane areas of the wafer 1 (See Figure 2).

Such techniques as aforesaid are now proving to be less than satisfactory, the more so as performance specifications become more stringent. There is a finite statistical probability that amongst the selected chips there will be found chips that do not conform to specification. It has been the practice to test also each chip for conformity to device function tests. Full function and accelerated testing techniques however are limited and such techniques are becoming increasingly more difficult as device function and logic complexity increases.

DISCLOSURE OF THE INVENTION

The present invention is intended as a remedy to the problem aforesaid.

In accordance with the invention thus there is provided a method of performance testing wherein, in the manufacture of integrated circuits, replica circuits produced are arranged in an array on a semiconductor wafer, characterised in that each replica includes, in addition to a device function circuit, a test-dedicated sub-circuit, this sub-circuit being capable of generating a test measurable that is dependent upon inherent performance.

Subsequent to the provision of test-dedicated sub-circuits as aforesaid, wafer probe tests may be applied and chips selected accordingly. Alternatively, the circuit design may provide that in subsequent packaging the sub-circuit is connected to device pins, and performance and function testing (and eventual selection) carried out thereafter. The test measurable may be analogue or may be digital and may be chosen thus to suit the test technique adopted. Examples of the measurable include a delay time or a frequency (both analogue), or a .TRUE./.FALSE, logic variable. BRIEF INTRODUCTION OF THE DRAWINGS

In the drawings accompanying this specifications-

Figures 1 and 2 illustrate in plan view, wafer sections adapted for known sample performance testing;

Figure 3 is a plan view of a wafer section modified for testing in accordance with this invention; and, inset, an enlarged view of a replica circuit;

Figures 4 to 6 are block schematic diagrams of test dedicated sub-circuits suitable for inclusion in the wafer construction shown in the preceding Figure.

DESCRIPTION OF EMBODIMENTS

In order that the invention may be better understood, embodiments of the invention will now be described and reference will be made to Figures 3 to 6 of the accompanying drawings. The description as follows is given by way of example only.

There is shown in Figure 3 a portion of a processed semiconductor wafer in which has been formed an array of replica circuits 3a_. Each replica circuit 3a_ includes, as usual, the device function circuit and may include other test-facility, e.g. logic test, sub-circuits. A distinguishing feature of the replica circuit 3a_ is the inclusion of a ^•performance' test-dedicated sub-circuit 5b.

The design of the sub-circuit 5b_ is not critical provided that it will generate a performance related parameter (i.e. the measurable). The form of this sub-circuit 5b thus may be optimised to suit the test strategy of the manufacturer. Possible implementations of this sub-circuit 5b_ are illustrated in Figures 4 to 6 and will now be described.

A first of these implementations, a simple delay measurement sub-circuit 5b, is illustrated In Figure 4. This circuit 5b_ consists of a chain of inverters Iτ_, 12' ••• I_n each with suitable impedance loading C^, C2'....C_n (The impedance values here are chosen so as to limit the average interconnect loading typical of the device function circuit). Under test conditions, and using ancillary test-apparatus, an interrogation pulse is applied to the sub-circuit 5b input I/P and the propagation delay to output O/P measured. For convenience of measurement and to bring the delay within measurable limits, a large number n of inverters would be incorporated in the chain. Twenty or more inverters, typically, might be used. Absolute time delay measurement will in general be less than ideal as delays will be inserted by the connected apparatus. Differential measurement techniques would be preferred therefore. More accurate delay measurements thus may be achieved using by-pass or alternative length switching techniques. t

Parallel chains of different lengths (i.e. of inverter content n) could be provided for this purpose. A second of these implementations, a ring oscillator 5b' is illustrated in Figure 5. The design of this sub-circuit 5b_" is similar to that of the preceding figure, but an odd number (n = 2m + 1) of inverters I are utilised and feedback is provided. The number n of inverters I would normally be in excess of 10, and odd. The output measurable in this case, is a frequency which is, in turn, a function of the individual gate delay. The sub-circuit 5b_' may also include frequency division circuitry (not shown) to facilitate measurement. An "OR" or an "AND" gate may be substituted at one of the inverter gate positions. This substitution will allow oscillation to be stopped, to prevent circuit noise and to reduce integrated circuit power consumption.

A thir and preferred implementation, a frequency meter 5b_", is illustrated in Figure 6. This sub-circuit is particularly suited for use in conjunction with a digital tester. In addition to a ring oscillator 5b* (Figure 5) this sub-circuit 5b" thus includes circuitry to enable interfacing to digital testers. As shown, the output of the oscillator 5b' is fed to a counter 7 and oscillator stop and counter reset functions are controlled via an inverter 9 connected at sub-circuit input I/P. Input signal and counter output are referred to a pulse conincidence detector. Under test, a "Go" signal starts the oscillator and the oscillator cycles are counted. Should the count reach a predetermined value during an input determined interval, a coincidence will be detected and a .TRUE, digital output generated. The width of the "Go" signal pulse can be varied systematically to allow measurement of ring oscillator frequency or to check that such frequency lies within specified limits.

It will be appreciated that the method and circuit above described have application inter alia to the quality control testing of gate array and cell-library based circuits . It is also possible to use the same to sort devices to meet the high and the low performance specifications of different customers .

Claims

1. A method of testing the performance of an integrate circuit wherein, in the manufacture of a plurality of integrated circuits on a semiconductor wafer, replica circuits are reproduced in an array on the wafer, each replica circuit providing one of the integrated circuits characterised in that each replica includes, in addition to the integrated circuit, a test-dedicated sub-circuit capable of generating a test measurable dependant upon inherent performance.

_.

2. A method as claimed in Claim 1 further including th step of applying test probes to the or selected ones of the integrated circuit, determining the test measurable, and selecting those integrated circuits having an acceptable test measurable.

3. A method as claimed in Claim 1 including the steps of, in packaging each of the integrated circuits, connecting the sub-circuit to device pins, determining t test measurable for each or selected ones of the package integrated circuits by connecting the said device pins t a test apparatus, and selecting those integrated circuit having an acceptable test measurable.

4._ A method as claimed in Claim 1, 2 or 3 wherein the sub-circuit, on test, produces an analogue test measurable.

5. A method as claimed in any of claims 1 to 4 wherein the test measurable includes a delay time thereby giving an indication of the inherent speed of the integrated circuit associated therewith.

6. A method of testing the performance of an integrated circuit substantially as hereinbefore described.

7. A semiconductor wafer having thereon a pluraltiy of replica circuits in an array, each replica circuit including, in addition to an integrated circuit arranged to provide a device function, a test-dedicated sub-circuit, for providing, on test, a test measurable dependent upon the inherent performance.

8. A wafer as claimed in Claim 7 wherein, the sub-circuit provides, on test, an analogue test measurable.

9. A wafer as claimed in Claim 7 or Claim 8 wherein the sub-circuit provides, on test, a delay indicative of the inherent speed of the integrated circuit associated therewith.

10. A semi-conductor wafer substantially as hereinbefore described with reference to and as illustrated in Figures 3 and 4 or Figures 3 and 5 or Figures 3 and 6 of the accompanying drawings.

11. A package integrated circuit device having device pins enabling the packaged circuit to be operated characterised additionally by a test-dedicated sub-circuit on the same chip as the integrated circuit and connected to particular device pins whereby connection of those device pins to a test apparatus permits a test measurable to be determined.