WO1988002174A3 - Nonvolatile memory cell array - Google Patents

Nonvolatile memory cell array Download PDF

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Publication number
WO1988002174A3
WO1988002174A3 PCT/US1987/002230 US8702230W WO8802174A3 WO 1988002174 A3 WO1988002174 A3 WO 1988002174A3 US 8702230 W US8702230 W US 8702230W WO 8802174 A3 WO8802174 A3 WO 8802174A3
Authority
WO
WIPO (PCT)
Prior art keywords
cell
substrate regions
nonvolatile memory
column lines
ioc1
Prior art date
Application number
PCT/US1987/002230
Other languages
French (fr)
Other versions
WO1988002174A2 (en
Inventor
Alan David Poeppelman
Raymond Alexander Turi
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Priority to DE8787905900T priority Critical patent/DE3775379D1/en
Publication of WO1988002174A2 publication Critical patent/WO1988002174A2/en
Publication of WO1988002174A3 publication Critical patent/WO1988002174A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Abstract

In a matrix array of nonvolatile memory cells, each cell (36) includes a floating gate (47) coupled by large and small capacitances (46, 44) to first and second substrate regions (42, 43). The cell (36) further includes first and second select transistors (49, 51) having gate electrodes enabled by a row line and source/drain paths coupled respectively between the first and second substrate regions (42, 43), and first and second column lines (IOC1, R1). The first and second substrate regions (42, 43) communicate with corresponding second and first substrate regions of adjacent cells in the row. Programming and reading of the cell involves applying appropriate voltages to the first and second column lines (IOC1, R1) and the first column line (I1C2) of an adjacent cell. Such sharing of column lines between adjacent cells enables a high packing density to be achieved.
PCT/US1987/002230 1986-09-22 1987-09-04 Nonvolatile memory cell array WO1988002174A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE8787905900T DE3775379D1 (en) 1986-09-22 1987-09-04 NON-VOLATILE MEMORY CELL ARRANGEMENT.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/910,053 US4769788A (en) 1986-09-22 1986-09-22 Shared line direct write nonvolatile memory cell array
US910,053 1986-09-22

Publications (2)

Publication Number Publication Date
WO1988002174A2 WO1988002174A2 (en) 1988-03-24
WO1988002174A3 true WO1988002174A3 (en) 1988-07-28

Family

ID=25428241

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1987/002230 WO1988002174A2 (en) 1986-09-22 1987-09-04 Nonvolatile memory cell array

Country Status (5)

Country Link
US (1) US4769788A (en)
EP (1) EP0281597B1 (en)
JP (1) JP2585669B2 (en)
DE (1) DE3775379D1 (en)
WO (1) WO1988002174A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4870304A (en) * 1987-12-08 1989-09-26 Cypress Semiconductor Corporation Fast EPROM programmable logic array cell
DE68913190T2 (en) * 1989-03-31 1994-08-04 Philips Nv EPROM, which enables multiple use of the bit line contacts.
US5168464A (en) * 1989-11-29 1992-12-01 Ncr Corporation Nonvolatile differential memory device and method
US5313605A (en) * 1990-12-20 1994-05-17 Intel Corporation High bandwith output hierarchical memory store including a cache, fetch buffer and ROM
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0040251A1 (en) * 1979-11-12 1981-11-25 Fujitsu Limited Semiconductor memory device
DE3136517A1 (en) * 1980-09-26 1982-06-16 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa PERFORMANCE OR NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2809191C3 (en) * 1978-03-03 1981-10-08 Industrie-Werke Karlsruhe Augsburg Ag, 7500 Karlsruhe Garbage truck with a rotating drum serving as a collecting container
JPS6046554B2 (en) * 1978-12-14 1985-10-16 株式会社東芝 Semiconductor memory elements and memory circuits
US4486769A (en) * 1979-01-24 1984-12-04 Xicor, Inc. Dense nonvolatile electrically-alterable memory device with substrate coupling electrode
DE2916884C3 (en) * 1979-04-26 1981-12-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Programmable semiconductor memory cell
US4387447A (en) * 1980-02-04 1983-06-07 Texas Instruments Incorporated Column and ground select sequence in electrically programmable memory
JPS6034198B2 (en) * 1980-11-26 1985-08-07 富士通株式会社 non-volatile memory
US4628487A (en) * 1984-08-14 1986-12-09 Texas Instruments Incorporated Dual slope, feedback controlled, EEPROM programming
US4616245A (en) * 1984-10-29 1986-10-07 Ncr Corporation Direct-write silicon nitride EEPROM cell
US4683554A (en) * 1985-09-13 1987-07-28 Ncr Corporation Direct write nonvolatile memory cells
US4698900A (en) * 1986-03-27 1987-10-13 Texas Instruments Incorporated Method of making a non-volatile memory having dielectric filled trenches

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0040251A1 (en) * 1979-11-12 1981-11-25 Fujitsu Limited Semiconductor memory device
DE3136517A1 (en) * 1980-09-26 1982-06-16 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa PERFORMANCE OR NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
RCA Review, volume 45, no. 1, March 1984, (Princeton, New Jersey, US), S.T. Hsu: "A novel memory device for VLSI E2PROM" *

Also Published As

Publication number Publication date
DE3775379D1 (en) 1992-01-30
US4769788A (en) 1988-09-06
JPH01501023A (en) 1989-04-06
EP0281597A1 (en) 1988-09-14
JP2585669B2 (en) 1997-02-26
WO1988002174A2 (en) 1988-03-24
EP0281597B1 (en) 1991-12-18

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