WO1988003350A1

WO1988003350A1 - Apparatus and method for altering the ratio of information to parity in a digital communications system

Info

Publication number: WO1988003350A1
Application number: PCT/US1986/002200
Authority: WO
Inventors: Walter Lee Davis; Leonard Edward Nelson
Original assignee: Motorola, Inc.
Priority date: 1986-10-21
Filing date: 1986-10-21
Publication date: 1988-05-05
Also published as: KR880702033A; NO882686L; NO882686D0; DK211688A; DK211688D0

Abstract

A digital communications receiver is provided which is capable of receiving encoded signals transmitted over a radio link. The receiver is configurable such that it is capable of being commanded to receive signals exhibiting either a first ratio of information to parity or signals having a second ratio of information to parity. The receiver can also be commanded to receive signals having third or fourth ratios of information to parity. Thus the effective information throughput of the receiver can be increased upon command when desired.

Description

APPA ATϋS AND METHOD FOR ALTERING THE RATIO OF INFORMATION TO PARITY IN A DIGITAL COMMUNICATIONS SYSTEM

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital communications systems which transmit encoded signals over a radio link to a receiver, and more particularly to a digital coir-rαunications system in which the encoded signals include both information portions and error correcting portions.

2. Background Art

Such digital communications systems as referred to above can include selective call receivers of the type commonly utilized in radio paging systems. A selective call receiver is a receiver that responds and alerts the user to calls that are directed to it only and not generally to all calls on a frequency or channel. Conventionally, such radios recognize messages being transmitted thereto by the particular address information of the transmitted signals. Commonly used address information signals include sequential tone signals comprised of multiple tones, and digitally encoded binary frequency shift keying (FSK) signals. Digital code receivers include decoders that compare the signal patterns received from the transmitter with the signal patterns assigned to the pager.

POCSAG and GOLAY SEQUENTIAL CODE (hereinafter GSC) are the two digital signalling formats which have found widespread application in modern paging systems. A complete description of the POCSAG system is contained in the publication " Report Of The Studies Of The British. Post Office Code Standardisation Advisory Group (POCSAG) " , published by the Telecommunications Development Department of the British Post Office, the contents of which are incorporated herein by reference.

In such a POCSAG radiopaging system, a central paging terminal or transmitter transmits encoded signals to a population of N remotely located paging receivers, wherein N is the size of the pager population. Each paging receiver or pager has its own unique digital address. Thus, a particular pager from the population may be selectively signalled or addressed by the paging terminal. When a particular pager receives and recognizes its address, the pager typically actuates an alert to let the user of the pager know that he has been paged. In display pager systems, message information follows the address . information. Thus, it is seen that the POCSAG system includes both address signals and message signals. Those skilled in the art, refer to the POCSAG code as (31, 21 BCH + Parity) . This designation signifies that each codeword includes 21 information bits out of the total 32 bits which, constitute the word length (32 = 31 + 1 Parity bit) . Each, codeword includes 21 bits dedicated to information whereas the remaining 11 bits are dedicated to error correction or parity checking. In POCSAG address codewords, the information portion is dedicated to a message flag bit, the address itself and 2 function bits. In POCSAG message codewords, the information portion is dedicated to a message flag bit and the message itself. The message flag permits the paging receiver to distinguish between an address codeword and a message codeword. It is observed that in the POCSAG signalling format discussed above, a relatively large percentage of the bits of both the address codewords and the message codewords are always dedicated to error correction, as opposed to addressing or message carrying purposes.

The GSC paging signalling format also concerns a paging terminal which transmits encoded signals to a population of N remotely located paging receivers. As with the POCSAG code discussed above, each paging receiver or pager employing GSC signalling has its own unique digital address. As with the POCSAG code, the bit structure of GSC is such that a substantial percentage of each GSC word is dedicated to error correction as opposed to message information.

More specifically, in GSC the individual address signals are comprised of two (23,12) Golay code words. This means that the address words of the Golay Sequential Code each have a wordlength of 2x23=46 bits, of which 2x12=24 bits are dedicated to information. The remaining 22 bits are dedicated to error correction, that is, parity. The message or data words of GSC are transmitted in (15,7) Golay code which means that the message words have a wordlength of 15 bits, of which 7 bits are dedicated to information and the remaining 8 bits are dedicated to parity. Thus, in GSC, the ratios of information bits to parity bits for both the address signals and the message signals are relatively low and fixed.

In summary, it is appreciated that both POCSAG and GSC paging signal formats include address signals and message signals. In the POCSAG system, the ratios of information to parity in the address signals and the message signals are identical. In the GSC system, the ratios of information in the address signals and the message signals are different. In both the POCSAG and GSC systems, however, the ratios of information to parity of the address signals and the message signals (if present) are fixed. That is, the ratio of information to parity of the address signals does not vary, and the ratio of information to parity of the message signals^' does not vary.

In the POCSAG and GSC signalling formats discussed above, the number of bits dedicated to error correction relates directly to the rate of falsing experienced by radio pagers using such, formats. Those skilled in the art appreciate that the greater the number of bits per codeword dedicated to error correction, then the lower is the falsing rate of the pager population, correspondingly. However, when a high percentage of bits per codeword is dedicated to error correction, the number of falses or errors is decreased at the expense of reducing information throughput. "'The signalling formats discussed above exhibit a ratio of information bits to error correcting bits per codeword which is constant and relatively low. It is clear that a large percentage of time is spent transmitting error detecting signals instead of information. Having such a relatively high percentage of overall signalling time occupied by error detection codes limits the number of pagers that can be addressed^* and messages that can be received and processed by such pagers during a given period of time. During periods of peak loading of the paging system, the constant length of the codeword and the constant lengths of the information and error correcting portions thereof, place an absolute limit on the number of pages that can be processed by the paging system in a given period of time.

System loading over a 24 hour period of a fully loaded paging system such as may be found in major metropolitan areas is illustrated in FIG. 4. In this illustration, the system is operating at 100 per cent of full capacity during the day from 10:00 A.M. until 4:00 P.M. This means, that the transmitter is transmitting at 100 per cent of its through-put capacity during this 6 hour interval during which the channel is fully loaded. New messages placed in the system during this time interval can encounter delays of up to 15 minutes as they are queued, waiting their turn for transmission. If the effective amount of information throughput of the transmitted signals in the system could be increased during this time interval, then the message throughput during these peak times could be increased thereby reducing or eliminating such queuing delays.

BRIEF SUMMARY OF THE INVENTION

Accordingly, one object of the present invention is to provide a paging system which is capable of varying the ratio of information to parity of the codewords thereof in response to system loading or other parameter or command such that the effective information throughput of the paging system is increased when desired.

Another object of the invention is to provide a pager receiver which is capable of processing paging signals having a first ratio of information to parity and then switching to processing paging signals having a second ratio of information to parity. In accordance with one embodiment of the invention, a radio communications pager is provided which decodes error correction encoded signals over a radio link from a remote location. The receiver includes apparatus for altering the decoding parity check algorithm of the receiver to match the encoding used in transmitting from the remote locations and further includes a receiver for receiving radio signals over a radio link to produce received signals. The pager includes a decoder for decoding the received signal. Such decoder includes an error correction circuit for correcting errors in the received signal. The decoder is adapted to detect a predetermined code signal to alter the error detection decoding characteristics of the error correcting means, whereby the relative information content of the transmitted signal can be varied.

The features of the invention believed to be novel are specifically set forth in the appended claims. However, the invention itself, both as to structure and method of operation, may best be under¬ stood by reference to the following description considered together with the accompanying drawings.

Brief Description of the Drawings

FIG. 1 is a graphic representation of a radio communications system.

FIG. 2 is a graphic representation of a radio communication receiver including an apparatus for -altering the error correction decoding algorithm used in the receiver.

FIG. 3A is a functional diagram of the microcomputer utilized in the system of the invention. FIG. 3B is a functional diagram of another ROM showing major modules for use with the microcomputer of FIG. 3A.

FIG. 4 is a system loading chart for a heavily loaded paging system.

FIGS. 5A and 5B comprise a descriptive diagram for a conventional data encoding system.

FIGS. 6A, 6B and 6C comprise a descriptive diagram for a first data encoding system, for the preferred embodiments of the invention.

FIGS. 7A, 7B, 7C and 7D comprise a descriptive diagram for a second data encoding system for the preferred embodiment of the invention, of which Fig. 7B shows a word format exhibiting a first information to parity ratio and Fig. 7D shows a word format exhibiting a second information to parity ratio.

FIGS. 8A, 8B and 8C comprise a descriptive diagram for a third data encoding system for the preferred embodiment of the invention.

FIGS. 9A, 9B and 9C comprise a descriptive diagram for a fourth data encoding system for the preferred embodiment of the invention.

FIGS. 10A, 10B and IOC comprise a descriptive diagram for a fifth data encoding system for the preferred embodiments of the invention.

FIGS. 11A, 11B, 11C and 11D comprise a detailed flowchart of the implementation of the preferred embodiment of the invention utilizing the data encoding system of FIGS. 6A-6C.

FIGS. 12A, 12B and 12C comprise a detailed flowchart of the implementation of the preferred embodiment of the invention utilizing the data encoding system of FIGS. 7A-7C.

FIGS. 13A, 13B and 13C comprise a detailed flowchart of the implementation of the preferred embodiment of the invention utilizing the data encoding system of FIGS. 8A-8C.

FIGS. 14A, 14B and 14C comprise a detailed flowchart of the implementation of the preferred embodiment of the invention utilizing the data encoding system of FIGS. 9A-9C.

FIGS. 15A, 15B and 15C comprise a detailed flowchart of the implementation of the preferred embodiment of the invention utilizing the data encoding system of FIGS. 10A-10C.

Description of the Preferred Eit-bodiment

As seen in FIG. 1, a radio communication system 10 includes a transmitter 11 which, transmits signals from antenna 12 to a plurality of selective call receivers such as tone alert pagers 14 and/or display pagers 15. Other types of selective call receivers such as tone and voice pagers (not shown) may also be employed.

FIG. 2 is a graphic representation of a radio communication receiver having an apparatus for altering the ratio of information to parity (hereinafter I/P ratio) of the receiver, such as a tone alert pager 14. The transmitted radio frequency (RF) signal from transmitter 11 is picked up at antenna 20 and applied to a conventional receiver portion designated 21 where detected digital signals are passed through low pass filter 22 and then through data limiter 23 before supplying the signal to the receiver control portion 24.

The digital signals are then applied to the bit pattern detector 25 of a microcomputer 26 where they are compared with address codes that are stored in an address code memory 27. Control logic 30 interfaces with the bit pattern detector 25 and the address code memory 27 as well as an output annunciator 31 which constitutes output signalling means. In a display pager such as that indicated at 15 in FIG. 1, the output annunciator 31 would typically include an LCD for displaying numeric or alphanumeric messages.

A crystal oscillator 32, constituting a reference oscillator, supplies timing signals to both the control logic 30 and to a divider 33. In the preferred embodiment, the crystal oscillator 32, which can be of conventional design, provides an output signal on line 70 of N x 38.4 KHz, wherein N is an integer selected to provide for ease of decoding in the microcomputer. In the preferred embodiment of the invention, N = 1 for POCSAG code and N = 4 for GSC.

Divider 33 includes a prescaler 71 which divides by 16 and which has an output 72 providing an output signal at N x 2400 Hz. This signal is then applied to a divide by 4 counter 73 by coupling prescaler output 72 to the input of counter 73. An output line 74 of counter 73 provides a signal which constitutes the bit clock signal which is used to control the sampling of the input data signal. As indicated in FIGS. 2 and 3, this bit clock signal is supplied to both the bit pattern detector 25 and control logic 30 of the CPU 26.

FIG. 3A shows a functional block diagram of the microcomputer 26 which contains the firmware for implementation of the I/P ratio alteration function of the receiver. In the preferred embodiment of the invention, the microcomputer is a Motorola 146805 type. U.S. Patent 4,518,961 entitled "Universal Paging Device with Power Conservation", owned by the assignee of this invention, discloses the use of such a microcomputer. The disclosure of this patent is hereby incorporated by reference.

The bit clock signal from divider 73 is supplied to a timer control unit 80 containing a prescaler and a timer and counter. The output of crystal oscillator 32 is connected to a central processing unit (CPU) 82 which contains the central processing unit control circuit, an arithmetic logic unit designated ALU, an accumulator, index register, condition code register, stack pointer, program counter high and program counter low modules. Also connected to the central processing unit are data directional input/output (I/O) registers 84 and 86 having a plurality of input/output lines. - In particular, eight lines are shown for each of two input/output ports. An input line of register 84 is connected to receive the bit stream signal from data limiter 23. An output line of register 86 is connected^"r to output annunciator 31. Four I/O lines of register 86 are connected to address code memory 27.

Also interfacing with the central processing unit are a read-only-memory (ROM) 88 and a random access memory (RAM) 90. As is characteristic of-the Motorola 146805 family, the on-chip RAM permits the microcomputer 26 to operate without an external RAM memory. The parallel input/output capability includes programmable pins indicating whether it is to be an input or an output. The timer/counter 80 is normally an^* eight bit counter with a programmable prescaler which can be used as an event counter to generate interrupt signals at certain software- selected events or can be used for timing keeping.

FIG. 3 also shows the arrangement of major firmware modules stored in the ROM 88. The choice and arrangement of this module is a function of the specific program of the embodiments of the present invention. The use of RAM 90 is principally to contain variables accessed during the program and as a scratch-pad storage.

FIG. 3B illustrates an alternate arrangement of major firmware modules stored in a ROM 92 for other embodiments of the present invention.

The 146805 microprocessor and its associated architecture and internal instruction set have been described in detail in the following U.S. patents and applications: U.S. Ser. No. 054,093, filed July 2, 1979, entitled "Low Current Input Buffers"; U.S. Serial No. 065,292, filed Aug. 9, 1979, entitled "Method for Reducing Power Consumed by a Static Microprocessor"; U.S. Ser. No. 065,293, filed August 9, 1979, entitled "Apparatus for Reducing Power Consumed by a Static Microprocessor"; U.S. Patent No. 4,300,195, filed Aug. 9, 1979, entitled "CMOS Microprocessor Architecture"; U.S. Patent No. 4,280,190, filed Aug. 9, 1979, entitled "Incrementor/Decrementor Circuit"; and U.S. Patent No. 4,308,581, filed Sept. 28, 1979, entitled "A Single Step System for a Microcomputer", all of the above six applications being commonly assigned to the assignee of the present invention. These six designated patents and applications are hereby incorporated by reference for a more complete description of the MC146805 microcomputer.

The operation of various embodiments of the receiver will now be discussed. A conventional POCSAG coding scheme is disclosed in FIGS. 5A and 5B. Referring first to FIG. 5A, in a POCSAG code format a sync code is transmitted followed by eight groups of address codes, namely groups 0-7, each of which includes two address segments. A single address segment is illustrated in FIG. 5B and consists of a 32 bit word. This 32 bit word includes a single bit message flag followed by address bits in bit positions 2 through 19. Function bits are provided in positions 20 and 21, parity check bits in position 22-31 and an even parity bit in position 32.

Depending on the desired operation of receivers 14 or 15, several variations can be made to the POCSAG code of FIG. 5 to provide for variable I/P ratio operation. Referring first to FIGS. 6A-C, a coding scheme is illustrated in which a six-bit I/P ratio code word is transmitted immediately after the sync code. An example of how the six bit code word might be encoded to indicate which one of four I/P ratios should be used, is illustrated in FIG.6C.

.The I/P ratio binary code 000000 indicates that a (31,21) BCH code is the encoding base for (31+1,21) codeword transmission, wiiile the binary code 010101 corresponds to a (41,21) BCH code as the encoding base for (41+1,21) codeword transmission. The binary code 101010 corresponds to a (45,21) BCH code which is the encoding base for (45+1,21) codeword transmission. An I/P ratio code of 111111 corresponds to a (55,21) BCH code which is the encoding base for (55+1,21) codeword transmission. In each of these four cases, the transmitted codewords are formed from the base BCH code by adding one bit to provide for even parity.

The decoding via computer of such BCH codes as above is described in "Error-Correcting Codes", Second Edition, by W. Wesley Peterson and E.J. Weldon, Jr. , published by the MIT Press, Cambridge, MA, a standard text which is incorporated herein by reference. It is noted that the BCH code distances, d, of the above BCH codes, namely, (31,21), (41,21), (45,21) and (55,21) are 5, 6, 7 and 8, respectively. The relative information content of the words decreases and the percentage of the words dedicated to error correction increases as the code distance, d, proceeds from smaller to larger numbers. It is also noted that the code derived from the base (31,21) BCH by adding a parity check bit is sometimes referred to as a (31+1,21) code, and the other derived codes referenced above are sometimes referred to as (41+1,21), (45+1,21) and (55+1,21) codes, respectively.

(For convenience, the I/P ratios above and elsewhere in this document are expressed in terms of a pair of numbers, the first number of which indicates the words length in bits, the second number of which indicates the number of bits per word dedicated to information. Any remaining bits are parity bits. Although, strictly speaking, these number pairs are not I/P "ratios", they give sufficient information for the actual I/P ratio to be readily derived. For example, the (31+1,21) code will be referenced here as the (32,21) code, and 21 of the 32 bits in each word thereof are dedicated to information. The remaining 11 bits are parity bits. Thus, the actual I/P ratio is 21/11.) Similarly, the (41+1,21) code will be referenced as (42,21). The (45+1, 21) code will be referenced as (46,21) and the (55+1,21) will be referenced as (56,21).)

In a system utilizing the code illustrated in FIGS. 6A-C, receiver 14 or 15 would detect a sync code at a predetermined I/P ratio. It would then detect the I/P ratio code. Based upon which of the I/P ratio codes is detected, it would change its I/P ratio to correspond to the transmitted I/P ratio code and then look for its address during its appropriate group window. The control logic for operation of the receiver under this system is illustrated in the flow chart 300 of FIGS. llA-C.

It is to be understood that an address codeword corresponds to a unique sequence of information bits. That is, a set of information, bits uniquely defines a codeword in each of the four possible code sets. Thus, the address information can be stored in the code plug (address code memory) in several forms. First, the complete codeword sequence for all the encoding formats can be stored in the code memory, or the codeword sequences can all be derived from the information bit pattern, and only the information bits need be stored in the code memory. This latter approach his the benefits of requiring less memory space, and it permits address codewords to be constructed from transmitted information about the encoding format.

It is also to be understood that the timing of the address words and sync words in the system shown in FIGS. 6A-C is a fixed function of the I/P ratio and that the timing used in decoding these signals can be directly derived from the I/P ratio.

As illustrated in flow chart 300 of FIGS. 11A-D, the system is first initialized at block 302. Next, the code plug memory is read at block 304, the result of which is utilized to initialize the timer, as shown at block 306. A search for bit sync then commences as shown at block 308. If bit sync is not found, the search for bit sync is continued. If bit sync is found, then bit timing is established as per block 310, after which the time-out timer is started to establish a time period during which the sync word is to be searched for and detected, as per block 312. During this time period, the system searches for the sync word, block 314. If the time period for locating the sync word expires without the sync word being found, block 316, then the search for bit sync is begun, again. However, if the sync word is detected, then the system proceeds to decode the I/P ratio code word which follows the sync code, block 320.

Depending on which one of four I/P ratio code words is detected in decision blocks 322, 326, 330 and 334, the I/P ratio is set to a corresponding one of four I/P ratios, as per blocks 324, 328, 332, and 336. More specifically, if the I/P ratio code word is detected to be 000000, 010101, 101010 or 111111, then the I/P ratio is set to (32,21), (42,21), (46,21) or (56,21), respectively.

Then, the timer is set up for address decoding at block 338. A wait is made for time-out, block 340, after which a search is made for the address at block 342. If an address is detected, then function bits are decoded as per block 344. The function bits are examined to determine if a message was received as shown at block 346. If no message function is present, then an alert signal is generated at block 348. However, if a message function is present, then the message is stored at block 350, after which an alert signal is generated at block 352.

After generation of an alert signal at 348 or 352, or if an address is not detected at 342, a timer is set up for the next sync word as per block 354. Then the I/P ratio is set to the I/P ratio of the sync code at block 356. The system waits for a timer time-out at block 358, and a new search for a sync word is initiated at block 360. If the sync word is not detected, a sync word detect flag is read at block 362 to enable a determination to be made whether or not the sync word detect flag is set as per decision block 364. If the sync word detect flag is not set, then the flag is set at block 366. Then the system sets the I/P ratio to^" the last decoded I/P ratio at block 368 and returns to set up the timer for address decoding, block 338. If the sync word detect flag was already set, the routine branches to second miss of sync word detection block 370, and returns to search for bit sync at block 308.

Recapping briefly, in the system illustrated by flow chart 300 a sync code is always transmitted at a predetermined I/P ratio, such as (32,21). Once bit sync has been established at block 308 the sync word must be detected at block 314. The I/P ratio code is decoded and the system is set in blocks 324, 328, 332., and 336 for the appropriate I/P ratio. At block 338, the timer is set for address decoding, the timer setting depends both upon the group to which the radio is assigned as well as, the I/P ratio at which, addresses and data are being transmitted. A receiver searches for its address at block 342 and takes appropriate action if its address is detected. The receiver I/P ratio is reset at block 356 to the sync code I/P ratio to look for the next sync code. If the next sync code is detected, the I/P ratio code word is decoded in the usual manner at block 320. However, in the event that the sync word is not detected, the receiver will search for its address at the appropriate group. Since the current I/P ratio code has not been decoded, the system will utilize the last decoded I/P ratio at block 368 when searching for its address. In the event that a sync code is not detected for a second consecutive time at block 370, the system returns to the search for bit sync block 308. This system is particularly suited for increasing system throughput during peak system loading.

A different I/P ratio control signalling scheme is illustrated in FIGS. 7A-D which has some similarity to the signalling scheme of FIGS. 8A-C. Both of these are similar to the POCSAG system of FIG. 5A-C, in that a sync code is followed by eight windows or pairs of address codes. In FIG. 7B, a particular address command is illustrated that includes a message flag bit, a change I/P ratio command signal in bit positions 2-19, I/P ratio control bits in bit positions 20-21, parity check bits in bit positions 22 and 31 and an even parity bit in position 32. The particular address command shown in Fig. 7B exhibits an I/P ratio of (32,21) by way of example which is one of the four I/P ratios the system can be commanded to employ. As illustrated in FIG. 7C, control bits 20-21 could be coded for instance with a 00 to indicate (32,21) code, 01 for (42,21) code, 10 for (46,21) code, and 11 for (56,21) code.

In the code corresponding to the new I/P ratio, that is the I/P ratio to which the system is to now switch, there will still be a message flag bit in position 1, information bits in position 2-19, and I/P ratio control bits in positions 20-21, with the difference in code structure being the number of parity check bits. Thus, the same general control word structure shown in Fig. 7B can be employed in the new code with the exception being the number of parity bits in the selected code.

In the system of FIG. 7, the change I/P ratio command signals will be transmitted to each of the eight groups of pagers, thereby causing the pagers to be set to the new I/P ratio in FIG. 7C. After transmitting the change I/P ratio command in each paging window the system then returns to sending pages in a normal manner but at the new indicated I/P ratio.

FIGS. 7B and 7D illustrate two examples of code words with different I/P ratios which can be supplied in the system of the invention. That is, FIG. 7B shows a (32,21) code word having a relatively high I/P ratio, which when selected provides the maximum data throughput of the four codes selectable in the embodiment of FIG. 7C. FIG. 7D shows a (56,21) code word having a relatively low I/P ratio, which provides the maximum error correction of the four codes selectable in the embodiment of FIG. 7C, although reduced data throughput correspondingly results.

As illustrated in flow chart 400 of FIG. 12A-C the system is first initialized at block 402. Next, the code plug memory is read at block 404, the result of which is utilized to initialize the timer, as shown at block 406. A search for bit sync then commences as shown at block 408. If bit sync is not found, the search for bit sync is continued. If bit sync is found, then bit timing is established as per block 410, after which the time-out timer is started to establish a time period during which the sync word is to be searched for and detected, as per block 412. During this time period, the system searches for the sync word, block 414. If the time period for locating the sync word expires without the sync word being found, block 416, then the search for bit sync is begun again. However, if the sync word is detected, then the system proceeds to set up a timer for address decoding, as per block 420. The system then waits for such timer to time-out at block 422, after which a search is conducted for address at block 424.

If the address is detected, then function bits are decoded at block 426. The function bits are examined to determine whether or not a message function was received, as per decision block 428. If a message function was not received, then an alert signal is generated at block 430. However, if a message function was received, the message is stored as per block 432 and then an alert is generated as per block 434.

If while searching for an address as block 424 the system detects a change I/P ratio command, the system takes action to change the I/P ratio accordingly. The I/P ratio control bits of the I/P ratio control command are examined to which one of the four variations possible in this example are present. That is, depending on which one of four I/P ratio control commands is detected in decision blocks 436, 440, 444 and 448, the I/P ratio is set to a corresponding one of four I/P ratios, as per blocks 438, 442, 446 and 450, respectively. More specifically, if the I/P ratio control command is detected to be 00, 01, 10 or 11, then the I/P ratio is set to (32,21), (42,21), (46,21) or (56,21), respectively.

After generation of alert signals at 430 or 434, or setting the I/P ratio at blocks 438, 442, 446 or 450, or if an address or a change I/P ratio control command is not detected at block 424, the timer is set up for the next sync word as per block 452. The system then waits for timer time-out at block 454, and a new search for sync is initiated at decision block 456.

If the sync word is not detected, a sync word detect flag is read at block 458. A determination is then made whether or not the sync detect flag is set at decision block 460. If the sync detect flag is not already set, the sync detect flag is then set, as seen at block 462. After setting the sync detect flag or if the sync word is not detected at block 456, the routine returns to again set up the timer for address decoding at block 420. However, if the sync flag was already set, the routine branches to a second miss of sync word detection block 464 and returns to search for bit sync at block 408.

To cover the situation in which paging receivers may be turned on after a system change command (I/P ratio change command) has been transmitted, the system transmitter or paging terminal can periodically retransmit the I/P ratio change command. This would act to keep all pagers in the system decoding at the proper I/P ratio.

To recap briefly, the routine shown in the flow chart 400 of FIGS. 12A-12C, like that of flow chart 300 of FIGS. 11A-11D, decodes the sync code at a predetermined I/P ratio, such as (32,21). However, unlike flow chart 300, in this system the addresses are also transmitted and decoded at the predetermined I/P ratio. In addition to a normal receiver address which can be detected at block 422, a change I/P ratio command can also be detected. The change I/P ratio command can be recognized by one or preferably all of the receivers in each group. If the change I/P ratio command is detected, the following two bits are examined at blocks 436, 440, 444 and 448 to determine the new system I/P ratio. This new system I/P ratio then becomes the predetermined I/P ratio for the receiver. Further decoding of sync codes and addresses is done at the new I/P ratio. This new I/P ratio is retained until such time as another change I/P ratio command is detected to provide for selection of a new system I/P ratio. The system I/P ratio is effected by transmitting the change I/P ratio command signals to each group of pagers so that all the pagers in the system will operate at the new I/P ratio. This system can provide for ever greater throughput than the system of flow chart 300, since even the sync words are transmitted at the new I/P ratio. That is, at times of peak system loading, the I/P ratio can be selected such that the number of information bits per codeword is increased and the number of parity or error correction bits is reduced to increase the overall system information throughput.

In the system .of FIG. 8, the control bit patterns are transmitted with each page address to indicate the I/P ratio of data following the address signal. After the data message is decoded, the pager reverts to the sync code I/P ratio. Thus, this system provides the ability to adjust the I/P ratio of individual message transmissions.

As illustrated in flow chart 500 of FIG. 13A-C the system is first initialized at block 502. Next, the code plug memory is read at block 504, the result of which is utilized to initialize the timer, as shown at block 506. A search for bit sync then commences as shown at block 508. If bit sync is not found, the search for bit sync is continued. If bit sync is found, then bit timing is established as per block 510, after which the time-out timer is started to establish a time period during which the sync word is to be searched for and detected, as per block 512. During this time period, the system searches for the sync word, block 514. If the time period for locating the sync word expires without the sync word being found, block 516, then the search for bit sync is begun again.

However, if the sync word is detected, then the system proceeds to set up a timer for address decoding, as per block 520. The system then waits for the timer to time-out at block 522, after which a search is conducted for address at block 524. If the pager's address is detected, then the two I/P ratio control bits following the address are examined to determine which I/P ratio should be used to receive a particular message. That is, depending on which one of four I/P ratio control bit sequences is detected in decision blocks 526, 530, 534 and 538, the I/P ratio of the receiver is set to a corresponding one of four I/P ratios, as per blocks 538, 542, 546 and 550, respectively. More specifically, if the I/P' ratio control bit sequence is detected to be 00, 01, 10 or 11, then the I/P ratio is set to (32,21), (42,21), (46,21) or (56,21), respectively for the subsequent message. The message is then received at the indicated I/P ratio as per block 542, after which an alert is generated at 544. The I/P ratio is then reset to the I/P ratio of the sync code as per block 546.

After the I/P ratio is reset in block 546 or when an address is not detected in block 524, the timer is set up for the next sync word as per block 550. The system then waits for timer time-out at block 552, and a new search for sync is initiated at decision block 554.

If the sync word is not detected, a sync word detect flag is read at block 556. A determination is then made whether or not the sync detect flag is set at decision block 558. If the sync detect flag is not already set, the sync detect flag is then set, as seen at block 560. After setting the sync detect flag or if the sync word is not detected at block 554, the routine returns to again set up the timer for address decoding at block 520. However, if the sync flag was already set, the routine branches to a second miss of sync word detection block 562 and returns to search for bit sync at block 508.

It is to be understood that in the system shown in FIG. 8, the sync word is always transmitted at a fixed interval.

Recapping briefly, the routine of flow chart 500 of FIGS. 13A-13C defines a system in which the sync code and the address are transmitted to the pagers at a predetermined I/P ratio. If the message is not a simple tone only page, but rather includes a numeric or alphanumeric message, this data message is transmitted with an I/P ratio indicated by the I/P control bits which follow the address of the pager. The I/P ratio control bits are decoded at the predetermined I/P ratio by the pager. However, the data message is decoded at the I/P ratio designated by the I/P control bits.

The I/P ratio of the pager receiver is then reset to the predetermined I/P ratio to decode the next sync word. This system can be used when an increase in system throughput is needed, as for example when long data messages are being transmitted. Since only data messages are transmitted at the new I/P ratio (which can be selected to exhibit a higher I/P ratio than the predetermined I/P ratio) , any errors resulting from the increase of information bits and decrease of error correcting bits will only affect the data messages received by the pagers and will not tend to increase the rate of false address detection by pagers. This result is due to the fact that the pagers' addresses are still transmitted at the predetermined I/P ratio.

Referring now to FIGS. 9A-C, a coding scheme is illustrated that is similar to the GOLAY sequential code (GSC) or the so called Echo code. As illustrated in FIG. 9A, an address signal is followed by I/P ratio information and then data. The address signal format is illustrated in FIG. 9B and includes two words, a first word 1 and a second word 2. The I/P ratio of each of the words shown in the particular example of Fig. 9B is (23,12), such that 12 bits of information are followed by 11 parity bits with a half bit space separating the two words. This is an example of one of the four I/P ratios whicli are selectable in this embodiment of the invention. That is, in this embodiment, the I/P ratio code encodes four I/P ratios with the six bit repetition code previously discussed. Thus, 000000 corresponds to a (21,12) I/P ratio, 010101 corresponds to a (23,12) I/P ratio, 101010 corresponds to a (33,12) I/P ratio, and 111111 corresponds to a (39,12) I/P ratio.

It is noted that the code distances, d, of the above BCH codes, namely, codes (21,12), (23,12), (33,12) and (39,12) are 5, 7, 10 and 12. The relative information content decreases and the percentage of the words dedicated to error correction increases as the code distance, d, proceeds from smaller to larger numbers.

While data is indicated as following the I/P ratio code in FIG. 9A, it will be understood that data need not be included, particularly where the default I/P ratio of the receiver used for decoding the address signal is being changed. As illustrated in FIGS. 14A-C, the paging receiver can respond to two distinct address signals. With the first of the address signals, the I/P ratio designated by the I/P ratio code is used for decoding the data message and the receiver reverts to the system I/P ratio to again look for its address. When the second pager address signal is transmitted, the I/P ratio code is retained as the new system address signal I/P ratio.

The control logic for operation of the receiver under this system is illustrated in FIGS. 14A-C. As illustrated in the flow chart of FIGS 14A-C, the system is first initialized at 602. Next the code plug memory is read at block 604. After the code plug is read, the .timer is set up at block 606, after which the system waits for a time-out at block 608. After waiting for such time-out, the timer is restarted in block 610 and ttfie address flag is^' set to address number 1 at block 612. Then, word 1 of the current address is loaded as seen at block 614.

After loading word 1 of the current address, the pager searches for word 1 in the received signal at decision block 616. If word 1 is not detected, then a decision is made whether or not this word is address 2 at block 636. If the subject word is not found to be address 2, then the address flag for address number 2 is set at block 638 and flow continues back to block 614 at which word 1 of the current address is loaded and so forth as seen in the flowchart of Fig. 14A. However, if the subject word is found to be address 2, then flow continues back to block 608 at which the system again waits for a time out, then the timer is restarted in block 610 and flow continues forward in the manner already discussed above and as seen in Figs 14A-C.

If word 1 is detected at block 616, then flow continues to decision block 618 where a determination is made whether word 1 or its inverse is detected. If word 1 is detected, then a detect flag is set for word 1 for the current address. If instead the inverse of word 1 was detected, then a detect flag is set for inverse word 1 for the current address. In either case, word 2 of current address is then loaded at block 626 after which a determination is made word 2 has been detected in block 628. If word 2 is not detected, then flow continues to decision block 636 at which a determination of whether this word is address 2 or not is made. This determination and subsequent flow has already been discussed in detail above and is not repeated here. However, if word 2 is detected at block 628, then a determination is made at decision block 630 whether word 2 or its inverse was detected. If word 2 was detected, then a detect flag for word 2 for current address is set at block 632. If the inverse of word 2 is detected, then a detect flag for inverse word 2 for current address is set at block 634.

In either case, the I/P ratio code word- is then decoded at block 640. As seen in Fig. 14C, tests are made at decision block 642, 646 _r 650 and 65.4 to determine whether the I/P ratio code equals 000000, 010101, 101010 or 111111, respectively. If the I/P ratio code word is found to be 000000, then the I/P ratio is set to be (21,12) at block 644. If the I/P ratio code word is found to be 010101, then the I/P ratio is set to be (23,12) at block 648. If the I/P ratio code word is found to be 101010, then the I/P ratio is set to be (33,12) at block 652. If the I/P ratio code word is found to be 111111, then the I/P ratio is set to be (39,12) at block 656.

Subsequent to setting the I/P ratio as described above, a determination is made at block 658 whether address 2 is present. If address 2 is present, then the new address signal I/P ratio is stored at block 660. Then, the detect flags are cleared at block 662, after which flow continues once again to block 608 at which the system waits for a time out and the above described process begins over again as indicated in Fig. 14A-14C. If the determination is made at block 658 that address 2 is not present, then the data message is decoded at block 664, after which the detect flags are cleared at block 666. Then, the system returns to operating at the I/P ratio for the address signals in block 668. Flow then continues to block 608 at which the system waits for a time out and the above described process begins over again is set forth in Figs. 14A-14C.

Referring now to FIGS. 10A-C, a coding scheme is illustrated that is similar to a GOLAY sequential code (GSC) or echo code. As illustrated in FIG. 10A, an address signal is followed by a data message. The address signal format is illustrated in FIG. 10B and includes two words, a first word 1 and a second word 2. The I/P ratio of each of the words shown in the particular example of Fig. 10B is (23,12), such that 12 bits of information are followed by 11 parity bits with a half bit space separating the two words.

In this embodiment, the I/P ratio of data that follows is indicated by the function code of the address signal. The function code is determined by whether word 1 and word 2 are sent or if their binary inverses are sent. As illustrated in FIG. IOC, function 1, indicated by sending word 1 and word 2, corresponds to a I/P ratio of (21,12). Function 2, indicated by sending word 1 and the binary inverse of word 2, corresponds to (23,12) code. Function 3, indicated by sending the inverse of word 1 and word 2, corresponds to (33,12) I/P ratio. While function 4, indicated by sending the inverse of word 1 and the inverse of word 2, corresponds to (39,12) I/P ratio.

While data is indicated as following the bit address signal in FIG. 10A, it will be understood that data need not be included, particularly where the default I/P ratio of the receiver used for decoding the address signal is being changed. As is illustrated in FIGS. 15A-C, the paging receiver can respond to two distinct address signals. With the first of the address signals, the function code is used for setting the I/P ratio for decoding the data message and the receiver then reverts to the default I/P ratio for the next address. When the second pager address signal is transmitted, the I/P ratio designated by the transmitted function is retained as the new default address signal I/P ratio.

The control logic for operation of the receiver under this system is illustrated in FIGS. 15A-C. As illustrated in the flow chart of FIGS 15A-C, the system is first initialized at 702. Next the code plug memory is read at block 704. After the code plug is read, the timer is set up at block 706, after which the system waits for a time-out at block 708. After waiting for such time-out, the timer is restarted in block 710 and the address flag is set to address number 1 at block 712. Then, word 1 of the current address is loaded as seen at block 714.

After loading word 1 of the current address, the pager searches for word 1 in the received signal at decision block 716. If word 1 is not detected, then a decision is made whether or not this word is address 2 at block 736. If the subject word is found to be address 2, then the address flag for address number 2 is set at block 738 and flow continues back to block 714 at which word 1 of the current address is loaded and so forth as seen in the flowchart of Fig. 15A. However, if the subject word is not found to be address 2, then flow continues back to block 708 at which the system again waits for a time out, then the timer is restarted in block 710 and flow continues forward in the manner already discussed above and as seen in Figs 15A-C.

If word 1 is detected at block 716, then flow continues to decision block 718 -where a determination is made whether word 1 or its inverse is detected. If word 1 is detected, then a detect flag is set for word 1 for the current address. If instead the inverse of word 1 was detected, then a detect flag is set for inverse word 1 for the current address. In either case, word 2 of current address is then loaded at block 726 after which a determination is made word 2 has been detected in block 728. If word 2 is not detected, then flow continues to decision block 736 at which a determination of whether this word is address 2 or not is made. This determination and subsequent flow has already been discussed in detail above and is not repeated here. However, if word 2 is detected at block 728, then a determination is made at decision block 730 whether word 2 or its inverse was detected. If word 2 was detected, then a detect flag for word 2 for current address is set at block 732. If the inverse of word 2 is detected, then a detect flag for inverse word 2 for current address is set at block 734.

In either case, tests are made at decision blocks 742, 746, 750 and 756 to determine whether the sequence received is sequence 12, 1 2BAR, 1BAR 2, or 1BAR 2BAR, respectively. If the received sequence is sequence 12, then the I/P ratio is set to (21,12) at block 744. If the received sequence is sequence 1 2BAR, then the I/P ratio is set to (23,12) at block 748. If the received sequence is sequence 1BAR 2, then the I/P ratio is set to (33,12) at block 752. If the received sequence is sequence 1BAR 2BAR, then the I/P ratio is set to (39,12) at block 756.

Subsequent to the setting of the I/P ratio as described. above, a determination is made whether address 2 is present at decision block 758. If address 2 is determined to be present, then the new address signal I/P ratio is stored at block 760, after which the detect flags are cleared at block 762. Flow then continues to the wait for time out block 708 and processing continues as per the flowchart of Figs. 15A-15C. If address 2 is not found to be present at block 758, then the data message is decoded at block 764 after which the detect flags are cleared at block 766. Then the system returns to the I/P ratio of for address signals in block 768, after which the system again waits for a time-out as per block 708. The system then continues operation as per the flowchart of Fig. 15A-15C. The various disclosed embodiments have been illustrated utilizing four I/P ratios, it would be understood that any desired I/P ratio can be utilized in the system. The system can be provided with a single alternate I/P ratio and any desired number of I/P ratios that can be selected by the necessary I/P ratio code word, function bits or other designation.

Again, to cover the situation in which paging receivers may be turned on after a system change command (I/P ratio change command) has been transmitted, the system transmitter or paging terminal can periodically retransmit the I/P ratio change command. This would act to keep all pagers in the system decoding at the proper I/P ratio.

From the above discussion of receiver apparatus for altering the ratio of information to parity upon command from the paging terminal, it is clear that a method is also disclosed for altering the ratio of information to parity in a digital paging receiver. In summary, this method includes the steps of receiving paging signals having a first ratio of information to parity and then decoding such paging signals having the first ratio of information to parity. The paging receiver then detects a command for altering the decoding characteristics of the receiver to decode paging signals having a second ratio of information to parity. When such command is detected, the decoding characteristics of the receiver are altered in response to such command to permit decoding of paging signals having the second ratio of information to parity. Paging signals exhibiting the second ratio of information to parity are then decoded.

While only certain preferred features of the invention have been shown by way of illustration. many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the present claims are intended to cover all such modifications and changes which fall within the true spirit of the invention.

Claims

CLAIMS We claim:

1. In a radio communications receiver that decodes error correction encoded signals transmitted over a radio link from a remote location, apparatus for altering the decoding parity check algorithm of the receiver to match the encoding used in transmitting from the remote locations, comprising:

(a) means for receiving radio signals over a radio link to produce received signals;

(b) means for decoding the received signal including:

(1) error correction means for correcting errors in the received signal,

(2) said decoding means adapted to detect a predetermined code signal to alter the error detection decoding characteristics of the error correcting means, whereby the relative information content of the transmitted signal can be varied.

2. In a paging receiver, a method for receiving paging signals transmitted from a paging terminal: receiving paging signals having a first ratio of information to parity; decoding said paging signals having a first ratio of information to parity; detecting a command to alter the decoding characteristics of said receiver to decode paging signals having a second ratio of information to parity; altering the decoding characteristics of said receiver in response to said command to permit decoding of said paging signals having a second ratio of information to parity, and decoding said paging signals having a second ratio of information to parity.