WO1988006348A1 - Integrated circuit package assembly - Google Patents

Integrated circuit package assembly Download PDF

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Publication number
WO1988006348A1
WO1988006348A1 PCT/US1987/002363 US8702363W WO8806348A1 WO 1988006348 A1 WO1988006348 A1 WO 1988006348A1 US 8702363 W US8702363 W US 8702363W WO 8806348 A1 WO8806348 A1 WO 8806348A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
chip
circuit package
package assembly
lead fingers
Prior art date
Application number
PCT/US1987/002363
Other languages
French (fr)
Inventor
Gerald K. Fehr
Abu Eghan
Original Assignee
Lsi Logic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corporation filed Critical Lsi Logic Corporation
Publication of WO1988006348A1 publication Critical patent/WO1988006348A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Definitions

  • This invention relates to an integrated circuit (IC) package assembly and in particular to a means for minimizing cracks that may form in the IC package during subsequent vapor phase reflow of the package to a system board.
  • IC integrated circuit
  • the IC chips are mounted on rigid lead frames. After this "die-attach" process, the chip is bonded using gold wires. The wires connect from the bond pads on the IC chip to leads or bond fingers which are part of the lead frame.
  • the whole die-attached and wire bonded chip configuration is encapsulated in thermoset epoxy plastic. After the encapsulation process the external leads are trimmed, formed and finished.
  • the packages are positioned on a printed circuit (PC) board which has solder paste spread on the active areas to enable the connection of the external formed leads to the printed circuit solder pads by solder reflow techniques.
  • PC printed circuit
  • vapor phase soldering using apparatus of the type shown schematically in FIG. 1 is preferably employed. With this process the PC board with the distributed solder paste and the IC packaged devices are lowered through a blanket vapor formed by condensing coils 1 into a vapor phase region 2, wherein the assembly 3 heats up to the vapor temperature. Dipping rack 4 and assembly 3 may be in region 2 for about 15 minutes. Vapor phase soldering is achieved by use of electrical immersion heaters 5 which boils fluorinated fluid 6 to its boiling temperature of about 220°C - 225°C, whereby the solder paste reflows and makes the desired connections between the leads of the IC package and the circuit connections of the printed circuit board.
  • the entrapped moisture within the package is heated and vaporizes.
  • the resulting water vapor is superheated, and provided enough moisture is present, the vapor attains the equilibrium vapor presence of steam at the soldering temperature.
  • the pressure of dry saturated steam would be about 25 bar absolute pressure or 367 pounds per square inch absolute. This level of pressure combined with regular thermomechani- cal stresses arising from the differences in expansion coefficient of the plastic chip and lead frame may give rise to cracking in the plastic material.
  • cracks tend to form from the corners or edges of the supporting pad or IC die. If the cracks are thin and small, they are difficult to find.
  • the cracks would allow moisture to enter the package to the detriment of the integrated circuit. Furthermore the cracks can cause mechanical or physical damage so that the IC package becomes inoperable at the onset. As a result, the IC assembly production yield is decreased and field operation of assembled units with undetected cracks would be unreliable.
  • One solution is to bake the IC packages slowly at abou 150°C for at least 16 hours to rid the package of moisture, for example. But the slow bake process does introduce a 16 hours long additional step to the board manufacture and is not economically feasible.
  • An object of this invention is to provide an improved IC assembly with minimal cracked IC packages after vapor phase reflow.
  • a plastic package housing an IC assembly comprises an IC die having an integrated circuit chip mounted on a rigid frame.
  • a flexible and compressible continuous tape is joined to the bottom surface of the lead frame that supports the IC die and to the leads or bond fingers extending from the IC die.
  • the thin tape is preferably made of Kapton (trademark of DuPont) and has an adhesive backing for facile attachment to the IC die pad and the bond fingers.
  • a silicon gel is applied in addition as a coating over the wires, lead fingers and the IC die to absorb stress that may be applied to the IC package elements.
  • FIGURE 1 is a representation of a vapor phase soldering apparatus y
  • FIGURE 2 is a cut-away top view of an integrated circuit package assembly, incorporating the invention
  • FIGURE 3 is side view of the integrated circuit package assembly illustrated in FIGURE 2; and FIGURES 4A and 4B are sectional views of alternative embodiments of the integrated circuit package assembly illustrated in FIGURE 1.
  • an integrated circuit chip 10 is mounted on a die pad 12 that is an integral part of a lead frame, as is known in the prior art.
  • Lead fingers 16 are joined to one end of wires 18, and the other ends of the wires are connected to bond pads 20 on the IC chip.
  • the assembly of the bonded IC chip on the die pad is encapsu ⁇ lated in a plastic epoxy package 22.
  • the outer portions of the leads 16B are trimmed and formed to shape for external connection to circuit traces on a board.
  • a thin tape or film 24 is attached to the bottom portions 16A of the lead fingers and to the bottom surface of the die pad.
  • the tape is made as a continuous flexible piece that is compressible and has a thickness in the range of about .002-.005 inch, by way of example.
  • the tape may be made of any material that can withstand the high temperatures associated with the processing of the integrated circuit package assembly and the epoxy encapsulation process, provided that the tape has the characteristics of flexibility and compressibility.
  • a protective coating 28 such as a soft gel, is placed over the bond wires and chip 10 prior to encapsulation, as shown in FIGS. 4A and 4B.
  • the gel is supported by the continuous tape backing.
  • a full gel overcoat 30 is applie to encompass the wires 18 and the chip 10.
  • a partial gel overcoat 32 is applied over the surface of the chip and covers the bonds on the chip.
  • the gel overcoat in each implementation is intended to absorb stresses that may appear as a consequence of the thermomechanical action of assembling the integrated circuit device with materials with different thermal properties.
  • the flexible and compressible tape that is provided at the bottom of the die attach pad and which extends to the lead fingers, crack initiation and propa- gation are impeded, stresses and the transmission of forces arising from stresses in the IC package are significantly reduced.
  • the flexible and compressible tape which is located to extend between the die attach pad and the lead fingers reduces the effect of stress concentration at "weak" points in the package assembly by blunting sharp radii, such as nicks and burrs.
  • the disclosed arrangement allows the application of full coverage of soft gel to the IC chip surface and wires without gel overflow to the backside during gel application. The application of soft gel further reduces stress at critical points in the package assembly, especially in packages incorporating relatively large dies.

Abstract

An integrated circuit package assembly (22) includes a semiconductor chip (10) mounted on a die pad (12), having wire leads (18) attached to bond pads (20) on the chip and lead fingers (16) connected to the wire leads and external connections. A flexible and compressible tape (24) is attached to the bottom of the die pad and extends to the lead fingers to reduce stress and to minimize cracking of the package material that encloses the chip and the wire leads during vapor phase. An optional soft gel (28) is added to coat the chip surface including the bonds to further reduce chip surface stress.

Description

INTEGRATED CIRCUIT PACKAGE ASSEMBLY
BACKGROUND OF THE INVENTION Field of the Invention
This invention relates to an integrated circuit (IC) package assembly and in particular to a means for minimizing cracks that may form in the IC package during subsequent vapor phase reflow of the package to a system board.
Description of the Prior Art
During the assembly of semiconductor devices in plastic packages, the IC chips are mounted on rigid lead frames. After this "die-attach" process, the chip is bonded using gold wires. The wires connect from the bond pads on the IC chip to leads or bond fingers which are part of the lead frame. The whole die-attached and wire bonded chip configuration is encapsulated in thermoset epoxy plastic. After the encapsulation process the external leads are trimmed, formed and finished. During the manufacture of system subassemblies involving these surface mountable plastic IC packages, the packages are positioned on a printed circuit (PC) board which has solder paste spread on the active areas to enable the connection of the external formed leads to the printed circuit solder pads by solder reflow techniques.
For mass production of system subassemblies where rapid processing is desirable, vapor phase soldering using apparatus of the type shown schematically in FIG. 1 is preferably employed. With this process the PC board with the distributed solder paste and the IC packaged devices are lowered through a blanket vapor formed by condensing coils 1 into a vapor phase region 2, wherein the assembly 3 heats up to the vapor temperature. Dipping rack 4 and assembly 3 may be in region 2 for about 15 minutes. Vapor phase soldering is achieved by use of electrical immersion heaters 5 which boils fluorinated fluid 6 to its boiling temperature of about 220°C - 225°C, whereby the solder paste reflows and makes the desired connections between the leads of the IC package and the circuit connections of the printed circuit board.
One major problem that is encountered as a result of moving the IC package assembly from an ambient environment to the vapor phase soldering environment which is at a relatively very high temperature is the formation of cracks in the epoxy plastic that encloses the IC device. These cracks may be either external or internal. The epoxy plastic is subject to the absorption of moisture through the bulk by diffusion process and along the leads or through cracks. The moisture may reside generally throughout the plastic body and in higher concentrations at surfaces with high surface energy such as at the chip and plastic interface. The equilibrium moisture level in the package is dependent on duration of storage of the package assemblies and the conditions under which storage occurs, and particularly on humidity level of the ambient.
During the vapor phase reflow soldering process, the entrapped moisture within the package is heated and vaporizes. The resulting water vapor is superheated, and provided enough moisture is present, the vapor attains the equilibrium vapor presence of steam at the soldering temperature. For example, at a temperature of about 224°C, the pressure of dry saturated steam would be about 25 bar absolute pressure or 367 pounds per square inch absolute. This level of pressure combined with regular thermomechani- cal stresses arising from the differences in expansion coefficient of the plastic chip and lead frame may give rise to cracking in the plastic material. When using the vapor phase technique for soldering IC package leads to the printed circuit, cracks tend to form from the corners or edges of the supporting pad or IC die. If the cracks are thin and small, they are difficult to find.
During operation of a system incorporating a cracked component, the cracks would allow moisture to enter the package to the detriment of the integrated circuit. Furthermore the cracks can cause mechanical or physical damage so that the IC package becomes inoperable at the onset. As a result, the IC assembly production yield is decreased and field operation of assembled units with undetected cracks would be unreliable.
One solution is to bake the IC packages slowly at abou 150°C for at least 16 hours to rid the package of moisture, for example. But the slow bake process does introduce a 16 hours long additional step to the board manufacture and is not economically feasible.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved IC assembly with minimal cracked IC packages after vapor phase reflow.
In accordance with this invention, a plastic package housing an IC assembly comprises an IC die having an integrated circuit chip mounted on a rigid frame. A flexible and compressible continuous tape is joined to the bottom surface of the lead frame that supports the IC die and to the leads or bond fingers extending from the IC die. The thin tape is preferably made of Kapton (trademark of DuPont) and has an adhesive backing for facile attachment to the IC die pad and the bond fingers. In one embodiment, a silicon gel is applied in addition as a coating over the wires, lead fingers and the IC die to absorb stress that may be applied to the IC package elements. Description of the Drawings
The invention will be described in greater detail with reference to the drawings in which:
FIGURE 1 is a representation of a vapor phase soldering apparatus y
FIGURE 2 is a cut-away top view of an integrated circuit package assembly, incorporating the invention;
FIGURE 3 is side view of the integrated circuit package assembly illustrated in FIGURE 2; and FIGURES 4A and 4B are sectional views of alternative embodiments of the integrated circuit package assembly illustrated in FIGURE 1.
Similar numerals refer to similar elements throughout the drawing.
Detailed Description of the Invention
With reference to FIGS. 2 an 3, an integrated circuit chip 10 is mounted on a die pad 12 that is an integral part of a lead frame, as is known in the prior art. Lead fingers 16 are joined to one end of wires 18, and the other ends of the wires are connected to bond pads 20 on the IC chip. The assembly of the bonded IC chip on the die pad is encapsu¬ lated in a plastic epoxy package 22. The outer portions of the leads 16B are trimmed and formed to shape for external connection to circuit traces on a board. To minimize the problem of cracking of the package material, which may occur as a result of the vapor phase soldering process that is employed in the manufacture of some integrated circuit system subassemblies, a thin tape or film 24, preferably made of Kapton and having an adhesive backing, is attached to the bottom portions 16A of the lead fingers and to the bottom surface of the die pad. The tape is made as a continuous flexible piece that is compressible and has a thickness in the range of about .002-.005 inch, by way of example. The tape may be made of any material that can withstand the high temperatures associated with the processing of the integrated circuit package assembly and the epoxy encapsulation process, provided that the tape has the characteristics of flexibility and compressibility. in addition, to reduce stress on the bond wires 18, a protective coating 28, such as a soft gel, is placed over the bond wires and chip 10 prior to encapsulation, as shown in FIGS. 4A and 4B. The gel is supported by the continuous tape backing. In FIG. 4A, a full gel overcoat 30 is applie to encompass the wires 18 and the chip 10. In FIG. 4B, a partial gel overcoat 32 is applied over the surface of the chip and covers the bonds on the chip. The gel overcoat in each implementation is intended to absorb stresses that may appear as a consequence of the thermomechanical action of assembling the integrated circuit device with materials with different thermal properties.
By virtue of the flexible and compressible tape that is provided at the bottom of the die attach pad and which extends to the lead fingers, crack initiation and propa- gation are impeded, stresses and the transmission of forces arising from stresses in the IC package are significantly reduced. In particular, the flexible and compressible tape which is located to extend between the die attach pad and the lead fingers reduces the effect of stress concentration at "weak" points in the package assembly by blunting sharp radii, such as nicks and burrs. Also, the disclosed arrangement allows the application of full coverage of soft gel to the IC chip surface and wires without gel overflow to the backside during gel application. The application of soft gel further reduces stress at critical points in the package assembly, especially in packages incorporating relatively large dies.

Claims

CLAIMSWhat is claimed is:
1. An integrated circuit package assembly comprising: a lead frame comprising a die pad and lead fingers, said lead fingers having inner and outer portions; an integrated circuit chip mounted to said die pad; wires connecting said chip to the inner portions of said lead fingers; an encapsulant enclosing the assembly of said integrated circuit chip and said die pad to form a package; and a flexible and compressible continuous tape attached to the bottom of said die pad and to said lead fingers so that cracking of said encapsulant material is minimized.
2. An integrated circuit package as in Claim 1, including a silicon gel material for forming a stress absorbing coating on top of said IC die and said wires.
3. An integrated circuit package assembly as in Claim 2, wherein said silicon gel material encompasses the exposed surfaces of said chip, said die pad, said wires and lead fingers, said gel being supported by said continuous tape.
4. An integrated circuit package assembly as in Claim 2, wherein said silicon gel covers only the bond pads on a surface of said chip including the ends of the wire leads attached to said bond pads, and said surface of said chip.
5. An integrated circuit package assembly as in Clai 1, wherein said tape is made of Kapton having an adhesive backing for attachment to said die pad and said lead fingers.
6. An integrated circuit package assembly as in Clai 1, wherein said outer portions of the lead fingers extend from said package.
7. An integrated circuit package assembly as in Clai 1, wherein said encapsulant is made of an epoxy plastic material.
8. An integrated circuit package assembly as in Clai 1, further including a printed circuit board to which said packaged chip assembly is mounted for electrical connection.
9. An integrated circuit package assembly as in Clai 8, wherein said electrical connection is effectuated by vapor phase soldering.
PCT/US1987/002363 1987-02-20 1987-09-16 Integrated circuit package assembly WO1988006348A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US1737487A 1987-02-20 1987-02-20
US017,374 1987-02-20

Publications (1)

Publication Number Publication Date
WO1988006348A1 true WO1988006348A1 (en) 1988-08-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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WO (1) WO1988006348A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415663A1 (en) * 1989-08-28 1991-03-06 Seiko Epson Corporation Tape assembly
US5075760A (en) * 1988-01-18 1991-12-24 Texas Instruments Incorporated Semiconductor device package assembly employing flexible tape
GB2260644A (en) * 1991-10-18 1993-04-21 Samsung Electronics Co Ltd Semiconductor package
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
DE112006003866T5 (en) 2006-03-09 2009-04-16 Infineon Technologies Ag An electronic multi-chip package with reduced voltage

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US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors
US3691289A (en) * 1970-10-22 1972-09-12 Minnesota Mining & Mfg Packaging of semiconductor devices
JPS54144872A (en) * 1978-05-04 1979-11-12 Omron Tateisi Electronics Co Electronic circuit device
GB2081974A (en) * 1980-08-05 1982-02-24 Gao Ges Automation Org Carrier element for an ic module
US4480150A (en) * 1982-07-12 1984-10-30 Motorola Inc. Lead frame and method
JPS6084854A (en) * 1983-10-14 1985-05-14 Toshiba Corp Resin-sealed type semiconductor device
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
US4621278A (en) * 1981-12-30 1986-11-04 Sanyo Electric Co., Ltd. Composite film, semiconductor device employing the same and method of manufacturing
US4631820A (en) * 1984-08-23 1986-12-30 Canon Kabushiki Kaisha Mounting assembly and mounting method for an electronic component
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die

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Publication number Priority date Publication date Assignee Title
US3440027A (en) * 1966-06-22 1969-04-22 Frances Hugle Automated packaging of semiconductors
US3691289A (en) * 1970-10-22 1972-09-12 Minnesota Mining & Mfg Packaging of semiconductor devices
JPS54144872A (en) * 1978-05-04 1979-11-12 Omron Tateisi Electronics Co Electronic circuit device
GB2081974A (en) * 1980-08-05 1982-02-24 Gao Ges Automation Org Carrier element for an ic module
US4621278A (en) * 1981-12-30 1986-11-04 Sanyo Electric Co., Ltd. Composite film, semiconductor device employing the same and method of manufacturing
US4480150A (en) * 1982-07-12 1984-10-30 Motorola Inc. Lead frame and method
US4558510A (en) * 1983-03-31 1985-12-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor device
JPS6084854A (en) * 1983-10-14 1985-05-14 Toshiba Corp Resin-sealed type semiconductor device
US4631820A (en) * 1984-08-23 1986-12-30 Canon Kabushiki Kaisha Mounting assembly and mounting method for an electronic component
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075760A (en) * 1988-01-18 1991-12-24 Texas Instruments Incorporated Semiconductor device package assembly employing flexible tape
EP0415663A1 (en) * 1989-08-28 1991-03-06 Seiko Epson Corporation Tape assembly
US5177596A (en) * 1989-08-28 1993-01-05 Seiko Epson Corporation Electronic component mounting structures for fpc tape carrier and methods of separation and application
US5389191A (en) * 1989-08-28 1995-02-14 Seiko Epson Corporation Mounting apparatus for deploying an electronic component mounts formed on a tape carrier
US5427641A (en) * 1989-08-28 1995-06-27 Seiko Epson Corporation Method of forming a mounting structure on a tape carrier
GB2260644A (en) * 1991-10-18 1993-04-21 Samsung Electronics Co Ltd Semiconductor package
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
DE112006003866T5 (en) 2006-03-09 2009-04-16 Infineon Technologies Ag An electronic multi-chip package with reduced voltage
US8604595B2 (en) 2006-03-09 2013-12-10 Infineon Technologies Ag Multi-chip electronic package with reduced stress
DE112006003866B4 (en) * 2006-03-09 2019-11-21 Infineon Technologies Ag A reduced voltage electronic multi-chip package and method of making the same

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