WO1988010468A1

WO1988010468A1 - Multiply-installable, multi-processor board for personal computer and workstation expansion buses

Info

Publication number: WO1988010468A1
Application number: PCT/US1988/002109
Authority: WO
Inventors: Samuel Winston Bogoch
Original assignee: Human Devices, Inc.
Priority date: 1987-06-19
Filing date: 1988-06-17
Publication date: 1988-12-29
Also published as: AU1993088A

Abstract

A configuration of multiple microprocessors is on a single circuit board which is connectable to the expansion bus of a personal computer or workstation (15). The circuit board of the invention includes a plurality of microprocessor systems and a common communications board bus (6) interconnecting the microprocessor systems with an electronic control means (5). A communications bus connects the board bus (6) to the expansion bus (16) of the personal computer or workstation (15) to provide control communication between the personal computer or workstation (15) and the microprocessor systems.

Description

MULTIPLY-INSTALLABLE, MULTI-PROCESSOR BOARD FOR PERSONAL COMPUTER AND WORKSTATION EXPANSION BUSES

BACKGROUND OF THE INVENTION

Parallel processing, or the use of a multiple of processors, executing programs.concurrently to speed up computation, is a technique well known in the art. Until now, however, computers employing parallel processing have been complex, expensive and difficult to program due to their largely nonstandard system components. There are many examples of such computers in the prior art, exemplified by U.S. Pat. Nos. 3,300,764, 4,351,025, 4,564,900, 4,591,977, and 4,591,981.

SUMMARY OF THE INVENTION

The present invention employs a novel configuration of multiple microprocessors, memory and other circuitry to allow many personal computers to be upgraded to parallel processing with the installation of a single board containing many processors in the expansion bus of the personal computer, and allows for installation of as many of these boards as the logical and physical capacity of the expansion bus will allow. Furthermore, the board is designed so that the internal logical organization of microprocessors on the board is reproduced at the level of boards within the PC expansion bus, and may be further reproduced as entire PC expansion buses within larger systems, and indeed at any hierarchical level. Thus an upgrade path is created from a simple personal computer to a true parallel supercomputer, with considerable software compatibility as the system is upgraded.

One object of the present invention is to provide a circuit board which may be installed singly in the bus of a personal computer, thereby providing that personal computer with at least four additional processing elements, each capable of executing and manipulating data independently from the others.

It is another object of the present invention that said circuit board be multiply installable in the bus of a personal computer, up to the physical capacity (number of slots) or logical capacity (number of memory- mapped and I/O mapped addresses) of the personal computer bus.

- It is another object of the present invention that the board be designed so that logical organization and control structure of multiply-installed boards within the personal computer be logically similar to the logical organization and control structure of processing elements within one board.

It is a further object of the present invention to allow communication to and from each processor in an orderly fashion.

It is another object of the present invention that it allow simultaneous transmission of programs or data to many processors at once from a single source.

The invention consists of a circuit board configuration containing a number of microprocessor systems, referred to as processing elements, and a common communications pathway, referred to as the board bus. The circuit board also contains control circuitry and an interface to the bus in which the board is installed, referred to as the host processor bus. Each processing element consists of at least one microprocessor integrated circuit, at least one memory integrated circuit and associated decoding and support circuitry, whose address, data and control lines are connected in what is referred to as the local bus. Additional circuitry such as additional memory, input/output or coprocessor integrated circuits may be included in the design of the processing elements, depending on performance requirements, but at the expense of compactness and low power consumption per element. Each element must also contain a set of controllable bidirectional logic buffers, referred to as element buffers, which connect, address, data and control lines of the element's local bus to the corresponding lines on the board bus. If the element buffers are disabled, the local bus is isolated from the board bus, and the processing element can function independently. The board bus serves as the communications pathway between processing elements. An additional set of controllable bidirectional buffers, referred to as the host processor buffers, connect address, data and control lines of the board bus to the corresponding lines on the host processor bus.

At least one processing element may contain additional circuitry to allow it to directly control the board bus and other processing elements on the board; this processing element is referred to as the controlling element. The element buffers of the controlling element are referred to as the controlling element buffers. The controlling element may also contain specialized circuitry to perform its DMA transfers at high speeds. as well as input-output circuitry to allow direct attachment to external devices without regard to the host processor bus. Also on the board are address decoding circuitry, to signal when the host processor is accessing the board, host buffers, to permit data and addresses to be transmitted between the host and board during said accesses, and a control register, associated control logic, and a set of element- select lines (one per element) and control lines, to arbitrate access to the board bus and processing elements. A set of service-request lines may also be provided, to allow processing elements to request service routines to be performed by the controlling element. Finally, there is a clock generator, which generates a synchronous system clock for all processors on the board; this can be disabled in favor, of a host processor system clock in systems where synchronous operation between the host -processor and boards is desired.

Memory-mapped decoding may be employed for access to the processing elements by the controlling element, meaning that the memories of processing elements are mapped into logical memory regions of the controlling element. Memory-mapped decoding may also be employed for access to the processing elements by the host processor, meaning that the memories of processing elements are mapped into logical memory regions of the host processor, although not necessarily with the same mapping as used for the controlling element. Memory- mapped decoding is also employed for access to the controlling element by the host processor, meaning that the memory of the controlling element is mapped into a logical memory region of the host processor. In cases where the memory map size of the host processor is limited, one or more input-output mapped registers may. be used to supplement the memory-mapped decoding. BRIEF DESCRIPTION OF THE DRAWING

FIG.l is a block diagram of the preferred embodiment, showing the logical arrangement of the processing elements, board bus and host processor bus. A configuration with one controlling element and four processing elements is illustrated as an example.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

Operation of the board is as follows: the processing elements 1,2,3,4 do not actively control the board bus 6 or host processor bus 16. Instead, direct memory access (DMA) is employed under control of the host processor 15 or controlling element 5 to read and .write data from and to the processing elements 1,2,3,4.

When the controlling element 5 needs to access the memory of one of the processing elements 1 through 4, it initiates a read or write operation to that region of its memory map occupied by that processing element, in this case processing element 1 for purposes of illustration. The control logic 8 tied to the control register 7 then initiates a wait signal which causes the controlling element 5 to lengthen the read or write cycle. Simultaneously, the control logic 8 activates the controlling element buffers 9, and using the processing element select line 11 (from among lines 11 through 14), signals the selected processing element 1 to suspend operation. Processing element 1 then suspends operation and relinquishes control of the local bus, at the same time activating its processing element buffers 21 and causing the control logic 8 to discontinue the wait signal. At this point, the controlling element 5 has direct access to the local memory of processing element 1, and the read or write operation can be completed. The element select line 11 remains active until another processing element is selected or the control register 7 is cleared, so that subsequent read or write operations to the memory of processing element 1 take place without wait states. Accessing another processing element (2 through 4), or clearing the control register 7, causes the control logic 8 to inactivate the element select line 11, allowing the microprocessor in the previously selected processing element 1 to inactivate its element buffers 21, thus isolating its local bus from the board bus. At this point, the previously selected processing element's microprocessor resumes program execution.

The control register and circuitry also provide for a broadcast mode, in which multiple processing elements 1, 2, 3, and 4 may be simultaneously accessed via DMA. This mode operates^' similarly to single-element DMA, except that reading from the processing elements' memories, which would cause massive data line contention - on the board bus 6, is disallowed; only writes may be performed in broadcast mode. This mode is available to controlling element 5, which can use it to access all processing elements on its board.

Access to controlling element 5 by the host processor 15 functions in a similar manner to access by the processing elements 1 through 4 by controlling element 5, with a few differences. Much as the controlling element 5 employs its high-order addressing to select a processing element, the host processor 15 must employ its high-order addressing to select the board in question, at which point controlling element select line 28 becomes active. Controlling element 5 then suspends operation and relinquishes control of its local bus, at the same time activating host processor buffers and causing the control logic 8 to discontinue the host wait signal. At this point the local bus of the controlling element 5 becomes a logical extension of the host bus 16 in which the board is installed, and reads and writes to the controlling element's memory may be performed by the host.

Additionally, the host now may have access to the board bus and processing elements, since they logically reside in the controlling element's memory map which is available to the host. Access to the processing elements can proceed in exactly the same fashion as described above, except that it is the host, acting via the local bus of the controlling element, which selects processing elements and performs reads and writes.

Provision is also made for a debug mode, in which control logic 8 sends non-maskable interrupt (NMI) signals to one or more processing elements; these non¬ maskable interrupts may be used to force execution of debugging programs, previously written to element memory by DMA, which facilitate the discovery of errors in other programs being executed by the processing element. An example of such a debugging program would be a 'register dump and wait¹ program, which would cause the processing element's microprocessor to write the contents of its internal registers to a preassigned area in memory, then execute a loop of null instructions. This memory could then be read by the host processor or controlling element in a subsequent DMA operation, to determine the exact microprocessor status at the time the NMI was asserted.

In the preferred embodiment of the invention, the host processor is an IBM PC or compatible personal computer, and the host processor bus is therefore the IBM PC bus, as described in detail in the IBM Personal Computer technical reference manual. The board illustrated in fig. 1 contains four processing elements (more than four processing units may be used) , where each processing element consists of the following components: a UPD70108C10 serves as the microprocessor 1,2,3,4, an 62256 static random-access memory serves as memory 41,42,43,44, a PAL16R4 programmable logic device and 74HC573 octal latch serve as support circuitry 51,52,53,54, and one 74HC245 octal bidirectional buffer and one 74ΞC573 octal latch are used to implement the - processing element buffers 21,22,23,24.

One controlling element is provided, which contains a UPD70208C10 which serves as the microprocessor as well as an 62256 static random-access memory, a 74HC573 octal latch which serves as support circuitry, and one 74HC245 and.one„74HC573 which serve as the controlling element buffers. The controlling element also contains a semicustom 2000-gate array circuit HD003 to perform high-speed DMA data transfer to and from the processing - elements, and a Zilog 8536 integrated circuit to perform input or output to devices other than the host PC. The board bus 6 consists of 16 conductors running the length of the board, which are connected to the respective 16 pins on the processing element buffers 21,22,23,24 of each of the four processing elements, as well as to the respective 16 pins on the controlling element buffers of the controlling element. Of these 16 conductors, 7 carry address lines A8-A14, 8 carry multiplexed address/data lines AD0-AD7, and the remaining line carries the read/write line. The host processor buffer is implemented by one 74HC245 octal bidirectional buffer circuit and two 74HC573 octal latch circuits. The decoding circuitry is implemented on semicustom 2000- gate array circuit HD001, and the control register and accompanying logic are implemented in semicustom 2000- gate array circuit HD002. The above described preferred embodiment of the invention is meant to be representative only, as certain changes may be made therein by those skilled in the art without departing from the clear teachings of the invention. Accordingly, reference should be made to the following claims which alone define the invention.

Claims

I claim:

1. A circuit board for installation in an expansion bus of a personal computer or workstation, which circuit board comprises:

(a) a plurality of processing elements;

(b) each of said processing elements including a microprocessing means, a memory means and an interface circuitry means; each of said microprocessing means, memory means and interface circuitry means being electrically and operatively connected to one another by a local bus;

(c) an electronic control means;

(d) a board bus electrically and operatively connecting said electronic control means to each of said processing elements for selective control by said electronic control means; and

(e) a communications bus electrically interconnecting said expansion bus of said personal computer or workstation and the board bus to provide control communication between said personal computer or workstation and said processing elements.

2. The circuit board according to claim 1 wherein a configurable decoding circuitry means is provided to-permit installation of multiple circuit boards, each of said circuit boards being of the type set forth in claim 1, in the expansion bus of the personal computer or workstation.

3. The circuit board according to claim 2 wherein the protocol for communication between the personal computer or workstation and the processing elements is direct memory access by means of the expansion bus and board bus, under control of the personal computer or workstation.

4. The circuit board according to claim 1 further characterized by:

(a) said electronic control means comprises at least one controlling element mounted on said circuit board and operable to control the board bus, said controlling element including a processing means, a memory means, and an interface circuitry means; each of said processing means, memory means and interface circuitry means being electrically and operatively connected to one another by a local control bus;

(b) said controlling element electrically interconnecting said board bus and said communications bus.

5. The circuit board according to claim 4 wherein the protocol for communication between the controlling element and the processing elements is ^'direct memory access by means of the board bus, under control of the controlling element.

6. The circuit board according to claim 4 wherein the protocol for communication between said personal computer or workstation and the controlling element is direct memory access by means of the communications bus, under control of the personal computer or workstation.

7. The circuit board according to claim 4 wherein the protocol for communication between said personal computer or workstation and the processing elements is direct memory access by means of the communications bus, local control bus and board bus, under control of the personal computer or workstation.

8. The circuit board according to claim 2 wherein a broadcast protocol is provided for simultaneously transmitting identical data from the personal computer or workstation to multiple processing elements on one or more circuit boards.

9. The circuit board according to claim 4 wherein a broadcast protocol is provided for simultaneously transmitting identical data from the personal computer or workstation to multiple controlling elements on one or more circuit boards each of said circuit boards being of the type set forth in claim 1.

10. The circuit board according to claim 4 wherein the controlling element includes a dedicated direct memory access controller circuit means operable to perform direct memory access at high speeds.

11. The circuit board according to claim 4 wherein the controlling element includes a dedicated service- request controller circuit means operable to arbitrate service requests generated by said processing elements.

12. The circuit board according to claim 4 wherein the controlling element includes input and output circuits to send and receive data from external devices.