WO1989002095A1 - Lcmos displays fabricated with implant treated silicon wafers - Google Patents
Lcmos displays fabricated with implant treated silicon wafers Download PDFInfo
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- WO1989002095A1 WO1989002095A1 PCT/US1988/002965 US8802965W WO8902095A1 WO 1989002095 A1 WO1989002095 A1 WO 1989002095A1 US 8802965 W US8802965 W US 8802965W WO 8902095 A1 WO8902095 A1 WO 8902095A1
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- liquid crystal
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- crystal device
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 42
- 239000010703 silicon Substances 0.000 title claims abstract description 42
- 235000012431 wafers Nutrition 0.000 title description 9
- 239000007943 implant Substances 0.000 title description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 39
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- 239000004973 liquid crystal related substance Substances 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 23
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
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- 210000002858 crystal cell Anatomy 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 3
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- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Definitions
- This invention relates to liquid crystal display systems and particularly to liquid crystal display systems including an array of pixel electrodes formed, on a semiconductor backplate which are individually addressable through control of field effect switching devices such as metal oxide semiconductor (MOS) transistors.
- MOS metal oxide semiconductor
- Liquid crystal display systems wherein a plurality of individually addressable cells or "pixels" are arranged in a matrix array, with each of the elemental cells of the array operating as a reflective light valve.
- the liquid crystal material In the absence of applied potential, the liquid crystal material is clear, and the cell appears dark to an observer.
- electric potential above a threshold level is applied across the liquid crystal material, the liquid crystal scatters the light, much like a piece of frosted glass, and the cell appears white to the observer.
- the percentage of incident light which is scattered towards the viewing area is proportional to the magnitude of the potential applied to the liquid crystal cell, and consequently gray level display presentations may be produced.
- a composite ' presentation is built up from thousands of individually controllable elemental liquid crystal cells, each of which must be updated (the potential across the cell reprogrammed) at a rate sufficiently high to prevent observable flicker in the presentation. This may be accomplished by sandwiching a thin layer of liquid 0 crystal material between a glass plate having a transparent electrode, and a backplate having a matrix array of reflective pixel electrodes formed on a semiconductor wafer.
- the backplate also contains the individual addressing circuitry and electrical storage - ' circuitry disposed contiguous to the reflective pixel electrode for each cell.
- the addressing circuitry has included transistors such as field effect .
- each storage capacitor 0 may be formed in the semiconductor backplate by ion implantation.
- the reflective pixel electrodes form the top- plates of the storage capacitors and a plurality of highly doped areas in the substrate, each disposed under a respective one of ,5 the reflective electrodes, serves as the bottom plate of each capacitor.
- Liquid crystal display systems of the type just described are reflective displays and therefore require incident light for their operation.
- the field effect transistors (FET's) used to control the storage capacitors in the backplate are extremely sensitive even to a very low level of incident light.
- the ability of the storage capacitors to maintain the applied potential across the liquid crystal cells between pulses is seriously affected by incident light.
- the shielding effect of the reflective electrodes which lie in a plane between the front of the display and the field effect transistors is insufficient to prevent incident light from discharging the potential on the storage capacitors. This is so because there must be a gap between respective columns and rows of electrodes.
- the connecting means comprises an intermediate electrode which is connected to the FET and particularly to its source.
- the intermediate electrode extends parallel to the semiconductor backplate surface to form a capacitor with the doped layer.
- a transparent front electrode supported on a glass plate. Liquid crystal material is confined by appropriate sealing means between the front and back electrodes.
- switching devices are provided for applying an actuating voltage between selected ones of the back electrodes and the front electrode in order to effect a pictorial display.
- These switching devices may be metal oxide semiconductor field effect transistors (MOSFET's) having a source and a drain formed as doped regions in the substrate.
- MOSFET's metal oxide semiconductor field effect transistors
- Such liquid crystal displays employing MOS switching transistors are referred to as LCMOS displays.
- a plurality of equidistant parallel gate buses has been used to activate the switching transistors associated with each display cell, while a plurality of equidistant parallel supply buses has been used to supply the display activating voltage to the switching transistors.
- Each of the equidistant parallel gate buses is connected to all of the gates of a respective row of switching transistors, while each of the equidistant parallel supply buses is connected to all of the drains of a respective column of switching transistors.
- the addressing matrix including the MOS switching devices is made with standard P-Channel MOS technology. Building such circuitry using standard silicon processing techniques requires 9 mask steps for establishing source-drain diffusions, channel stop, gate oxide, polysilicon-to-diffusion contacts, polysilicon, light block, metal-to-polysilicon contacts, top metal, and bonding pads.
- Devices fabricated according to the foregoing processing techniques and structure are subject to line defects caused by one of three mechanisms: photolithography errors (scratches, photo-resist pinholes, bridging particles, etc.), oxide defects which result in polysilicon-to-substrate or diffusion shorts, or excessive leakage from the diffusions to substrate.
- photolithography errors scratches, photo-resist pinholes, bridging particles, etc.
- oxide defects which result in polysilicon-to-substrate or diffusion shorts, or excessive leakage from the diffusions to substrate.
- One of the factors contributing to excessive leakage and shorts in prior art devices is that the supply buses
- a liquid crystal matrix display is fabricated on a special silicon-on-insulator (SOI) structure.
- SOI structure includes a high quality epitaxial silicon layer disposed above a dielectric layer such as silicon nitride, which is in turn disposed above a silicon substrate.
- the high quality epitaxial silicon layer is implanted with dopant and etched to form switching device elements including channels, sources, and drains.
- a gate oxide is formed over the doped epitaxial silicon regions, and switching device gates are formed over the switching device channels.
- Suitable dielectric, pixel electrode metallization, light blocking masks and contact metallization may be deposited over the polysilicon according to well-known prior art procedures.
- source regions formed by implanting the epitaxial silicon are employed as one plate of the storage capacitors used in the liquid crystal display.
- the underlying silicon substrate serves as the second plate of the storage capacitors with the intervening dielectric layer serving as the capacitor dielectric.
- a matrix layout is employed wherein column supply buses are formed simultaneously with formation of the switching device elements, while row gate buses are formed simultaneously with creation of the switching device gates.
- the SOI structure employed according to the invention has several advantages over prior art bulk P-channel devices.
- FIG. 1 is a side sectional view of a LCMOS display device according to the preferred embodiment.
- FIG. 2 is a top view of a LCMOS display device according to the preferred embodiment.
- FIG. 3 is a side sectional view illustrating a stage in fabrication of an LCMOS display device according to the preferred embodiment.
- FIG. 4 is a side sectional view illustrating a more advanced stage in fabrication of a LCMOS display device according to the preferred embodiment.
- the preferred LCMOS display structure is illustrated in the cross-sectional drawing of FIG. 1 and the schematic top view of FIG. 2.
- a silicon substrate wafer 11 carries an implant generated dielectric layer 13 and a silicon device layer 15.
- the silicon device layer 15 includes a drain 17, a channel
- a column supply bus 37 (FIG. 2) connected to the drain 17 is also formed in the silicon device layer 15.
- An insulating layer or gate oxide 27 is formed over the drain 17, the channel 19 and the source/ capacitor region 21.
- a polysilicon gate 29 is formed on the oxide layer 27 over the channel 19. The polysilicon gate 29 is formed as part of a polysilicon layer which is patterned to additionally form gate supply buses 49
- the gate 29, the drain 17, and the source/ capacitor 21 comprise a first field effect or MOS switch structure.
- a second drain 23 is also, shown in FIG. 1, separated from the first MOS switch structure by a dielectric layer 31 comprising a dielectric such as silicon dioxide (Si0 2 ) applied over the gate 29 and gate oxide 27 after formation of the MOS switch structures.
- the second drain 23 is part of a second field effect or MOS switch structure identical to the first MOS switch structure.
- a pixel electrode 33 is formed over the dielectric layer 31.
- the pixel electrode 33 is formed of a metal conductor such as silver or aluminum and has an extension 35, which passes through an opening in the dielectric layer 31 to contact the source/capacitor 21.
- the remaining liquid crystal cell structure 36 formed above each pixel electrode 33 is formed according to conventional approaches.
- activation of the gate 29 charges a capacitor formed between the source/ capacitor region 21 and the silicon substrate 11.
- the source/capacitor region 21 thus forms one plate of a capacitor, the other plate of which is the substrate 11.
- the capacitor formed by the source/ capacitor region 21 and the substrate 11 sustains a voltage which is applied through the pixel electrode 33 to activate the liquid crystal.
- an analog video signal voltage level supplied to the drain 17 over the column bus 37 is transferred to the capacitor when the gate 29 is activated.
- FIG. 2 shows the gate oxide 27 which is formed (grown) over the silicon layer 15 in which the drains 17, channels 19, source/capacitor regions 21 and column supply buses 37 are formed.
- the centrally located, generally rectangular portion 43 of the gate oxide 27 overlies the source/capacitor region 21.
- the source/capacitor region 21 conforms to the same generally rectangular shape as, and lies slightly within the boundaries of, the overlying rectangular portion 43 of ' the gate oxide 27, as may also be seen in FIG. 1.
- the substantially rectangular portion 43 of the gate oxide 27 is connected to the portion 44 of the gate oxide 27 overlying the column supply buses 37 by a narrow channel oxide bridge 45, which generally overlies the channel 19 of the field effect device structure formed in the semiconductor layer 15.
- etched out areas 39 surround the rectangular oxide structure 43. These etched out areas 39 result when the originally planar semiconductor layer 15 is etched to form islands of semiconductor material in which the field effect device drains 17, channels 19, and sources 21 are formed.
- the etched out areas 39 serve to define the boundaries of the individual cells or pixels of the liquid crystal display and also isolate the column buses 37 from one another.
- the crosshatched area of FIG. 2 represents structure fabricated of polysilicon. The polysilicon is shaped into row electrodes 49, extensions of which form the gates 29 over the channels 19 beneath the channel oxide bridges 45.
- drains of MOS switching devices similar in function to the drains 17 of FIG. 1 were typically fabricated as P-type diffusion structures. Such P-type diffusions have been a major source of defects in prior art displays because they are isolated from the associated substrate by only a pn junction voltage breakdown.
- the preferred embodiment of FIG. 1 eliminates this problem by isolating the substrate 11 from the semiconductor material 15 in which the drain 17 and the source/capacitor region 21 are formed by means of the implant-generated dielectric layer 13.
- the implant-generated dielectric layer 13 is initially created as part of a silicon-on-insulator (SOI) structure 41 as shown in FIG. 3. It may be noted that the process of constructing an SOI structure, such as structure 41, is known in the art per se. Nevertheless, it will be briefly described hereafter.
- the SOI structure 41 is prepared by starting with a standard silicon wafer, depositing about 500 nanometers (nm) of epitaxial silicon onto it, and then implanting the wafer with a high dose of either
- ⁇ 5 - nitrogen or oxygen for example, 10 ⁇ ' to 10 atoms/cm 2 .
- the implant energy is adjusted so that the range of ion travel is peaked near the interface between the initially deposited epitaxial silicon and the substrate 11. After a thermal anneal, a structure
- epitaxial silicon layer 15 is almost equivalent to bulk silicon. In this manner, the SOI structure 41 of FIG.- 3 is formed, having a lightly doped epitaxial silicon layer 15 formed over a more heavily doped substrate 11.
- doping of the field effect drains 17, channels 19, sources 21 and column buses 37 is established in the epitaxial layer 15 according to well-known procedures.
- the epitaxial layer 15 of the SOI structure 41 is first implanted everywhere to set channel doping. After
- 25 channel doping is set by this implantation, the regions which are to become field effect device channels 19 are masked, and the remaining epitaxial layer 15 is implanted heavily, to establish doping characteristics of the source, drain and column electrodes 17, 21, 37.
- a heavy implant of this nature is the implantation of phosphorus at an energy of 150 kiloelectron volts (KEV) to obtain a concentration of 5 x 10 15 atoms/cm 2 .
- KEV kiloelectron volts
- 35 heavy implant are not critical.
- the epitaxial silicon layer 15 is masked with a second or "isolation" mask and chemically (wet) etched to create islands connected
- a layer of polysilicon is next deposited on the gate oxide 27, doped heavily for conductivity, and then
- a second 5 x 10 15 dose implant of phosphorus could be used after patterning of the undoped polysilicon to dope both the polysilicon and the source and drain regions 17, 21 in a self-aligned manner, as is
- Processing beyond this step may be identical to 30 prior art procedures for establishing the remaining LCMOS structure, including establishment of smoothing and blocking layers.
- a suitable dielectric is deposited over the structure of FIG. 4, followed by a suitable metal layer.
- the metal layer is patterned by a 35 light blocking mask to prevent activation by the projection light of the display system, as taught, for example, in U.S. Patent No. 4,239,346, assigned to Hughes Aircraft Company.
- a suitable dielectric is then deposited, followed by a contact masking operation
- Suitable dielectric materials for these operations include oxides or nitrides of silicon applied via low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor
- PECVD plasma chemical vapor deposition
- the semiconductor material 15 of both single crystal silicon and thin film transistor technology. Since the semiconductor material 15 is isolated from the silicon substrate 11 and can be patterned into islands, the device is less prone to leakage-induced defects, while still retaining the
- a further advantage of the preferred embodiment is that the substrate silicon wafer 11 can be used as a ground plane. This eliminates the need for a separate
- Defect correction at the polysilicon level may not be necessary because of expected improved yields; however, if it is necessary it can be accomplished by etching off the gate oxide 27 after the polysilicon mask operation has been completed. This could be done with or without further masking. This approach allows defect correction at higher densities, another advantage.
Abstract
An improved LCMOS display device employing a silicon-on-insulator (SOI) substrate (41) having an epitaxial silicon layer (15) lying over an implant-generated dielectric layer (13). MOS device and capacitor elements (17, 19, 21) used to activate the display are formed and interconnected in the epitaxial silicon (15). The implant-generated dielectric layer (13) and underlying silicon substrate (41) also serve as capacitor elements, thereby simplifying the structure and fabrication of the display device and providing improved operation through improved isolation of the MOS device elements formed in the epitaxial silicon (15) from the substrate (41).
Description
LCMOS DISPLAYS FABRICATED WITH IMPLANT TREATED SILICON WAFERS
BACKGROUND OF THE INVENTION 1. Field of the Invention
This invention relates to liquid crystal display systems and particularly to liquid crystal display systems including an array of pixel electrodes formed, on a semiconductor backplate which are individually addressable through control of field effect switching devices such as metal oxide semiconductor (MOS) transistors.
2. Description of the Related Art
Liquid crystal display systems are known wherein a plurality of individually addressable cells or "pixels" are arranged in a matrix array, with each of the elemental cells of the array operating as a reflective light valve. In the absence of applied potential, the liquid crystal material is clear, and the cell appears dark to an observer. When electric potential above a threshold level is applied across the liquid crystal material, the liquid crystal scatters the light, much like a piece of frosted glass, and the cell appears white to the observer. The percentage of incident light which is scattered towards the viewing area is proportional to the magnitude of the potential applied to the liquid
crystal cell, and consequently gray level display presentations may be produced.
In high resolution display systems, a composite' presentation is built up from thousands of individually controllable elemental liquid crystal cells, each of which must be updated (the potential across the cell reprogrammed) at a rate sufficiently high to prevent observable flicker in the presentation. This may be accomplished by sandwiching a thin layer of liquid 0 crystal material between a glass plate having a transparent electrode, and a backplate having a matrix array of reflective pixel electrodes formed on a semiconductor wafer. The backplate also contains the individual addressing circuitry and electrical storage -' circuitry disposed contiguous to the reflective pixel electrode for each cell. Typically, the addressing circuitry has included transistors such as field effect .transistors and the storage circuitry has comprised capacitors with the reflective pixel electrode forming BD one element or plate of the capacitor. Each field effect transistor is utilized to address an associated element of the matrix array, and the associated storage capacitor maintains the applied potential across the liquid crystal cell until the information is updated. An example of 5 this type of construction is disclosed and claimed in U.S. Patent No. 3,862,360 issued to Dill et al. , and assigned to the assignee of the present invention.
As taught in the above-identified Dill et al. patent, one element, or plate, of each storage capacitor 0, may be formed in the semiconductor backplate by ion implantation. As further taught by Dill et al., the reflective pixel electrodes form the top- plates of the storage capacitors and a plurality of highly doped areas in the substrate, each disposed under a respective one of ,5 the reflective electrodes, serves as the bottom plate of each capacitor.
Liquid crystal display systems of the type just described are reflective displays and therefore require incident light for their operation. The field effect transistors (FET's) used to control the storage capacitors in the backplate are extremely sensitive even to a very low level of incident light. As a result, the ability of the storage capacitors to maintain the applied potential across the liquid crystal cells between pulses is seriously affected by incident light. The shielding effect of the reflective electrodes which lie in a plane between the front of the display and the field effect transistors is insufficient to prevent incident light from discharging the potential on the storage capacitors. This is so because there must be a gap between respective columns and rows of electrodes.
An improved prior art display designed to alleviate adverse effects of incident light is disclosed in U.S. Patent No. 4,103,297 issued to McGreivy et al. and.assigned to the assignee of the present invention. The display of the '297 patent jLncludes a semiconductor backplate having a major surface in which a heavily doped layer is created. An array of openings arranged in a plurality of columns and rows is left in the doped layer and a switching device (FET) is formed in the semiconductor backplate within each opening. A coplanar array of closely spaced reflective back electrodes is disposed above the backplate surface, with each back electrode extending entirely over a respective one of the openings. Means are provided for electrically connecting each of the FET's to the back electrode extending over it. In the preferred embodiment disclosed in the '297 patent, the connecting means comprises an intermediate electrode which is connected to the FET and particularly to its source. The intermediate electrode extends parallel to the semiconductor backplate surface to form a capacitor with the doped layer.
- Spaced from the coplanar array of the back electrodes disclosed in the '297 patent is a transparent front electrode supported on a glass plate. Liquid crystal material is confined by appropriate sealing means between the front and back electrodes. Finally, switching devices are provided for applying an actuating voltage between selected ones of the back electrodes and the front electrode in order to effect a pictorial display. These switching devices may be metal oxide semiconductor field effect transistors (MOSFET's) having a source and a drain formed as doped regions in the substrate. Such liquid crystal displays employing MOS switching transistors are referred to as LCMOS displays. In the prior art, a plurality of equidistant parallel gate buses has been used to activate the switching transistors associated with each display cell, while a plurality of equidistant parallel supply buses has been used to supply the display activating voltage to the switching transistors. Each of the equidistant parallel gate buses is connected to all of the gates of a respective row of switching transistors, while each of the equidistant parallel supply buses is connected to all of the drains of a respective column of switching transistors. In fabrication of LCMOS displays according to the prior art, the addressing matrix including the MOS switching devices is made with standard P-Channel MOS technology. Building such circuitry using standard silicon processing techniques requires 9 mask steps for establishing source-drain diffusions, channel stop, gate oxide, polysilicon-to-diffusion contacts, polysilicon, light block, metal-to-polysilicon contacts, top metal, and bonding pads. Devices fabricated according to the foregoing processing techniques and structure are subject to line defects caused by one of three mechanisms:
photolithography errors (scratches, photo-resist pinholes, bridging particles, etc.), oxide defects which result in polysilicon-to-substrate or diffusion shorts, or excessive leakage from the diffusions to substrate. One of the factors contributing to excessive leakage and shorts in prior art devices is that the supply buses connecting the drains are isolated from the substrate by only a diode breakdown voltage. Such line defects are a source of considerable reduction in production yields and increased production costs.
It has thus appeared desirable to reduce line defects in prior art LCMOS devices. It would be additionally desirable to reduce processing steps and complexity, which contribute to such defects.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to improve liquid crystal displays;
It is another object of the invention to provide an improved structure for a LCMOS display; It is another object of the invention to reduce line defects in LCMOS displays;
It is another object of the invention to increase isolation of supply buses from the device substrate in LCMOS structures; It is still another object of the invention to provide a LCMOS structure which is simpler to fabricate. According to the invention, a liquid crystal matrix display is fabricated on a special silicon-on-insulator (SOI) structure. This SOI structure includes a high quality epitaxial silicon layer disposed above a dielectric layer such as silicon nitride, which is in turn disposed above a silicon substrate. The high quality epitaxial silicon layer is implanted with dopant and etched to form switching device elements including
channels, sources, and drains. A gate oxide is formed over the doped epitaxial silicon regions, and switching device gates are formed over the switching device channels. Suitable dielectric, pixel electrode metallization, light blocking masks and contact metallization may be deposited over the polysilicon according to well-known prior art procedures.
According to the foregoing structural approach, source regions formed by implanting the epitaxial silicon are employed as one plate of the storage capacitors used in the liquid crystal display. The underlying silicon substrate serves as the second plate of the storage capacitors with the intervening dielectric layer serving as the capacitor dielectric. In one embodiment, a matrix layout is employed wherein column supply buses are formed simultaneously with formation of the switching device elements, while row gate buses are formed simultaneously with creation of the switching device gates.
The SOI structure employed according to the invention has several advantages over prior art bulk P-channel devices. First, the SOI structure isolates both the polysilicon layer and the epitaxial silicon device layer from the bulk of the wafer, i.e. the substrate. This isolation eliminates shorts arising from leaky diodes. Second, by using the bulk of the wafer as one plate of the' storage capacitors, two entire masking layers can be eliminated. The device of the invention is thus simpler to fabricate while retaining all of the advantages of prior art LCMOS devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The just summarized invention will now be described in detail in conjunction with the drawings of which:
FIG. 1 is a side sectional view of a LCMOS display device according to the preferred embodiment.
FIG. 2 is a top view of a LCMOS display device according to the preferred embodiment.
FIG. 3 is a side sectional view illustrating a stage in fabrication of an LCMOS display device according to the preferred embodiment.
FIG. 4 is a side sectional view illustrating a more advanced stage in fabrication of a LCMOS display device according to the preferred embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred LCMOS display structure is illustrated in the cross-sectional drawing of FIG. 1 and the schematic top view of FIG. 2. In this structure, a silicon substrate wafer 11 carries an implant generated dielectric layer 13 and a silicon device layer 15. The silicon device layer 15 includes a drain 17, a channel
19, and a source/capacitor region 21 formed adjacent one another. A column supply bus 37 (FIG. 2) connected to the drain 17 is also formed in the silicon device layer 15. An insulating layer or gate oxide 27 is formed over the drain 17, the channel 19 and the source/ capacitor region 21. A polysilicon gate 29 is formed on the oxide layer 27 over the channel 19. The polysilicon gate 29 is formed as part of a polysilicon layer which is patterned to additionally form gate supply buses 49
(FIG. 2) . The gate 29, the drain 17, and the source/ capacitor 21 comprise a first field effect or MOS switch structure.
A second drain 23 is also, shown in FIG. 1, separated from the first MOS switch structure by a dielectric layer 31 comprising a dielectric such as silicon dioxide (Si02) applied over the gate 29 and gate oxide 27 after formation of the MOS switch structures. The second drain 23 is part of a second
field effect or MOS switch structure identical to the first MOS switch structure.
A pixel electrode 33 is formed over the dielectric layer 31. The pixel electrode 33 is formed of a metal conductor such as silver or aluminum and has an extension 35, which passes through an opening in the dielectric layer 31 to contact the source/capacitor 21. The remaining liquid crystal cell structure 36 formed above each pixel electrode 33 is formed according to conventional approaches.
In operation of the structure of FIG. 1, activation of the gate 29 charges a capacitor formed between the source/ capacitor region 21 and the silicon substrate 11. The source/capacitor region 21 thus forms one plate of a capacitor, the other plate of which is the substrate 11. The capacitor formed by the source/ capacitor region 21 and the substrate 11 sustains a voltage which is applied through the pixel electrode 33 to activate the liquid crystal. Typically, an analog video signal voltage level supplied to the drain 17 over the column bus 37 is transferred to the capacitor when the gate 29 is activated.
A matrix layout of devices according to FIG. 1 is illustrated in FIG. 2. FIG. 2 shows the gate oxide 27 which is formed (grown) over the silicon layer 15 in which the drains 17, channels 19, source/capacitor regions 21 and column supply buses 37 are formed. The centrally located, generally rectangular portion 43 of the gate oxide 27 overlies the source/capacitor region 21. The source/capacitor region 21 conforms to the same generally rectangular shape as, and lies slightly within the boundaries of, the overlying rectangular portion 43 of'the gate oxide 27, as may also be seen in FIG. 1. The substantially rectangular portion 43 of the gate oxide 27 is connected to the portion 44 of the gate oxide 27
overlying the column supply buses 37 by a narrow channel oxide bridge 45, which generally overlies the channel 19 of the field effect device structure formed in the semiconductor layer 15. As further shown in FIG. 2, etched out areas 39 surround the rectangular oxide structure 43. These etched out areas 39 result when the originally planar semiconductor layer 15 is etched to form islands of semiconductor material in which the field effect device drains 17, channels 19, and sources 21 are formed. The etched out areas 39 serve to define the boundaries of the individual cells or pixels of the liquid crystal display and also isolate the column buses 37 from one another. The crosshatched area of FIG. 2 represents structure fabricated of polysilicon. The polysilicon is shaped into row electrodes 49, extensions of which form the gates 29 over the channels 19 beneath the channel oxide bridges 45.
In the prior art, drains of MOS switching devices similar in function to the drains 17 of FIG. 1 were typically fabricated as P-type diffusion structures. Such P-type diffusions have been a major source of defects in prior art displays because they are isolated from the associated substrate by only a pn junction voltage breakdown. The preferred embodiment of FIG. 1 eliminates this problem by isolating the substrate 11 from the semiconductor material 15 in which the drain 17 and the source/capacitor region 21 are formed by means of the implant-generated dielectric layer 13. The implant-generated dielectric layer 13, is initially created as part of a silicon-on-insulator (SOI) structure 41 as shown in FIG. 3. It may be noted that the process of constructing an SOI structure, such as structure 41, is known in the art per se. Nevertheless, it will be briefly described hereafter.
The SOI structure 41 is prepared by starting with a standard silicon wafer, depositing about 500 nanometers (nm) of epitaxial silicon onto it, and then implanting the wafer with a high dose of either
■5 - nitrogen or oxygen, for example, 10^' to 10 atoms/cm2. The implant energy is adjusted so that the range of ion travel is peaked near the interface between the initially deposited epitaxial silicon and the substrate 11. After a thermal anneal, a structure
10 results, which, in the case of nitrogen implantation, has 300 nm of high quality silicon 15 on top of a silicon nitride insulating layer 13 which is 400 nm thick. The interfaces between the three layers 11, 13, 15 are extremely sharp and the crystalline quality of the
15 epitaxial silicon layer 15 is almost equivalent to bulk silicon. In this manner, the SOI structure 41 of FIG.- 3 is formed, having a lightly doped epitaxial silicon layer 15 formed over a more heavily doped substrate 11.
After formation of the SOI structure 41, the
20 doping of the field effect drains 17, channels 19, sources 21 and column buses 37 is established in the epitaxial layer 15 according to well-known procedures. The epitaxial layer 15 of the SOI structure 41 is first implanted everywhere to set channel doping. After
25 channel doping is set by this implantation, the regions which are to become field effect device channels 19 are masked, and the remaining epitaxial layer 15 is implanted heavily, to establish doping characteristics of the source, drain and column electrodes 17, 21, 37. One
30 example of a heavy implant of this nature is the implantation of phosphorus at an energy of 150 kiloelectron volts (KEV) to obtain a concentration of 5 x 1015 atoms/cm2. As those skilled in the art will appreciate, the exact dopant concentration used for this
35 heavy implant are not critical. In an alternate
sequence, one could employ phosphorus as a dopant with a phosphine chemical predeposition, if desired, to obtain a lower sheet resistance.
After establishing the field effect device
5 doping as just described, additional well-known processing steps are performed to bring the device to the stage illustrated in FIG. 4. The epitaxial silicon layer 15 is masked with a second or "isolation" mask and chemically (wet) etched to create islands connected
10 vertically with stripes of material. The islands include the source, drain, and channel elements of the field effect switches such as elements 17, 19, 21 of FIG. 1, while the stripes of material comprise the column buses 37. In the next step, 140 nanometers (nm) of oxide is
1.5 thermally grown over the entire etched epitaxial layer 15 to form the gate oxide 27. The application of heat in this step also serves to activate the dopant implants.
A layer of polysilicon is next deposited on the gate oxide 27, doped heavily for conductivity, and then
2CC patterned to create the gates 29 and row buses 49. Alternatively, a second 5 x 1015 dose implant of phosphorus could be used after patterning of the undoped polysilicon to dope both the polysilicon and the source and drain regions 17, 21 in a self-aligned manner, as is
25 well-known in the art.
The structure at this point is illustrated in FIG. 4.
Processing beyond this step may be identical to 30 prior art procedures for establishing the remaining LCMOS structure, including establishment of smoothing and blocking layers. Briefly, a suitable dielectric is deposited over the structure of FIG. 4, followed by a suitable metal layer. The metal layer is patterned by a 35 light blocking mask to prevent activation by the
projection light of the display system, as taught, for example, in U.S. Patent No. 4,239,346, assigned to Hughes Aircraft Company. A suitable dielectric is then deposited, followed by a contact masking operation
-5 (VIA) . Finally, deposition and patterning of the top metal and pads metal is performed. Suitable dielectric materials for these operations include oxides or nitrides of silicon applied via low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor
10 deposition (PECVD) with typical metallization material being silver, aluminum or other similar materials, many varieties of which are known in the art.
It will be appreciated that the approach of the preferred embodiment combines some of the best features
15 of both single crystal silicon and thin film transistor technology. Since the semiconductor material 15 is isolated from the silicon substrate 11 and can be patterned into islands, the device is less prone to leakage-induced defects, while still retaining the
2.0, advantage of single crystal silicon for the actual semiconductor layer 15.
A further advantage of the preferred embodiment is that the substrate silicon wafer 11 can be used as a ground plane. This eliminates the need for a separate
25 ground connection for the storage capacitors as was needed in some earlier LCMOS displays and simplifies the fabrication sequence, since the capacitor can be made using the silicon nitride insulator as the dielectric. Yields•are expected to be higher with the
30 approach of the preferred embodiment due to elimination of diffusion leakage to the substrate 11, a major line-defect causing mechanism. An additional benefit is that defects in the prior art channel stop mask result primarily in shorted lines. Defects in the isolation
35 mask which replaces the channel stop mask according to
the invention result in open display lines (column buses) or in shorted display cells, neither of which are as damaging as shorted display lines. This is particularly true for open line defects which can be accommodated by redundant drive, i.e., by providing the display actuating voltage at both ends of each column bus 37.
Defects which result from polysilicon-to-silicon shorts should be reduced as well in the preferred embodiment by the layer of silicon nitride located between the polysilicon and the silicon substrate.
Photolithography defects will still be present, but the elimination of two mask steps required in the prior art will help to limit their number.
Defect correction at the polysilicon level may not be necessary because of expected improved yields; however, if it is necessary it can be accomplished by etching off the gate oxide 27 after the polysilicon mask operation has been completed. This could be done with or without further masking. This approach allows defect correction at higher densities, another advantage.
The foregoing description has been directed to a preferred embodiment of a LCMOS display device employing a silicon-on-insulator substrate. Those skilled in the art will appreciate that many adaptations and variations in the preferred embodiment may be made without departing from the scope and spirit of the invention. Therefore, it is to be understood that the invention may be practiced other than as specifically described herein.
Claims
1. In a liquid crystal device, the structure comprising: a substrate; a dielectric layer disposed on said substrate; a layer of semiconductor material disposed on said dielectric layer; and switching device means formed in said semiconductor material for activating the liquid crystal of said liquid crystal device.
2. The structure of Claim 1 wherein said switching device means comprises a drain, channel and source of a plurality of field effect switching devices.
3. The structure of Claim 2 wherein said source further forms a capacitor with said dielectric layer and said substrate.
4. The structure of Claim 2 further including a plurality of gate means for rendering the channels of each of said field effect switching devices conductive.
5. The structure of Claim 4 wherein each said gate means is disposed above a respective said channel.
6. The structure of Claim 4 further including a plurality of first bus means formed in said semiconductor layer, each of said bus means conductively connecting the drains of a plurality of said field effect switching devices.
7. The structure of Claim 6 wherein said semiconductor layer contains etched out areas defining each said first bus means and isolating each said first bus means from each other said first bus means.
8. The structure of Claim 7 further including a plurality of second bus means, each of said second bus means conductively connecting a plurality of said gates.
9. The structure of Claim 8 wherein said substrate comprises silicon.
10. The structure of Claim 9 wherein said semiconductor material comprises silicon.
11. In- a liquid crystal display device having a plurality of separately activatable liquid crystal display cells, the structure comprising: a silicon substrate; a dielectric layer disposed on said substrate; a layer of semiconductor material disposed on said dielectric layer; and means formed in said layer of semiconductor for forming a capacitor in conjunction with said dielectric layer and said silicon substrate for activating a display cell of said liquid crystal display device and for switching an activation signal to said capacitor.
12. The liquid crystal device structure of Claim 11 wherein said dielectric layer comprises ion implanted epitaxial silicon.
13. The liquid crystal device structure of Claim 12 wherein said means for forming a capacitor and for switching comprises field effect device elements including a drain, channel, and source.
14. The liquid crystal device structure of Claim 13 wherein said source comprises one plate of said capacitor and said substrate comprises a second plate of said capacitor.
15. The liquid crystal device structure of Claim 14 wherein said dielectric layer is implanted with silicon nitride.
16. In a liquid crystal device having a plurality of separately activatable liquid crystal cells, the structure comprising: a substrate above which each of said liquid i crystal cells is disposed; and a structural layer epitaxially grown on said substrate, said layer including a semiconductor layer overlying an ion implanted dielectric layer.
17. The liquid crystal device structure of Claim 16 wherein said substrate comprises silicon.
18. The liquid crystal device structure of Claim 16 wherein said semiconductor layer comprises epitaxial silicon.
19. The liquid crystal device structure of Claim 18 wherein said ion implanted dielectric layer includes implanted ions of nitrogen or oxygen.
20. The liquid crystal device structure of Claim 19 wherein said dielectric layer is about 400 nanometers thick and said epitaxial silicon is about 300 nanometers thick.
21. The liquid crystal device structure of Claim 18 wherein said epitaxial silicon is patterned into a plurality of interconnected islands.
22. The liquid crystal device structure of Claim 21 wherein elements of a field effect device structure are formed in each of said islands.
23. The liquid crystal device structure of Claim 22 further including gate means established over each of said islands and forming part of said field effect device structure.
24. The liquid crystal device structure of Claim 23 further including bus means for connecting a plurality of said gate means.
25. The liquid crystal device structure of Claim 24 wherein said gate means and bus means are fabricated of polysilicon.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US9018887A | 1987-08-27 | 1987-08-27 | |
US090,188 | 1987-08-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1989002095A1 true WO1989002095A1 (en) | 1989-03-09 |
Family
ID=22221693
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1988/002965 WO1989002095A1 (en) | 1987-08-27 | 1988-08-23 | Lcmos displays fabricated with implant treated silicon wafers |
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WO (1) | WO1989002095A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0461362A2 (en) * | 1990-04-17 | 1991-12-18 | Canon Kabushiki Kaisha | Process for preparing a thin film semiconductor device |
EP0554063A1 (en) * | 1992-01-31 | 1993-08-04 | Canon Kabushiki Kaisha | Semiconductor device and liquid crystal display |
EP0554062A1 (en) * | 1992-01-31 | 1993-08-04 | Canon Kabushiki Kaisha | Method of manufacturing transistor bases and liquid-crystal cells provided with same |
EP0731375A2 (en) * | 1995-03-06 | 1996-09-11 | Canon Kabushiki Kaisha | Liquid crystal display apparatus |
WO2000037999A1 (en) * | 1998-12-19 | 2000-06-29 | The Secretary Of State For Defence | Active semiconductor backplane |
US7642584B2 (en) * | 1991-09-25 | 2010-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3895272A (en) * | 1972-12-20 | 1975-07-15 | Gennady Grigorievich Smolko | Thin-film microcircuit |
EP0068094A2 (en) * | 1981-06-30 | 1983-01-05 | International Business Machines Corporation | Process for forming a semiconductor device on a silicon ribbon and device thus formed |
EP0070598A1 (en) * | 1981-07-16 | 1983-01-26 | Koninklijke Philips Electronics N.V. | Display device |
US4431271A (en) * | 1979-09-06 | 1984-02-14 | Canon Kabushiki Kaisha | Display device with a thin film transistor and storage condenser |
DE3312743C2 (en) * | 1982-04-13 | 1986-12-18 | Kabushiki Kaisha Suwa Seikosha, Shinjuku, Tokio/Tokyo | Thin film MOS transistor and use of the same as a switching element in an active matrix arrangement |
-
1988
- 1988-08-23 WO PCT/US1988/002965 patent/WO1989002095A1/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3895272A (en) * | 1972-12-20 | 1975-07-15 | Gennady Grigorievich Smolko | Thin-film microcircuit |
US4431271A (en) * | 1979-09-06 | 1984-02-14 | Canon Kabushiki Kaisha | Display device with a thin film transistor and storage condenser |
EP0068094A2 (en) * | 1981-06-30 | 1983-01-05 | International Business Machines Corporation | Process for forming a semiconductor device on a silicon ribbon and device thus formed |
EP0070598A1 (en) * | 1981-07-16 | 1983-01-26 | Koninklijke Philips Electronics N.V. | Display device |
DE3312743C2 (en) * | 1982-04-13 | 1986-12-18 | Kabushiki Kaisha Suwa Seikosha, Shinjuku, Tokio/Tokyo | Thin film MOS transistor and use of the same as a switching element in an active matrix arrangement |
Non-Patent Citations (2)
Title |
---|
IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-33, No. 8, August 1986, TOMIHISA SUNATA et al., "A 640x400 Pixel Active-Matrix LCD Using a-Si TFT's", pages 1218-1221. * |
XEROX DISCLOSURE JOURNAL, Vol. 9, No. 4, July/August 1986, FANG-CHEN LUO, "Storage Capacitors in a TFT Adressed Liquid Crystal Display Panel", pages 261-262. * |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0461362A2 (en) * | 1990-04-17 | 1991-12-18 | Canon Kabushiki Kaisha | Process for preparing a thin film semiconductor device |
EP0461362A3 (en) * | 1990-04-17 | 1992-03-04 | Canon Kabushiki Kaisha | Thin film semiconductor device and process for preparing the same |
US5510640A (en) * | 1990-04-17 | 1996-04-23 | Cannon Kabushiki Kaisha | Semiconductor device and process for preparing the same |
US7642584B2 (en) * | 1991-09-25 | 2010-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
EP0554063A1 (en) * | 1992-01-31 | 1993-08-04 | Canon Kabushiki Kaisha | Semiconductor device and liquid crystal display |
EP0554062A1 (en) * | 1992-01-31 | 1993-08-04 | Canon Kabushiki Kaisha | Method of manufacturing transistor bases and liquid-crystal cells provided with same |
US5412240A (en) * | 1992-01-31 | 1995-05-02 | Canon Kabushiki Kaisha | Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness |
EP0731375A2 (en) * | 1995-03-06 | 1996-09-11 | Canon Kabushiki Kaisha | Liquid crystal display apparatus |
EP0731375A3 (en) * | 1995-03-06 | 1997-07-23 | Canon Kk | Liquid crystal display apparatus |
US5726720A (en) * | 1995-03-06 | 1998-03-10 | Canon Kabushiki Kaisha | Liquid crystal display apparatus in which an insulating layer between the source and substrate is thicker than the insulating layer between the drain and substrate |
WO2000037999A1 (en) * | 1998-12-19 | 2000-06-29 | The Secretary Of State For Defence | Active semiconductor backplane |
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