WO1989005521A1

WO1989005521A1 - Solar cell panel

Info

Publication number: WO1989005521A1
Application number: PCT/US1988/003974
Authority: WO
Inventors: Hans G. Dill; David R. Lillington; Dieter K. Zemmrich
Original assignee: Spectrolab, Inc.
Priority date: 1987-12-03
Filing date: 1988-11-07
Publication date: 1989-06-15

Abstract

A solar cell panel arrangement is disclosed wherein a plurality of solar cell matrices (10) fabricated from a single wafer of semiconductor material are connected in parallel. Each solar cell matrix (10) contains a plurality of series-connected solar cells (12) of the wrapthrough type. Each solar cell matrix (10) provides the desired system voltage. Consequently, solar cell panels according to the invention are less susceptible to damage and catastrophic power loss, since damage to one solar cell matrix will not affect the other parallel-connected solar cell matrices and only small overall power loss to the panel will result.

Description

SOLAR CELL PANEL

_! BACKGROUND OF THE INVENTION

1. Field of the Invention;

This invention relates generally to solar cells and more particularly to solar cell panels. 2. Background of the Invention:

Today, solar cells provide an energy source to power everything from cars to satellites. In a typical silicon solar cell there is a front doped semiconductor layer which receives light and a rear doped semiconductor layer. The front and rear semiconductor layers are of opposite conductivity type and a P-N junction forms where they meet. A contact is disposed on the front layer to collect current generated by any light impinging thereon, and another contact is deposited on the back of the cell. An individual single P-N junction solar cell as described above which is made of silicon will typically generate at the load point about 0.5 volts (for gallium arsenide solar cells about 0.9 volt). Moreover, no matter how large the solar cell, it will still only generate 0.5 volts. Consequently, to achieve a system voltage to power electronic components and motors, which typically is much greater than 0.5 volts, many solar cells must be connected in series until the system voltage is reached. For example, for a satellite having a system voltage of 60V, 120 individual solar cells each generating 0.5 volts must be connected together in series.

Conventionally, in spacecraft application, such as satellites, solar cells which are typically 7 cm x 7 cm square are connected in series forming a solar cell panel taking up large areas on the spacecraft. Solar cells used on spacecraft, however, are very fragile and susceptible to damage by particles such as from meteorites or concentrated energy pulses. Should one of the solar cells be hit by a particle or energy beam, the entire series connected panel could be lost, consequently resulting in significant loss of the power needed to run the electronics. There exists a need, therefore, to reduce the vulnerability of solar cell panels to such damage. At the same time space and packing density requirements must be held to a minimum. An effective approach has been developed to interconnect solar cells so they can be spaced close to one another and which is described in U.S. Patent No. 4,610,077 issued September 9, 1986 entitled "Process for Fabricating a Wraparound

Contact Solar Cell". Conventionally, in fabricating a solar cell panel, individual cell chains are tailored in size to fit into the space allocated. If on one part of the spacecraft only a small area is available for a panel, individual solar cells in the panel have to be made very small to fit in that allocated area. On the other hand, if a large area is available in another part of the spacecraft, individual solar cells in that panel are made larger. Manufacturing cells of different sizes is costly. It would be a great advantage to provide a solar cell arrangement where all cells in every solar cell panel are the same size, but flexible enough to fit into different sized areas and geometries.

SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide a solar cell panel arrangement that is less vulnerable to localized damage.

It is a further object of this invention to provide a solar cell matrix arrangement that is simple and cost effective to manufacture, providing higher yields.

It is a feature of this invention to have a matrix of very small individual solar cells connected in series which provides the system voltage at the cell level.

It is a further feature of this invention to have a plurality of solar cell matrices connected in parallel to form a solar cell panel wherein each cell matrix independently provides the necessary system voltage.

It is an advantage of this invention that should damage occur to one solar cell matrix in a given panel, other solar cell matrices will continue to provide the system voltage.

It is a further advantage of this invention that a solar cell matrix can be fabricated from a single semiconductor wafer. A solar cell arrangement according to the present invention includes a plurality of solar cell matrices connected in parallel with one another. Each solar cell matrix includes a plurality of individual solar cells connected together in series so as to provide the desired system voltage. If one solar cell matrix in the panel should be damaged and rendered inoperable, the system power will not drop significantly. Each solar cell matrix is manufactured from a single wafer. In each wafer, a P-N junction and a plurality of front and back contacts are formed. A cover glass is bonded to the front of the wafer and the wafer is cut to form a plurality of individual solar cells attached to the cover glass. The individual solar cells are connected in series to form a solar cell matrix. Ultimately, several of such solar cell matrices are connected in parallel to form a solar cell panel. Since each solar cell matrix is made from wafers, each matrix will typically be about the size of a normal solar cell. Accordingly, if one solar cell in a panel of solar cells is damaged, the loss of this solar cell will have little effect on the system power. On the other hand, in a conventional solar cell panel made with conventional solar cells, if one cell in the panel is damaged the system power could be degraded substantially since the whole series string of up to 30 or more solar cells will be lost. Other and further objects, advantages and characteristic features of the present invention will become readily apparent from the following detailed description of preferred embodiments of the invention when taken in conjunction with the appended claims.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a perspective view of a solar cell matrix in accordance with the invention. FIG. 2 is an enlarged section taken along 2-2. FIG. 3 is a front view of a solar cell panel in accordance with the invention.

FIG. 4 is an enlarged back view of the last two solar cells and diode of the solar cell matrix illustrated in FIG. 1. FIGS. 5a-5k are schematic illustrations of a preferred process sequence for fabricating a solar cell matrix.

DETAILED DESCRIPTION OF THE INVENTION

Referring now with greater particularity to FIGS. 1, 2 and 4, a solar cell matrix 10 is shown having 48 individual solar cells 12 therein arranged in rows and columns, as well as a single diode 50. Solar cells 12 are of the wrapthrough type having both contacts on the back surface 16 of solar cells 12. More specifically, each solar cell 12 has a front semiconductor layer 20 of a first conductivity type, which may be n-type conductivity, for example; and a back semiconductor layer 22 of a second conductivity type, which may be p-type conductivity. The semiconductor material for the body of solar cells 12 may be silicon or gallium arsenide, for example. Alternatively, the solar cells 12 may be thin film solar cells composed of for example gallium arsenide on germanium or silicon substrates.

Front and back semiconductor layers 20 and 22 have front and back major surfaces 14 and 16, respectively, front major surface 14 being the light receiving surface. Furthermore, each solar cell has a front and back contact 24 and 26, respectively. Front contact 24, which is illustrated in FIG. 2, has a grid pattern spaced over front surface 14 for collecting light generated current carriers from front semiconductor layer 20. In this embodiment the grid pattern 24 is a star configuration but may be any configuration designed to minimize series resistance losses. Front contact 24 is extended to the back major surface 16 of solar cells 12 by extending the front grid contact metallization 24 through hole 30, which is referred to as a wrapthrough contact 32 (see also FIG. 4). Wrapthrough contact 32, which carries current collected from front semiconductor layer 20, is insulated from the back semiconductor layer 22 by a layer of insulating material (not shown) which electrically isolates the wrapthrough contact 32 from the p-type conductivity semiconductor material of layer 22.

Wrapthrough metallization 32 may extend as a thin metallic strip 62 to the peripheral edge 34 of the solar cells 12, as shown in FIG. 4. Back contact 26 may cover most of back major surface 16, or may be gridded. Solar cells 12 are glued to cover glass 40 by an optically stable adhesive 42 such as εilicone, or alternatively Teflon bonding may be employed. The glue 42 typically forms a layer about 2 mils thick. Cover glass 40 may be made of fused silica or borosilicate, for example. Individual solar cells 12 are spaced apart by about 2 mils, for example.

Individual solar cells 12 are connected in series, thin metallic strip 62 of the wrapthrough contact 32 of one solar cell being electrically coupled to the back contact 26 of another solar cell, thereby forming a matrix of solar cells 10. For example, as shown in FIG. 4, a short strip of copper 44 may be soldered or welded to metallic strip 62 near the peripheral edge 34 of one solar cell and also soldered or welded to the back contact 26 of an adjacently located solar cell. Stitch bonding using metallic wire or ribbon may also be used to electrically connect individual solar cells 12 in series.

Diode 50, the last component in solar cell array 10, has a front semiconductor layer 20' of a first conductivity type, such as n-type conductivity; and a back layer 22' of an opposite conductivity type, such as p-type conductivity. Diode 50 has a layer of metallization disposed on its front major surface which serves as a cathode contact 52. Cathode contact 52 is wrapped through hole 56 in the diode, via wrapthrough contact 57, to the back major surface 58 over an insulator layer, not shown. This insulator layer electrically separates the cathode contact 52 and wrapthrough contact 57 from the back layer 22' which is of p-type semiconductor material. Wrapthrough metallization 57 may extend as a thin metallic strip 62• to the peripheral edge of diode 50. A back contact 59 disposed over back major surface 58 of diode 50 is a metallization layer covering most of the back major surface but being spaced from the wrapthrough metallization by a gap 67 which is typically 10-20 mils. Back contact 59 serves as the anode contact for diode 50. Metallic strip 62 of the last series-connected solar cell 64 is electrically coupled to the cathode, or front, wrapthrough contact 57 of diode 50 by adding a short strip of copper 44 to metallic strip 62 and metallic strip 62', for example. Diode 50 serves as a blocking diode to prevent current flow from the system bus back through solar cells 12 in the event of a failure of cells 12.

Individual solar cells 12 and diode 50 may be fabricated from a single wafer, which is discussed more fully below. Consequently, each solar cell matrix is typically about the same size as an ordinary solar cell. However, whereas one typical solar cell provides only about 0.5 volt (for silicon semiconductor material) , solar cell matrix 10 provides a much greater voltage since it has a plurality of 0.5 volt solar cells connected in series. For example, solar cell matrix 10 as depicted in FIG. 1 which has 48 solar cells will provide about 24 volts (for silicon solar cells) . The number of individual solar cells in a solar cell matrix can be increased or decreased to achieve a wide range of system voltage within the limits of physical size of the individual cells. As shown in FIG. 3, a plurality of solar cell matrices.10 are connected in parallel. Twenty solar cell arrays 10 are shown. First bus bar 70 is electrically coupled to the back contact 26 of the first series connected solar cell 71 (see FIG. 1) in each solar cell matrix 10. Second bus bar 74 is connected to the anode contact of the protection diode 50, namely the back contact 59 on the back surface 58. Bus bars 70 and 74 may be strips of copper arranged in rows between solar cell arrays 10. The electrical coupling between bus bars 70 and 74 and solar cell contacts 26 and 59, respectively, may be accomplished by soldering a copper tab 80 between the bus bars and the appropriate contact on the solar cell matrix. A solar cell panel 90 results which is less vulnerable to damage and power loss. For example, in the panel 90 illustrated in FIG. 3 (which has 20 solar cell matrices) , should one solar cell matrix 10 be hit by a meteorite particle causing that solar cell matrix to be open circuited, only a 5% power loss to the entire panel will result. Additional or fewer solar cell arrays can be used depending on the power requirements of the particular electronic system. Furthermore, the solar cell arrays 10 can be arranged in different patterns to fit in either small or large areas that may be available. Moreover, solar cell arrays and panels embodying the invention may be fabricated by relatively low-cost, high yield processes.

A solar cell matrix 10 can be fabricated according to a preferred method as illustrated in FIG. 5.

Components in the embodiment of FIG. 5 which are the same as or equivalent to respective components in the embodiment of FIGS. 1, 2 and 4 are designated by the same second and third reference numeral digits as their corresponding components in FIGS. 1, 2 and 4 along with the addition of a prefix numeral "1". Beginning with a wafer 101 of silicon about four inches in diameter, as illustrated in FIG. 5a, for example, wafer 101 has front and back major essentially parallel surfaces 114 and 116 respectively, see also FIG. 5b. Wafer 101 may contain a sufficient concentration of impurities to initially possess a uniform conductivity of p-type. Other semiconductor materials can also be used such as gallium arsenide or indium phosphide, for example. Wafer 101 is laser scribed to form a plurality of openings 130, forty-nine openings 130 being illustrated in FIG. 5a. Openings 130 are arranged in rows and columns. Conventional state-of-the-art laser scribing techniques may be used to form openings 130 and a neodymium yttrium aluminum garnet, or (Nd.YAG) , laser scriber has been found quite useful for cutting holes 130. However, other alternative means for providing openings 130 may be used and include, for example, cavitation, sawing, or sandblasting methods available in the silicon wafer processing art. Following laser scribing, openings 130 are etched to provide a smooth surface, and to remove crystal damage generated by laser scribing.

As shown in FIG. 5b, a shallow p+ layer 117 may be diffused into the back major surface 116 of the wafer 101. The p+ layer 117 can be produced by any p-type dopant such as boron, aluminum, or gallium, and the method of applying the dopant can be by electron beam or thermal evaporation, using a liquid, solid or gaseous source. The dopant could also be implanted using an ion beam source. The p-type dopant can be thermally diffused into back surface 116 using a laser, infrared source, or heating source. A cost effective and reliable method of making the shallow p+ layer 117 is disclosed in an article written by Gillanders, Mardesich & Garlick, entitled "Low Alpha, Boron BSF Solar Cell", 17th IEEE Photovoltaic Specialists Conference, pp. 128-143 (1984) , which is incorporated herein by reference. The shallow p+ layer 117 may be about one micron thick, for example. For some applications in high radiation orbits the use of a p+ layer is not required, nor is it desirable. The presence or absence of this p+ layer is immaterial to the spirit of this invention.

Wafer 101 in FIG. 5b is transferred to a low temperature chemical vapor deposition (CVD) station (not shown) where a thin layer 121 of silicon dioxide, Si0₂, is deposited over the back surface 116, walls 131 of holes 130 and a portion of front surface 114 of wafer 101 as shown in FIG. 5C to a thickness typically on the order of 10,000 A. Low temperature chemical deposition processes used for forming thin oxide layers 121 are generally well known in the art and are discussed, for example, in Part 3 of "Thin Film Processes" by Vossen and Kern, Academic Press, New York, 1978 at pages 258-320.

Next, the structure of FIG. 5c is transferred to a suitable diffusion furnace (not shown) where an n-type diffusion is carried out using phosphine gas, PH₃, at approximately 800*C. and a nitrogen carrier to thereby produce shallow p-n junction 125 on the order of 0.15 to 0.2 microns in junction depth, as shown in FIG. 5d. Alternatively, the n-type layer may be formed by ion implantation or any other of the techniques previously mentioned for producing the p+ layer (laser induced diffusion) » As is known in the art, the depth of the p-n junction 125 is related to the collection efficiency of the solar cell. A discussion of this relationship may be found, for example, in "Fundamentals of Solar Cells: Photovoltaic Solar Energy Conversion" by Allen L. Fahrenbruch and Richard H. Bube, New York Academic Press, 1983. Diffused p-n junctions are also described in "Physics and Technology of Semiconductor Devices" by A.S. Grove, John Wiley and Sons, 1967. After the p-n junction 125 has been formed, oxide mask 121 is removed (not shown) using a dilute hydrofluoric acid etchant solution.

With the p-n junction 125 in place, wafer 101 is transferred to a conventional low pressure chemical vapor deposition (CVD) station (not shown) where a thin layer 135 of silicon dioxide, Si0_2/ is deposited covering walls 131 of holes 130 and adjacently located small portions of the front and back major surfaces 114 and 116, respectively, as shown in FIG. 5e, to a thickness typically on the order of 10,000A. Low temperature chemical deposition processes used for forming thin oxide layers 135 are generally well-known in the art and are discussed, for example, in Part 3 of "Thin Film Processes" by Vossen and Kern, Academic Press, New York 1978 at pages 258-320. Alternatively, Si₃N₄ or other highly insulating dielectric may be used.

Next, the structure of FIG. 5e is transferred to a conventional photoresist deposition and mask forming station (not shown) where an outer photoresist mask 141 is formed over the entire wafer 101 and Si0₂ layers 135, as shown in FIG. 5f. The formation of photoresist masks, such as the mask 141, is well-known in the art, and such masks are described, for example, by William S. DeForest in "Photoresist: Materials and Processes", McGraw-Hill, 1975. Thereafter the photoresist mask 141 on front surface 114 is exposed a first time with the desired grid contact pattern for the front major surface, such as the pattern of grid 24 in FIG. 2. The remaining front photoresist 143 is shown in FIG. 5g. The photoresist mask 141 is then exposed a second time leaving openings therethrough to the back surface in the desired pattern for the back contact (26 in FIG. 4, for example) and wrapthrough contact (32 in FIG. 4). Back photoresist is indicated by reference number 145, in FIG. 5g. With the photoresist mask 143 and 145 firmly in place, the structure of FIG. 5g is transferred to a suitable multilayer metal deposition station (not shown) where a thin multilayer metal film 151 is deposited on both sides of the masked structure of FIG. 5g to form the metallized structure of FIG. 5h. Then, using conventional photoresist liftoff techniques, the photoresist mask 143 and 145 of FIG. 5h is removed by soaking in a suitable solvent to thereby carry away portions of the metallization lying thereover, leaving metallization as shown in FIG. 5i. Thin grid lines 124 of the completed solar cell structure of FIG. 5i are preferably titanium-palladium-silver, with titanium being the initial or surface layer of about 500 A in thickness, the palladium being the next or middle layer of approximately 800 A in thickness, and the upper layer being silver of about 5 microns in thickness. Wraparound contact 132 and the back surface contact 126 for the solar cell are preferably aluminum-titanium-palladium-silver, with the titanium-palladium-silver being identical to the composition of grid lines 124, and with an added inner layer of aluminum of a thickness of about 0.15 micron. For a further discussion of multiple element metallization systems of the above type, reference may be made to Fischer and Gereth, "Transactions on Electron Devices", Vol. ED-18, No. 8, August 1971, page 457. The thin collection grid lines 124 are typically about 0.2 mils in thickness and about 1.0 mil wide. Back contacts 126 are typically of the same composition as front grid lines 124. An array of solar cells is fabricated on a single wafer with metallization for forty-nine solar cells. Wafer 101 is thereafter bonded to a cover glass 140 such as fused silica or borosilicate using an optically stable adhesive 142 such as εilicone DC-93500 adhesive (manufactured by Dow Corning) . Teflon bonding may also be employed, for example. The front 147 (FIG. 5i) of wafer 101 and metallization 124 is glued to cover glass 140 as shown in FIG. 5j.

Next the individual solar cells 161 shown in FIG. 5j are cut into independent and distinct solar cells 112 using a saw, for example, as shown in FIG. 5k. Surfaces 171 represents a cut between two adjacent solar cells 112. Consequently, the solar cell matrix 10 as shown in FIG. 1 results. An advantage of fabricating very small solar cells out of a single wafer is improved yield for complex semiconductor materials such as gallium arsenide or indium phosphide. In fabricating conventional large area solar cells, any localized defects in the semiconductor material itself, or metallization defects can render the whole cell inoperable. On the other hand, in forming a plurality of solar cells out of a wafer by the method of the invention, if a localized defect is present in the wafer, the individual solar cell encompassing that defect may be rendered inoperable but the rest of the solar cells in the matrix are still operable.

Various modifications may be made to the above-described embodiments without departing from the scope of the invention. For example, the solar cells fabricated by the present process may be of varying sizes and shapes other than square or rectangular. Additionally, one or more of the openings may be formed for the wrapthrough contact or the wrapthrough opening may be formed near the periphery of solar cells.

Claims

CLAIMSWhat is claimed is:

1. A solar cell matrix comprising: a plurality of wrapthrough solar cells arranged in rows and columns are electrically connected in series.

2. A solar cell matrix as defined in Claim 1 further including at least one diode electrically connected in series with the last series-connected diode in said solar cell matrix.

3. A solar cell matrix as defined in Claim 2 wherein said solar cells are substantially rectangular in shape.

4. A solar cell panel, comprising: a plurality of solar cell matrices arranged on a substrate and electrically connected in parallel with one another, each solar cell matrix including a plurality of solar cells, each solar cell having a semiconductor body, said body having front and back opposed substantially parallel surfaces and further having at least one hole therethrough extending from said front surface to said back surface; a front electrical contact including grid lines disposed on said front surface and wrapthrough metallization contacting said grid lines extending through said hole from said front major surface to said back major surface; a back electrical contact disposed on said back surface, said wrapthrough metallization and back major contact being electrically isolated from each other; and said solar cells in each matrix being electrically connected in series.

5. A solar cell panel as defined in Claim 4, wherein said solar cells in each of said solar cell arrays are arranged in rows and columns.

6. A solar cell panel as defined in Claim 5 wherein said semiconductor bodies are substantially rectangular in shape.

7. A solar cell panel as defined in Claim 4 wherein each solar cell matrix includes at least one diode electrically connected in series with the last series-connected solar cell in each matrix.

8. A solar cell panel arrangement, comprising: a first plurality of wrapthrough solar cells forming a first solar cell matrix, each solar cell comprising a semiconductor body having an n-type conductivity layer and an adjacent p-type conductivity layer, front and back major surfaces, respectively, and a p-n junction between said layers, said semiconductor body further having a hole therethrough from said front major surface to said back major surface; a front electrical contact on said front major surface which extends through said hole to said back major surface; a back electrical contact on said back major surface which is electrically isolated from said front electrical contact; said first plurality of wrapthrough solar cells being electrically connected together in series; a diode electrically connected in series with a preselected one of said solar cells in said first solar cell matrix; a second plurality of wrapthrough solar cells forming a second solar cell matrix, each solar cell comprising a semiconductor body having an n-type conductivity layer and an adjacent p-type conductivity layer, front and back major surfaces, respectively, and a p-n junction sandwiched between said layers, said semiconductor body having a hole therethrough from said front surface to said back surface; a front electrical contact on said front major surface which extends through said hole to said back major surface; a back electrical contact on said back major surface which is electrically isolated from said front electrical contact; said second plurality of wrapthrough solar cells being electrically connected in series; a diode electrically connected in series with a preselected one of said solar cells in said second solar cell matrix; and said first and second solar cell matrices being electrically connected in parallel.

9. A solar cell panel as defined in Claim 8 wherein said solar cells in said first and second solar cell arrays are arranged in rows and columns.

10. A solar cell panel as defined in Claim 9 wherein said solar cells are substantially rectangular in shape.

11. A method of fabricating a solar cell array comprising the steps of: providing a wafer of semiconductor material having front and back major surfaces; forming a plurality of openings from said front to said back major surfaces of said wafer; forming a p-n junction under and essentially parallel to said front major surface; depositing a layer of insulating material on said front major surface covering part of said front major surface and extending through said openings in the wafer to said back major surface; depositing metallization on said front and said back major surfaces to form a plurality front and back contacts, respectively, in relation to each opening, said front major contact being wrapped through said hole to said back major surface; securing said front major surface to a cover glass; cutting said wafer to form a plurality of individual solar cells with front and back contacts; and electrically interconnecting said solar cells in series.

12. A method for fabricating a solar cell panel comprising the steps of: providing a first wafer of semiconductor material; forming a plurality of wrapthough solar cells on said wafer; securing the front of said wafer to a cover glass; cutting said wafer to form individual wrapthrough solar cells; electrically interconnecting said individual wrapthrough solar cells in series to form a first series connected array of solar cells; providing a second wafer of semiconductor material; forming a second plurality of wrapthrough solar cells in said wafer; securing the front of said second wafer to a second cover glass; cutting said wafer to form individual wrapthrough solar cells electrically interconnecting said individual second wrapthrough solar cells in series to form a second series-connected array of solar cells; electrically connecting said first and second series connected arrays of solar cells in parallel; and attaching said solar cell arrays to a substrate.

13. The method defined in Claim 12 wherein the securing of each said wafer to the said cover glass is carried out by a layer of glue at least about one mil thick.

14. The method defined in Claim 12 wherein said solar cells are arranged in rows and columns.

15. A method of fabricating a solar cell array, comprising: providing a first wafer of semiconductor material of a first conductivity type having front and back major essentially parallel surfaces; forming a plurality of holes in said wafer extending through said wafer from the front major surface to the back major surface; forming a second conductivity type layer under said first major surface of said wafer, defining a p-n junction between said first and second conductivity layers and in a plane essentially parallel to said front and back major surfaces; depositing a layer of insulating material on said front major surface covering part of said front major surface and extending through the openings in the wafer to the back surface; depositing a like plurality of front electrical contacts on said front major surface of said wafer, said contacts being spaced apart from one another, each one of said front electrical contacts being located near one of said holes and extending through one of said holes to said back major surface on said layer of insulating material; forming a plurality of back electrical contacts underlying respective ones of said front electrical contacts, said back electrical contacts being electrically isolated from said front electrical contacts; gluing said wafer to a cover glass; cutting said wafer into a plurality of individual solar cells formed by said respective pairs of front and underlying back electrical contacts; and electrically interconnecting respective ones of said back electrical contact to respective ones of said front electrical contacts forming a first series connected array of solar cells.

16. A method for fabricating a solar panel as defined in Claim 15 wherein said first and second solar cell arrays are mounted on a rigid substrate.

17. A method for fabricating a solar panel as defined in Claim 15 wherein solar cells in respective arrays are arranged in rows and columns.