WO1989005570A1

WO1989005570A1 - Mounting substrate for leadless ceramic chip carrier

Info

Publication number: WO1989005570A1
Application number: PCT/US1988/004318
Authority: WO
Inventors: Jorge M. Hernandez
Original assignee: Rogers Corporation
Priority date: 1987-12-08
Filing date: 1988-12-02
Publication date: 1989-06-15
Also published as: IT8822889A0; GB8828691D0; JPH01204379A

Abstract

A socket (10, 40, 70, 100) for a leadless ceramic chip carrier (34, 66, 96) comprised of a ceramic material which is preferably substantially identical to the ceramic material composing the leadless chip carrier (34, 66, 96) (typically alumina). The use of the ceramic socket (10, 40, 70, 100) of the present invention provides an essentially exact match between the coefficients of thermal expansion of the chip carrier (34, 66, 96) and the socket and thereby eliminates the problems of the prior art regarding catastrophic failure of the solder joints. Another important feature of the novel leadless chip carrier socket (10, 40, 70, 100) of the present invention (in addition to its ceramic composition) is the incorporation of the decoupling function in the ceramic socket itself. As a result, undesirable lead inductance (present in prior art plastic molded sockets) is reduced as well as more efficient (relative to conventional decoupling schemes) utilization of printed wiring board (36, 68, 98, 106) ''real estate''.

Description

MOUNTING SUBSTRATE FOR LEADLESS CERAMIC CHIP CARRIER

Background of the Invention:

This invention relates generally to surface mounted leadless ceramic chip carriers. More particularly, this invention relates to a socket for a surface moμnted leadless chip carrier comprised of a ceramic material and incorporating therein at least one capacitive element for providing noise decoupling.

It is well known that ceramic leadless chip carriers are surface mounted on printed wiring boards typically made of an epoxy glass laminate material. It is also well known that one of the most severe problems in using ceramic leadless chip carriers on surface mounted PC boards has been the large difference in the coefficient of thermal expansion between the ceramic material of the leadless IC package and the epoxy-glass laminate material of the PC board. That difference produces excessive stresses on the solder joints which connect the chip carrier to the PC board when the assembly goes through temperature excursions. As a result, the soldered joints develop fatigue and eventually crack in a catastrophic manner. This is obviously a severe reliability problem. Two common solutions have been developed for this problem. The first solution tries to match the coefficient of thermal expansion of the PC board to that of the ceramic chip carrier by adding a metal core inside the PC board. Typically, the metal core is made of copper clad Invar alloy. Unfortunately, this solution makes the PC board heavier and more expensive. In addition, this solution has other complications, such as the board becoming more like a heat sink, which makes the removal of heat from the Invar core difficult. In general, this is detrimental to the reliability of the PC board assembly.

A second typical solution is the use of plastic molded sockets, with "J" or "Gull-Wing" shaped leads for solder surface mounted attachment to the PC board and a cavity with contacts on top, in a cavity configuration, to receive the chip carrier. Sometimes, means are provided to secure the chip carrier inside the socket cavity. The complexity and tolerances required for the installed socket makes it very costly. Additionally, the socket is bulky, taking more board space than the chip carrier itself. This is a disadvantage which can be serious for those applications where board area is at a premium.

Another disadvantage of the plastic molded socket is the added "lead length" of the connections between the socket cavity contacts, down to the "J" or "Seagull-Wing" leads of the socket themselves. That length introduces extra inductance which is detrimental to the high frequency performance of the decoupling scheme.

Still another disadvantage with the use of known plastic molded sockets is that the decouplng of the leadless chip carrier is typically effected by placing one or more multilayer chip ceramic capacitors, surface mounted, close to the carrier itself and connected to the voltage and ground solder pads of the PC board by vias down into internal power and ground planes in the PC board. That scheme takes additional board area, which again can be at a premium. Solutions which have been proposed for solving this decoupling problem include the use of MLC ceramic capacitors mounted in decoupling capacitors which are then mounted over the leadless chip carrier. Examples of such decoupling capacitors are disclosed in U.S. Application S.N. 027,739 filed March 19, 1987 (now U.S. Patent

No. 4.734.819 ), U.S. Application Serial No. 028,172 filed March 19, 1987 (now U.S. Patent No. ,734,818 , _anc ^~ U.S. Application Serial No. 027,932 filed March 19, 1987, all of these applications being assigned to the assignee hereof and fully incorporated herein by reference.

Summary of the Invention:

The above-discussed and other problems and deficiencies of the prior art are overcome or alleviated by the novel socket for a surface mounted leadless chip carrier of the present invention. In accordance with the present invention, a socket for a leadless ceramic chip carrier is comprised of a ceramic material which is preferably substantially identical to the ceramic material composing the leadless chip carrier (typically alumina) . The use of the ceramic socket of the present invention provides an essentially exact match between the coefficients of thermal expansion of the chip carrier and the socket and thereby eliminates the problems of the prior art regarding catastrophic failure of the solder joints.

Another important feature of the novel leadless chip carrier socket of the present invention (in addition to its ceramic composition) is the incorporation of the decoupling function in the ceramic socket itself. As a result, undesirable lead inductance (present in prior art plastic molded sockets) is reduced as well as more efficient (relative to conventional decoupling schemes) utilization of printed wiring board "real estate". The above discussed and other features and advantages of the present invention will be appreciated and understood by those of ordinary skill in the art from the following detailed description and drawings.

Brief Description of the Drawings:

Referring now^' to the drawings, wherein like elements are numbered alike in the several FIGURES:

FIGURE 1 is a perspective plan view of a ceramic socket for use in conjunction with a leadless chip carrier in accordance with a first embodiment of the present invention; FIGURE 2 is a bottom perspective view of the socket of FIGURE 1;

FIGURE 3 is an enlarged view, partly in cross section, of a contact pin from the socket of FIGURES 1 and 2;

FIGURE 4 is a side view showing the ceramic socket of FIGURE 1 in a subassembly with a leadless ceramic chip carrier and a printed wiring board; -

FIGURE 5 is a perspective plan view of a ceramic socket for a leadless chip carrier in accordance with a second embodiment of the present invention; FIGURE 6 is a bottom perspective view of the ceramic socket of FIGURE 5;

FIGURE 7 is an enlarged cross-sectional elevation view along the line 7-7 of FIGURE 5;

FIGURE 8 is an enlarged cross-sectonal elevation view along the line 8-8 of FIGURE 6;

FIGURE 9 is a side elevation view of the ceramic socket of FIGURE 5 is a subassembly with a leadless ceramic chip carrier and a printed wiring board;

FIGURE 10 is a perspective plan view of a ceramic socket in conjunction with a leadless chip carrier in accordance with a third embodiment of the present invention;

FIGURE 11 is a bottom perspective view of the ceramic socket of FIGURE 10; FIGURE 12 is an enlarged cross-sectional elevation view along the line 12-12 of FIGURE 11; FIGURE 13 is a side elevation view of the ceramic socket of FIGURE 10 in a subassembly with a leadless ceramic chip carrier and a printed wiring^' board;

FIGURE 14 is a side elevation view of a ceramic socket similar to the ceramic socket of FIGURE 1, but adapted for through-hole mounting; and

FIGURE 15 is an enlarged side elevation view partly in cross-section, of a portion of the subassembly shown in FIGURE 14.

Description of the Preferred Embodiment:

Referring simultaneously to FIGURES 1-3, a socket for use in conjunction with a leadless ceramic chip carrier (LCCC) is shown generally at 10. Socket 10 includes a substantially rectangular or square substrate 12 comprised of a suitable ceramic material which is typically alumina. Substrate 12 includes a top surface 14 and a bottom surface 16. Top surface 14 has an array of holes 18 drilled therethrough along the four side edges thereof. Each hole is filled with a conductive material such as conductive ink to define a plurality of vias. Top surface 14 additionally includes a plurality of conductive pads 22 printed thereon in locations corresponding to conductive vias 20. Conductive pads 22 are adapted to receive and electrically connect with castellations of a well know leadless ceramic chip carrier (see FIGURE 4). Of course, conductive pads may be printed on top surface 14 using any known and conventional printing means and any known and conventional conductive ink such as silver palladium (Ag-Pd) , or tungsten conductive inks. The bottom surface 16 of ceramic substrate 12 includes a plurality of contact pins 24 which are mechanically and electrically connected to a corresponding via using any suitable conductive adhesive or solder. Preferably, each pin 24 includes a flat head 25 which contacts bottom surface 16. It will be appreciated then that an electrical bridge is formed by each via 20 electrically interconnecting conductive pads 22 to conductive pins 24. Preferably, pins 24 are relatively short and thick cylindrical pins which provide for low inductance. This pin configuration will also comply to the stress caused by thermal excursions. Preferably the pins have a length of between about 0.025" and 0.040" and a diameter of between about 0.030" and 0.050".

In addition to pins 24, lower surface 16 of substrate 12 includes a pair of opposed and spaced conductive pads 26 and 28. Each pad 26 and 28 will be electrically connected to at least one of the conductive pins 24. For example in FIGURE 2, conductive pad 26 is electrically connected to conductive pin 24* while conductive pad 28 is electrically connected to conductive pin 24". Conductive pads 26 and 28 preferably have a diverging configuration with respect to pins 24 and terminate along a relatively wide perimeter. It will be appreciated that the use of such wide conductive pads leads to low inductance. At least one decoupling capacitive element electrically communicates between pads 26 and 28. Preferably, this decoupling capacitive element comprises a known multilayer capacitive element of the type having a pair of opposed end terminations between interleaved layers of metallization and ceramic with alternating metallized layers connected to the end terminations, such as shown in U.S. Patent No. 4,584,627, assigned to the assignee hereof, all of the contents of which are incorporated herein by reference. In the FIGURE 2 embodiment, two multilayer ceramic decoupling capacitors 30 and 32 have been provided onto bottom surface 16. It will be appreciated that the respective conductive end terminations of each capacitive element 30, 32 are electrically connected to respective pads 26 and 28 using solder or some other suitable electrical adhesive material 33. It will be further appreciated that the conductive pins which are selected to be in electrical communication with conductive pads 26 and 28 (in this case, pins 24' and 24") must be electrically connected to the power and ground leads of the LCCC castellations. Thus, conductive pin 24' of FIGURE 2 will be positioned under a power or • ground castellation of a leadless ceramic chip carrier which is placed thereon. Similarly, conductive pin 24" will eventually lead to a power or ground castellation of the LCCC. Of course, each socket 10 will be tailored to have a configuration of conductive pins 24 in contact with pads 26 and 28 which correspond to the particular power and ground configuration of a selected LCCC.

In FIGURE 4, a subassembly of the ceramic socket 10 of FIGURE 1, a leadless ceramic chip carrier 34 and a printed wiring board 36 is shown. It will be appreciated that leadless chip carrier 34 is comprised of a ceramic material and has a substantially rectangular or square configuration. Along the four sides of LCCC 34 are a plurality of conductive castellations 38 which electrically connect to an integrated circuit chip within the LCCC in a well known fashion. The castellations 38 of LCCC 34 are electrically connected to corresponding conductive pads 22 on the top surface 14 of socket 10 using solder or other conductive adhesive material. As mentioned, the power and ground castellations 38 of LCCC 34 will be electrically connected to those surface pads 22 (in this case pads 22' and 22") which electrically connect to conductive pins 24 (in this case pins 24' and 24") communicating with lower conductive pads 26 and 28. Conductive pins 24 in turn are soldered or otherwise adhesively connected to surface pads 40 located on a conventional printed circuit board 36. Note that the length of conductive pins 24 must be enough so as to provide sufficient spacing for the decoupling capacitive elements 30 and 32. The leadless ceramic chip carrier socket 10 of FIGURES 1-4 thus defines a decoupling ceramic socket means.

Turning now to FIGURES 5-9, a decoupling ceramic socket in accordance with the present invention is shown generally at 40. As in socket 10, socket 40 is comprised of a block 42 of ceramic material such as alumina and includes an upper surface 44 having a pluralityOf conductive pads 46 arranged along the perimeter thereof and a lower surface 48 having a pair of opposed and spaced conductive pads 50 and 52 which are electrically interconnected by at least one (and in this case two) decoupling capacitor elements, preferably multilayer ceramic decoupling capacitor elements 54 and 56. The FIGURE 5 embodiment of the present invention substantially differs from the FIGURE 1 embodiment in the way in which upper conductive pads 46 are electrically connected to the bottom surface 48 of ceramic substrate 42. Rather than using the via structure of the FIGURE 1 embodiment, in the FIGURE 5 embodiment, a plurality of conductive J-shaped leads 58 are used to electrically interconnect top surface 44 to bottom surface 48. The J-shaped leads 58 may be comprised of any suitable conductive metal such as copper. It will be appreciated that the use of a conductive metal will impart a compliant spring action to leads 58. Preferably, two different types of leads are utilized. The majority of leads 58 will be of the type shown in FIGURE 7 wherein the lead is mechanically and electrically connected (via solder or other conductive adhesive) to a conductive mounting pad 46. The bottom end of lead 58 terminates at a flattened section 60 which is adapted for surface mounting on a mounting pad of a printed wiring board.

A second configuration of lead 58 is shown in FIGURE 8 at 58'. Lead 58' is utilized in those locations where it is necessary to interconnect a conductive pad 46 on upper surface 44 to a lower conductive pad 50 or 52 on lower surface 48. In this case, lead 58* includes a central member 64 for defining a U-shaped jaw which is received by a portion of the side edge of substrate 52. Thus as shown in FIGURE 8, an upper conductive pad 46 electrically communicates with a lower conductive pad 50 or 52 via the U-shaped portion of lead 58'. As in leads 58 of FIGURE 7, leads 58' terminate with a flattened portion 60' adapted for surface mounting on a printed wiring board.

Turning now to FIGURE 9, decoupled ceramic socket 40 is used in the same manner as previously described socket 10 and is mounted between a leadless ceramic chip carrier 66 and a printed wiring board 68 wherein the socket 40 performs both the functions of electrically interconnecting LCCC 66 to printed wiring board 68 as well as providing the important decoupling function through the use of decoupling multilayer capacitor elements 54 and 56.

In FIGURES 10-13, a preferred embodiment of the present invention is shown generally at 70. Ceramic LCCC socket 70 is similar to ceramic sockets 10 and 40 of FIGURES 1 and 5 respectively and combines some of the features of each. Ceramic socket 70 includes a substrate 72 having a top surface 74 and a bottom surface 76. Upper surface 74 includes a plurality of conductive pads 78 along the perimeter thereof while lower surface 76 includes a pair of spaced opposed pads 80 and 82 electrically interconnected by decoupling capacitive elements 84 and 86 as in the previous embodiments. In addition, as in socket 10 of FIGURES 1-4, socket 70 includes a plurality of openings through substrate 76 which are filled with a conductive material (e.g. conductive ink) to form conductive vias 88. Conductive vias 88 will either electrically interconnect upper conductive pads 78 to a plurality of conductive pads 89 on lower surface 76; or will electrically interconnect upper conductive pads 78 to lower conductive pads 80 or 82. As in socket 40 of FIGURES 5-9, socket 70 also includes a plurality of springy or compliant J-shaped leads 90. However, while J-shaped leads 58 of FIGURES 5-9 electrically bridge the opposed top and bottom surfaces of the ceramic substrate, in the FIGURE 10 embodiment of the present invention, J-shaped leads 90 are positioned along bottom surface 76 only. Thus, the J-shaped leads include an upper flattened portion 92 and a lower flattened portion 94. Upper flattened portion 92 is adapted to be supported by lower ceramic surface 76 while lower flattened portion 94 is adapted to be supported by a solder pad on a printed wiring board. Thus, as shown in FIGURE 12, an upper conductive pad 78 will electrically communicate to flattened portion 94 of lead 90 by way of via 88. As a result, as shown in FIGURE 13, socket 70 will act to interconnect a leadless ceramic chip carrier 96 to a printed wiring board 98 in a manner similar to the previously described embodiments as shown in FIGURES 4 and 9.

The ceramic socket for use with surface mounted leadless ceramic chip carriers of the present invention overcomes many of the problems and deficiencies of the prior art. For example, because the socket of the present invention is comprised of a ceramic material, the problems derived during thermal expansion wherein catastrophic joint failure often develops between the ceramic chip carrier and the printed circuit board is obviated. In addition, the many costly and inefficient solutions which have been proposed for solving problems accompanying thermal expansion such as the use of a metal core (Invar core) printed circuit board and the use of plastic molded sockets are no longer necessary. Also, the problems of conserving real estate on the surface of the printed wiring board and high inductance associated with utilizing decoupling capacitors are also obviated by incorporating the decoupling function directly within the ceramic socket of the present invention.

Still another important feature of the present invention is shown in FIGURES 14 and 15 wherein yet another embodiment of a ceramic socket is shown which in effect convert a leadless ceramic chip carrier to a through hole insertable device. FIGURES 14 and 15 show a ceramic socket 100 which is essentially similar to socket 100 and 10 is that instead of the short pins 24 having flattened bottom surfaces, socket 100 includes a plurality of pins 102 which have a narrow end termination configuration adapted for insertion onto a through-hole type printed wiring board. Thus, as shown in FIGURE 15, pin 102 has been inserted into a through-hole 104 of printed wiring board 106 and is soldered therein for electrical and mechanical connection to the wiring board. Of course, it will be appreciated that any of the other embodiments (sockets 40 or 70) of the present invention may similarly be adapted for use in connection with through-hole mounting on a printed circuit board. As as result, the decoupled ceramic socket of the present invention may be used as a means to effectively convert a surface mountable leadless ceramic chip carrier to a through-hole insertable device as is clearly shown in FIGURE 14.

While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation. What is claimed is:

Claims

CLAIM 1. A socket for mounting leadless ceramic chip carriers comprising: ceramic substrate means having opposed upper and lower planar surfaces; an array of upper conductive pads on said upper surface of said ceramic substrate means; a first lower conductive pad on said lower surface of said ceramic substrate means and a second lower conductive pad on said lower surface of said ceramic substrate means, said first and second lower conductive pads being electrically isolated from each other; at least one decoupling capacitor element means on said ceramic substrate means lower surface and electrically communicating between said first and second lower conductive pads; an array of conductive pin means attached to said ceramic substrate means, one each of said conductive pin means being electrically connected to one each of said upper conductive pads; and at least one of said conductive pin means being

" electrically connected to said first lower conductive pad and at least another one of said conductive pin means being electrically connected to said second lower conductive pad.

CLAIM 2. The socket of claim 1 wherein: said ceramic substrate means is rectangular and wherein said array of upper conductive pads terminate along the periphery of said upper surface of said ceramic substrate means and said first and second lower conductive pads terminate along the periphery of said lower surface of said ceramic substrate means.

CLAIM 3. The socket of claim 1 including: an array of electrically conductive vias through said ceramic substrate means communicating between each of said upper conductive pads and said lower surface of said substrate means; and one each of said conductive pin means being connected to one each of said vias.

CLAIM 4. The socket of claim 3 wherein: each of said conductive pin means comprises a cylindrical rod having flattened top and botttom surfaces.

CLAIM 5. The socket of claim 3 wherein: said conductive pin means has a J-shaped configuration.

CLAIM 6. The socket of claim 1 wherein: each of said conductive pin means have a J-shape.

CLAIM 7. The socket of claim 6 wherein: at least one of said J-shaped conductive pin means includes a central member extending therefrom to define a jaw for receiving an edge of said ceramic substrate means and thereby electrically interconnecting one of said upper conductive pads to one of said first and second lower conductive pads.

CLAIM 8. The socket of claim 1 wherein: said decoupling capacitor element means comprises a multilayer capacitive element having opposed end terminations.

CLAIM 9. The socket of claim 2 wherein: said first and second lower conductive pads each has a configuration which diverges away from said periphery of said lower surface of said ceramic substrate means.

CLAIM 10. The socket of claim 1 wherein: said ceramic substrate means comprises alumina.

CLAIM 11. The socket of claim 1 wherein: each of said pin means has a narrow termination to permit through-hole mounting thereof.

CLAIM 12. A socket for use with a surface mounted leadless chip carrier wherein the surface mounted leadless chip carrier package has an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the conductive connecting means being first and second voltage level conductive connecting means, the socket including: ceramic substrate means having opposed upper and lower planar surfaces; an array of upper conductive pads on said upper surface of said ceramic substrate means; a first lower conductive pad on said lower surface of said ceramic substrate means and a second lower conductive pad on said lower surface of said ceramic substrate means, said first and second lower conductive pads being electrically isolated from each other; at least one decoupling capacitor element means on said ceramic substrate means lower surface and electrically communicating between said first and second lower conductive pads; an array of conductive pin means attached to said ceramic substrate means, one each of said conductive pin means being electrically connected to one each of said upper conductive pads; at least one of said conductive pin means being electrically connected to said first lower conductive pad and at least another one of said conductive pin means being electrically connected to said second lower conductive pad; and the configurations of at least some of said pin means corresponding to configurations of first and second voltage levels of connecting means of the surface mounted leadless chip carrier package.

CLAIM 13. The socket of claim 12 wherein: said ceramic substrate means is rectangular and wherein said array of upper conductive pads terminate along the periphery of said upper surface of said ceramic substrate means and said first and second lower conductive pads terminate along the periphery of said lower surface of said ceramic substrate means.

CLAIM 14. The socket of claim 12 including: an array of electrically conductive vias through said ceramic substrate means communicating between each of said upper conductive pads and said lower surface of said substrate means; and one each of said conductive pin means being connected to one each of said vias.

CIJAIM 15. The socket of claim 14 wherein: each of said conductive pin means comprises a cylindrical rod having flattened top and botttom surfaces.

CLAIM 16. The socket of claim 12 wherein: said conductive pin means has a J-shaped configuration.

CLAIM 17. The socket of claim 12 wherein: each of said conductive pin means have a J-shape.

CLAIM 18. The socket of claim 17 wherein: at least one of said J-shaped conductive pin means includes a central member extending therefrom to define a jaw for receiving an edge of said ceramic substrate means and thereby electrically interconnecting one of said upper conductive pads to oneof said first and second lower conductive pads.

CLAIM 19. The socket of claim 12 wherein: said decoupling capacitor element means comprises a multilayer capacitive element having opposed end terminations.

CLAIM 20. The socket of claim 13 wherein: said first and second lower conductive pads each has a configuration which diverges away from said periphery of said lower surface of said ceramic substrate means.

CLAIM 21. The socket of claim 12 wherein: said ceramic substrate means comprises alumina.

CLAIM 22. The socket of claim 12 wherein: each of said pin means has a narrow termination to permit through-hole mounting thereof.

CLAIM 23. An electronic subassembly comprising: a surface mountable leadless integrated circuit chip carrier package, said leadless chip carrier package having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means; a circuit board, said circuit board having conductive pads thereon for electrically communicating with said connecting means from said leadless chip carrier package; socket means, said socket means being mounted between said surface mountable leadless integrated circuit chip carrier and said circuit board and electrically interconnecting said leadless chip carrier package to said circuit board, said socket means comprising; ceramic substrate means having opposed upper and lower planar surfaces; an array of upper conductive pads on said upper surface of said ceramic substrate means; a first lower conductive pad on said lower surface of said ceramic substrate means and a second lower conductive pad on said lower surface of said ceramic substrate means, said first and second lower conductive pads being electrically isolated from each other; at least one decoupling capacitor element means on said ceramic substrate means lower surface and electrically communicating between said first and second lower conductive pads; an array of conductive pin means attached to said ceramic substrate means, one each of said conductive pin means being electrically connected to one each of said upper conductive pads; at least one of said conductive pin means being electrically connected to said first lower conductive pad and at least another one of said conductive pin means being electrically connected to said second lower conductive pad, and the configurations of at least some of said first and second pin means corresponding to configurations of first and second voltage levels of connecting means of said leadless chip carrier package.

CLAIM 24. The subassembly of claim 23 wherein: said ceramic substrate means is rectangular and wherein said array of upper conductive pads terminate along the periphery of said upper surface of said ceramic substrate means and said first and second lower conductive pads terminate along the periphery of said lower surface of said ceramic substrate means.

CLAIM 25. The subassembly of claim 23 including: an array of electrically conductive vias through said ceramic substrate means communicating between each of said upper conductive pads and said lower surface of said substrate means; and one each of said conductive pin means being connected to one each of said vias.

CLAIM 26. The subassembly of claim 25 wherein: each of -said conductive pin means comprises a cylindrical rod having flattened top and botttom surfaces.

CLAIM 27. The subassembly of claim 25 wherein: said conductive pin means has a J-shaped configuration.

CLAIM 28. The subassembly of claim 23 wherein: each of said conductive pin means have a J-shape.

CLAIM 29. The subassembly of claim 28 wherein: at least one of said J-shaped conductive pin means includes a central member extending therefrom to define a jaw for receiving an edge of said ceramic substrate means and thereby electrically interconnecting one of said upper conductive pads to oneof said first and second lower conductive pads.

CLAIM 30. The subassembly of claim 23 wherein: said decoupling capacitor element means comprises a multilayer capacitive element having opposed end terminations.

CLAIM 31. The 'subassembly of claim 24 wherein: said first and second lower conductive pads each has a configuration which diverges away from said periphery of said lower surface of said ceramic substrate means.

CLAIM 32. The subassembly of claim 23 wherein: said ceramic substrate means comprises alumina.

CLAIM 33. The subassembly of claim 23 wherein: each of said pin means has a narrow termination to permit through-hole mounting thereof.