WO1989006456A1 - Low voltage and low power frequency synthesizer - Google Patents
Low voltage and low power frequency synthesizer Download PDFInfo
- Publication number
- WO1989006456A1 WO1989006456A1 PCT/US1988/004547 US8804547W WO8906456A1 WO 1989006456 A1 WO1989006456 A1 WO 1989006456A1 US 8804547 W US8804547 W US 8804547W WO 8906456 A1 WO8906456 A1 WO 8906456A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- vco
- capacitance
- frequency synthesizer
- memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
- H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Definitions
- the field of the invention relates to frequency synthesizers for use in communication devices and more particularly, to frequency synthesizers which operate on very low voltages and reduced power.
- Frequency synthesizer phase locked loops have been utilized in communication transceivers for some period of time.
- the normal approach is to use a varactor tuned voltage controlled oscillator in combination with controlled modulus frequency divisors in the phase locked loop to produce the desired output frequency.
- a varactor, or voltage controlled capacitor is commonly used to vary the resonant frequency of the VCO tuning network in accordance with a control voltage.
- This approach requires the use of high varactor control voltages, typically, 12 volts or more, to achieve the VCO tuning range that is needed for feedback transceiver applications.
- the voltage required and power consumed by this varactor tuning approach in a frequency synthesizer would consume excessive power and would result in a very shortened battery life.
- the present invention is intended to overcome this disadvantage of the prior art by providing a channel frequency memory which provides not only the appropriate phase locked loop divisors or a PLL-VCO synthesizer but also alters the VCO frequency tuning network by selectively adding discrete capacitors to the frequency determining network of the VCO as a course frequency adjustment.
- a channel frequency memory which provides not only the appropriate phase locked loop divisors or a PLL-VCO synthesizer but also alters the VCO frequency tuning network by selectively adding discrete capacitors to the frequency determining network of the VCO as a course frequency adjustment.
- FIG. 1 shows a block diagram of a frequency synthesizer in employing the present invention.
- FIG. 2 is an additional detailed block diagram of a portion of the frequency synthesizer shown in FIG. 1. DESCRIPTION OF THE PREFERRED EMBODIMENT '
- FIG. 1 shows a phase locked loop frequency synthesizer, which includes many parts common with the frequency synthesizers of the prior art, but also includes additional devices as taught by the present invention.
- Reference oscillator 10 provides a fixed frequency reference signal to a divider 12. The divided down frequency from divider 12 is provided as a first input to phase detector 14 which provides a signal through a low pass filter 16 as a first input of VCO 18.
- One output of VCO 18 is connected through a programmable divider 20 and back to a second input to phase detector 14.
- a memory 22 modifies programmable divider 20 to adjust the division ratio of the two signals incoming to phase detector 14 so that the VCO produces an output of FQ that is appropriate for the desired frequency synthesizer output.
- the operation of the elements as presently described, is well known in the art as a normal phase locked loop frequency synthesizer.
- Channel frequency memory 22 not only includes division information supplied to the programmable divider 20 to adjust the output frequency, but it further includes information supplied to a frequency switch matrix 24 which adds discrete capacitors directly into the frequency determining resonant network of VCO 18.
- a frequency switch matrix 24 which adds discrete capacitors directly into the frequency determining resonant network of VCO 18.
- FIG. 2 shows, in a more detailed manner, the structure of frequency matrix 24.
- the channel frequency data corresponding to the desired frequency and divisor information which is supplied to divider 20 from EEPROM memory 22 is supplied to a frequency to capacitance decoding logic block 26.
- This frequency to capacitance decoding logic supplies an output to selector switch driver logic 28 which selects various combinations of discrete capacitance from a capacitor array 30. These values are then added to the frequency determining resonant network of VCO 18.
- the output of capacitor array 30 may be one or any combination up to and including all of the capacitance. When added to the frequency determining circuit this achieves a course value of tuning for the frequency determining resonant circuit of VCO 18.
- the frequency to capacitance decoding logic interprets from a predetermined value the appropriate capacitance which must be added to the VCO to enable the VCO to tune in a low power vernier manner to achieve the resultant frequency F Q .
- the selector switch driver logic responds to the freguency to capacitance decoding logic to merely select and latch which capacitors in the capacitor array 30 must be coupled into the circuit to achieve the course tuning.
- the present low power frequency synthesizer augments the tuning capability of the VCO circuit as it is driven by an outside voltage source with discrete capacitor values to alter the tuning.
- the normal phase locked loop in combination with the altered coarse tuning provides the appropriate programmable frequency control ratio so that the synthesizer may provide the final output frequency FQ in the appropriate range for desired operation.
Abstract
A low power and low voltage frequency synthesizer includes a memory (22) containing information to provide divisor information to the variable divider (20) of a phase locked loop and information to select predetermined values of capacitance to connect to the frequency determining resonant network of the VCO (18) to provide a coarse tuning. This tuning is then further modified by the normal operation of the phase locked loop.
Description
LQ VOLTAGE AND LOW POWER FREQUENCY SYNTHESIZER
FIELD OF THE INVENTION
The field of the invention relates to frequency synthesizers for use in communication devices and more particularly, to frequency synthesizers which operate on very low voltages and reduced power.
BACKGROUND OF THE INVENTION Frequency synthesizer phase locked loops have been utilized in communication transceivers for some period of time. The normal approach is to use a varactor tuned voltage controlled oscillator in combination with controlled modulus frequency divisors in the phase locked loop to produce the desired output frequency. In these prior art techniques, a varactor, or voltage controlled capacitor, is commonly used to vary the resonant frequency of the VCO tuning network in accordance with a control voltage. This approach requires the use of high varactor control voltages, typically, 12 volts or more, to achieve the VCO tuning range that is needed for feedback transceiver applications. In the case of small portable devices, especially single cell receivers, the voltage required and power consumed by this varactor tuning approach in a frequency synthesizer would consume excessive power and would result in a very shortened battery life. The present invention is intended to overcome this disadvantage of the prior art by providing a channel frequency memory which provides not only the
appropriate phase locked loop divisors or a PLL-VCO synthesizer but also alters the VCO frequency tuning network by selectively adding discrete capacitors to the frequency determining network of the VCO as a course frequency adjustment. Thus, only a low voltage, low varactor network with a much reduced tuning range is required to fine tune the VCO and allow the loop to operate properly.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a low voltage, low powered frequency synthesizer which is capable of operating on at most a two cell battery.
It is a further object of the invention to provide a very low power frequency synthesizer utilizing a VCO that is tuned by a combination of additive capacitors and a low voltage varactor network to cover a broad range of frequencies.
It is yet a further object of the invention to provide a phase locked loop frequency synthesizer which does not require multi-cell batteries in conjunction with voltage multipliers to achieve reasonable tuning ranges.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of a frequency synthesizer in employing the present invention. FIG. 2 is an additional detailed block diagram of a portion of the frequency synthesizer shown in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT '
FIG. 1 shows a phase locked loop frequency synthesizer, which includes many parts common with the frequency synthesizers of the prior art, but also includes additional devices as taught by the present invention. Reference oscillator 10 provides a fixed frequency reference signal to a divider 12. The divided down frequency from divider 12 is provided as a first input to phase detector 14 which provides a signal through a low pass filter 16 as a first input of VCO 18. One output of VCO 18 is connected through a programmable divider 20 and back to a second input to phase detector 14. A memory 22, for the preferred embodiment, an electrically erasable programmable read only memory containing channel frequency divisor information, modifies programmable divider 20 to adjust the division ratio of the two signals incoming to phase detector 14 so that the VCO produces an output of FQ that is appropriate for the desired frequency synthesizer output. The operation of the elements as presently described, is well known in the art as a normal phase locked loop frequency synthesizer.
Channel frequency memory 22 not only includes division information supplied to the programmable divider 20 to adjust the output frequency, but it further includes information supplied to a frequency switch matrix 24 which adds discrete capacitors directly into the frequency determining resonant network of VCO 18. Thus, instead of requiring the high voltages and high current drains that are needed to drive the voltage controlled reactive elements used in prior art VCO tuning networks, fixed capacitance values can be selectively added to the frequency determining resonant network to
provide the appropriate range of frequency outputs that are necessary to provide a broadband frequency synthesis. This is achieved while conserving the normal power that would be required to achieve that tuning.
FIG. 2 shows, in a more detailed manner, the structure of frequency matrix 24. The channel frequency data corresponding to the desired frequency and divisor information which is supplied to divider 20 from EEPROM memory 22 is supplied to a frequency to capacitance decoding logic block 26. This frequency to capacitance decoding logic supplies an output to selector switch driver logic 28 which selects various combinations of discrete capacitance from a capacitor array 30. These values are then added to the frequency determining resonant network of VCO 18. The output of capacitor array 30 may be one or any combination up to and including all of the capacitance. When added to the frequency determining circuit this achieves a course value of tuning for the frequency determining resonant circuit of VCO 18.
In operation, the frequency to capacitance decoding logic interprets from a predetermined value the appropriate capacitance which must be added to the VCO to enable the VCO to tune in a low power vernier manner to achieve the resultant frequency FQ. The selector switch driver logic responds to the freguency to capacitance decoding logic to merely select and latch which capacitors in the capacitor array 30 must be coupled into the circuit to achieve the course tuning.
Thus, it may be seen that for various frequencies, rather than tuning the VCO with a high voltage varactor network and correspondingly
consuming the power required to maintain it and combining that with an appropriate divisor in programmable divider 20, the present low power frequency synthesizer augments the tuning capability of the VCO circuit as it is driven by an outside voltage source with discrete capacitor values to alter the tuning. The normal phase locked loop in combination with the altered coarse tuning provides the appropriate programmable frequency control ratio so that the synthesizer may provide the final output frequency FQ in the appropriate range for desired operation. It will be clear to those skilled in the art that the switching in of the capacitor array requires considerably less power than the power required to drive the frequency determining resonant circuit of a VCO and maintain it at a fixed voltage and frequency output position for considerable lengths of time. Thus, it may be seen that the entire operation of the frequency synthesizer occurs with considerably less power consumed and may be operated with considerable lower voltages. What is claimed is:
Claims
1. A low voltage and low power frequency synthesizer including a memory containing divisor information, a variable divider phase locked loop responsive to the divisor information for controlling the output frequency of a voltage controlled oscillator comprising: memory means (22) containing information corresponding to the desired frequency and divisor information of the VCO; and frequency capacitance switch means (24) coupled between said memory and said VCO responsive to additional information to select a predetermined value of capacitance, said switch means further including means producing a coarse tuning frequency by augmenting the value of capacitance in the frequency determining network of the VCO, whereby a broad range of frequencies can be synthesized at lower voltages and maintained with lower power consumption with the phase locked loop operating to maintain the precision of the desired frequency.
2. The frequency synthesizer of claim 1, wherein the memory means further comprises a programmable Read Only Memory (ROM) .
3. The frequency synthesizer of claim 2 , wherein said EROM is electrically erasable.
4. The frequency synthesizer of claim 1, further including a plurality of capacitors (30) from which the frequency capacitance switch means may select.
5. The frequency synthesizer of claim 4, wherein the plurality of capacitance (30) includes at least five values in a binary related sequence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP89501787A JPH03502992A (en) | 1988-01-07 | 1988-12-19 | Low voltage/low power frequency synthesizer |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/141,380 US4893087A (en) | 1988-01-07 | 1988-01-07 | Low voltage and low power frequency synthesizer |
US141,380 | 1988-01-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1989006456A1 true WO1989006456A1 (en) | 1989-07-13 |
Family
ID=22495446
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1988/004547 WO1989006456A1 (en) | 1988-01-07 | 1988-12-19 | Low voltage and low power frequency synthesizer |
Country Status (5)
Country | Link |
---|---|
US (1) | US4893087A (en) |
EP (1) | EP0394358A4 (en) |
JP (1) | JPH03502992A (en) |
AU (1) | AU3033689A (en) |
WO (1) | WO1989006456A1 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994024767A1 (en) * | 1993-04-20 | 1994-10-27 | Rca Thomson Licensing Corporation | An oscillator with switched reactive elements |
FR2738425A1 (en) * | 1995-09-05 | 1997-03-07 | Motorola Inc | METHOD AND APPARATUS FOR CONTROLLING A TUNING RANGE OF A VOLTAGE CONTROLLED OSCILLATOR IN A FREQUENCY SYNTHESIZER |
US5610560A (en) * | 1993-04-20 | 1997-03-11 | Rca Thomson Licensing Corporation | Oscillator with switched reactive elements |
US5684434A (en) * | 1995-10-30 | 1997-11-04 | Cypress Semiconductor | Erasable and programmable single chip clock generator |
US5757212A (en) * | 1995-12-21 | 1998-05-26 | Cypress Semiconductor Corp. | Method and apparatus for providing a pin configurable architecture for frequency synthesizers |
WO2002091580A2 (en) * | 2001-05-08 | 2002-11-14 | Infineon Technologies Ag | Phase locked loop |
US6597250B2 (en) | 2000-09-29 | 2003-07-22 | Koninklijke Philips Electronics N.V. | Low-noise and rapid response frequency synthesizer, and corresponding frequency synthesizing method |
US6650196B2 (en) | 2000-09-29 | 2003-11-18 | Broadcom Corporation | Multi-frequency band controlled oscillator |
US8035455B1 (en) | 2005-12-21 | 2011-10-11 | Cypress Semiconductor Corporation | Oscillator amplitude control network |
US8035401B2 (en) | 2007-04-18 | 2011-10-11 | Cypress Semiconductor Corporation | Self-calibrating driver for charging a capacitive load to a desired voltage |
US8073042B1 (en) | 2005-04-13 | 2011-12-06 | Cypress Semiconductor Corporation | Recursive range controller |
US8564252B2 (en) | 2006-11-10 | 2013-10-22 | Cypress Semiconductor Corporation | Boost buffer aid for reference buffer |
US9667240B2 (en) | 2011-12-02 | 2017-05-30 | Cypress Semiconductor Corporation | Systems and methods for starting up analog circuits |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0292021A (en) * | 1988-09-29 | 1990-03-30 | Mitsubishi Rayon Co Ltd | Digital pll circuit |
JPH07101847B2 (en) * | 1988-10-21 | 1995-11-01 | シャープ株式会社 | Digital Phase Locked Loop Device |
JPH02296410A (en) * | 1989-05-11 | 1990-12-07 | Mitsubishi Electric Corp | Delay circuit |
JP2798142B2 (en) * | 1990-06-15 | 1998-09-17 | 三菱電機株式会社 | Frequency synthesizer |
US5719514A (en) * | 1995-03-31 | 1998-02-17 | Ando Electric Co., Ltd. | Delay circuit compensating for variations in delay time |
US6115318A (en) * | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
US6912680B1 (en) | 1997-02-11 | 2005-06-28 | Micron Technology, Inc. | Memory system with dynamic timing correction |
US5940608A (en) * | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5946244A (en) | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US5953284A (en) * | 1997-07-09 | 1999-09-14 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
US6011732A (en) * | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US5940609A (en) * | 1997-08-29 | 1999-08-17 | Micorn Technology, Inc. | Synchronous clock generator including a false lock detector |
US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US6101197A (en) * | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
KR100510462B1 (en) * | 1998-03-31 | 2005-11-25 | 삼성전자주식회사 | Multi-Channel Voltage Controlled Oscillator with Automatic Adjustment and Its Oscillation Method |
US6016282A (en) * | 1998-05-28 | 2000-01-18 | Micron Technology, Inc. | Clock vernier adjustment |
US6311050B1 (en) * | 1998-05-29 | 2001-10-30 | Silicon Laboratories, Inc. | Single integrated circuit phase locked loop for synthesizing high-frequency signals for wireless communications and method for operating same |
US6137372A (en) * | 1998-05-29 | 2000-10-24 | Silicon Laboratories Inc. | Method and apparatus for providing coarse and fine tuning control for synthesizing high-frequency signals for wireless communications |
US6308055B1 (en) * | 1998-05-29 | 2001-10-23 | Silicon Laboratories, Inc. | Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications |
US7221921B2 (en) * | 1998-05-29 | 2007-05-22 | Silicon Laboratories | Partitioning of radio-frequency apparatus |
US6304146B1 (en) | 1998-05-29 | 2001-10-16 | Silicon Laboratories, Inc. | Method and apparatus for synthesizing dual band high-frequency signals for wireless communications |
US6993314B2 (en) | 1998-05-29 | 2006-01-31 | Silicon Laboratories Inc. | Apparatus for generating multiple radio frequencies in communication circuitry and associated methods |
US6327463B1 (en) | 1998-05-29 | 2001-12-04 | Silicon Laboratories, Inc. | Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications |
US6226506B1 (en) * | 1998-05-29 | 2001-05-01 | Silicon Laboratories, Inc. | Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications |
US7092675B2 (en) * | 1998-05-29 | 2006-08-15 | Silicon Laboratories | Apparatus and methods for generating radio frequencies in communication circuitry using multiple control signals |
US6147567A (en) * | 1998-05-29 | 2000-11-14 | Silicon Laboratories Inc. | Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications |
US6574288B1 (en) | 1998-05-29 | 2003-06-03 | Silicon Laboratories Inc. | Method and apparatus for adjusting a digital control word to tune synthesized high-frequency signals for wireless communications |
US6150891A (en) * | 1998-05-29 | 2000-11-21 | Silicon Laboratories, Inc. | PLL synthesizer having phase shifted control signals |
US6167245A (en) * | 1998-05-29 | 2000-12-26 | Silicon Laboratories, Inc. | Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications |
US7242912B2 (en) | 1998-05-29 | 2007-07-10 | Silicon Laboratories Inc. | Partitioning of radio-frequency apparatus |
US6233441B1 (en) | 1998-05-29 | 2001-05-15 | Silicon Laboratories, Inc. | Method and apparatus for generating a discretely variable capacitance for synthesizing high-frequency signals for wireless communications |
US7035607B2 (en) * | 1998-05-29 | 2006-04-25 | Silicon Laboratories Inc. | Systems and methods for providing an adjustable reference signal to RF circuitry |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6029250A (en) * | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6323735B1 (en) | 2000-05-25 | 2001-11-27 | Silicon Laboratories, Inc. | Method and apparatus for synthesizing high-frequency signals utilizing on-package oscillator circuit inductors |
EP1193877A1 (en) * | 2000-09-29 | 2002-04-03 | Koninklijke Philips Electronics N.V. | Fast tuning fractional-N frequency synthesizer and corresponding frequency synthesizing process |
US7103127B2 (en) * | 2001-03-30 | 2006-09-05 | Skyworks Solutions, Inc. | System for controlling the frequency of an oscillator |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
MXPA04010486A (en) * | 2002-04-23 | 2004-12-13 | Thomson Licensing Sa | Tuning apparatus. |
US6724265B2 (en) | 2002-06-14 | 2004-04-20 | Rf Micro Devices, Inc. | Compensation for oscillator tuning gain variations in frequency synthesizers |
US7162307B2 (en) * | 2003-02-11 | 2007-01-09 | Medtronic, Inc. | Channel occupancy in multi-channel medical device communication |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US6882064B2 (en) * | 2003-06-23 | 2005-04-19 | Intel Corporation | System to vary capacitance based on a control signal |
US7234070B2 (en) * | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4305045A (en) * | 1979-11-14 | 1981-12-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop clock synchronizing circuit with programmable controller |
US4330758A (en) * | 1980-02-20 | 1982-05-18 | Motorola, Inc. | Synchronized frequency synthesizer with high speed lock |
US4453136A (en) * | 1980-10-22 | 1984-06-05 | U.S. Philips Corporation | AFC System for controlling an oscillator according to an input frequency |
US4613826A (en) * | 1985-05-03 | 1986-09-23 | Kabushiki Kaisha Toshiba | Frequency synthesizer for CATV tuner |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3032378A1 (en) * | 1980-08-28 | 1982-04-01 | Robert Bosch Gmbh, 7000 Stuttgart | MULTI-CHANNEL RADIO FOR THE OPERATING MODE INTERACTION AND / OR CONDITIONAL INTERCOM |
US4631496A (en) * | 1981-04-06 | 1986-12-23 | Motorola, Inc. | Battery saving system for a frequency synthesizer |
GB2120478B (en) * | 1982-04-22 | 1985-10-16 | Standard Telephones Cables Ltd | Voltage controlled oscillator |
IT1185568B (en) * | 1985-05-17 | 1987-11-12 | Face Standard Ind | CIRCUIT DEVICE TO FACILITATE CHANNELING IN A FREQUENCY SYNTHESIZER |
US4635000A (en) * | 1985-11-12 | 1987-01-06 | Xerox Corporation | Temporal pixel clock synchronization system |
-
1988
- 1988-01-07 US US07/141,380 patent/US4893087A/en not_active Expired - Fee Related
- 1988-12-19 EP EP19890901925 patent/EP0394358A4/en not_active Withdrawn
- 1988-12-19 WO PCT/US1988/004547 patent/WO1989006456A1/en not_active Application Discontinuation
- 1988-12-19 JP JP89501787A patent/JPH03502992A/en active Pending
- 1988-12-19 AU AU30336/89A patent/AU3033689A/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4305045A (en) * | 1979-11-14 | 1981-12-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop clock synchronizing circuit with programmable controller |
US4330758A (en) * | 1980-02-20 | 1982-05-18 | Motorola, Inc. | Synchronized frequency synthesizer with high speed lock |
US4453136A (en) * | 1980-10-22 | 1984-06-05 | U.S. Philips Corporation | AFC System for controlling an oscillator according to an input frequency |
US4613826A (en) * | 1985-05-03 | 1986-09-23 | Kabushiki Kaisha Toshiba | Frequency synthesizer for CATV tuner |
Non-Patent Citations (1)
Title |
---|
See also references of EP0394358A4 * |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994024767A1 (en) * | 1993-04-20 | 1994-10-27 | Rca Thomson Licensing Corporation | An oscillator with switched reactive elements |
US5610560A (en) * | 1993-04-20 | 1997-03-11 | Rca Thomson Licensing Corporation | Oscillator with switched reactive elements |
FR2738425A1 (en) * | 1995-09-05 | 1997-03-07 | Motorola Inc | METHOD AND APPARATUS FOR CONTROLLING A TUNING RANGE OF A VOLTAGE CONTROLLED OSCILLATOR IN A FREQUENCY SYNTHESIZER |
US6433645B1 (en) | 1995-10-30 | 2002-08-13 | Cypress Semiconductor Corp. | Programmable clock generator |
US5877656A (en) * | 1995-10-30 | 1999-03-02 | Cypress Semiconductor Corp. | Programmable clock generator |
US5684434A (en) * | 1995-10-30 | 1997-11-04 | Cypress Semiconductor | Erasable and programmable single chip clock generator |
US5757212A (en) * | 1995-12-21 | 1998-05-26 | Cypress Semiconductor Corp. | Method and apparatus for providing a pin configurable architecture for frequency synthesizers |
US6597250B2 (en) | 2000-09-29 | 2003-07-22 | Koninklijke Philips Electronics N.V. | Low-noise and rapid response frequency synthesizer, and corresponding frequency synthesizing method |
US6650196B2 (en) | 2000-09-29 | 2003-11-18 | Broadcom Corporation | Multi-frequency band controlled oscillator |
WO2002091580A2 (en) * | 2001-05-08 | 2002-11-14 | Infineon Technologies Ag | Phase locked loop |
WO2002091580A3 (en) * | 2001-05-08 | 2003-04-10 | Infineon Technologies Ag | Phase locked loop |
US6924706B2 (en) | 2001-05-08 | 2005-08-02 | Infineon Technologies Ag | Phase locked loop |
US8073042B1 (en) | 2005-04-13 | 2011-12-06 | Cypress Semiconductor Corporation | Recursive range controller |
US8526558B1 (en) | 2005-04-13 | 2013-09-03 | Cypress Semiconductor Corporation | Recursive range controller |
US8035455B1 (en) | 2005-12-21 | 2011-10-11 | Cypress Semiconductor Corporation | Oscillator amplitude control network |
US8564252B2 (en) | 2006-11-10 | 2013-10-22 | Cypress Semiconductor Corporation | Boost buffer aid for reference buffer |
US8164365B2 (en) | 2007-04-18 | 2012-04-24 | Cypress Semiconductor Corporation | Non-resistive load driver |
US8035401B2 (en) | 2007-04-18 | 2011-10-11 | Cypress Semiconductor Corporation | Self-calibrating driver for charging a capacitive load to a desired voltage |
US8570073B2 (en) | 2007-04-18 | 2013-10-29 | Cypress Semiconductor Corporation | Load driver |
US9124264B2 (en) | 2007-04-18 | 2015-09-01 | Cypress Semiconductor Corporation | Load driver |
US9923559B2 (en) | 2007-04-18 | 2018-03-20 | Monterey Research, Llc | Load driver |
US10418990B2 (en) | 2007-04-18 | 2019-09-17 | Monterey Research, Llc | Load driver |
US11223352B2 (en) | 2007-04-18 | 2022-01-11 | Monterey Research, Llc | Load driver |
US9667240B2 (en) | 2011-12-02 | 2017-05-30 | Cypress Semiconductor Corporation | Systems and methods for starting up analog circuits |
Also Published As
Publication number | Publication date |
---|---|
EP0394358A4 (en) | 1991-04-10 |
AU3033689A (en) | 1989-08-01 |
US4893087A (en) | 1990-01-09 |
JPH03502992A (en) | 1991-07-04 |
EP0394358A1 (en) | 1990-10-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4893087A (en) | Low voltage and low power frequency synthesizer | |
US5598405A (en) | Time division multiple access time division duplex type transmitter-receiver | |
US5909149A (en) | Multiband phase locked loop using a switched voltage controlled oscillator | |
US6229399B1 (en) | Multiple frequency band synthesizer using a single voltage control oscillator | |
US4088959A (en) | Multiple-band digital frequency synthesizer receiver | |
US7432768B2 (en) | Voltage controlled digital analog oscillator and frequency synthesizer using the same | |
EP0051774A1 (en) | Battery saving frequency synthesizer arrangement | |
US20120142283A1 (en) | Wireless communication apparatus | |
US5175511A (en) | Phase-locked loop synthesizer for use in tdm communications system | |
US6157821A (en) | Voltage step up for a low voltage frequency synthesizer architecture | |
US6271731B2 (en) | Control circuit for programmable frequency synthesizer | |
US6661291B2 (en) | Fractional and rapid response frequency synthesizer, and corresponding frequency synthesizing method | |
CN112234981B (en) | Data and clock recovery circuit | |
EP0755120A1 (en) | Phase-locked loop circuit | |
GB2333622A (en) | Single counter dual modulus frequency division apparatus | |
US20020090917A1 (en) | Frequency synthesizer and method of generating frequency-divided signal | |
KR100339687B1 (en) | Multi-band phase locked frequency mixer | |
JPH0993125A (en) | Pll synthesizer circuit | |
EP1514343A1 (en) | An arrangement for low power clock generation | |
US20080079500A1 (en) | Method And System For A Local Oscillator (LO) Generator Architecture For Multi-Band Wireless Systems | |
US6924706B2 (en) | Phase locked loop | |
EP2107681B1 (en) | Prescaler circuit and buffer circuit | |
KR100316845B1 (en) | Apparatus for combining phase locked frequencies with a dual frequency bands | |
KR100423060B1 (en) | Tunable filter circuit using the phase locked loop | |
JPH09289448A (en) | Receiving device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AU JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE FR GB IT LU NL SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1989901925 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1989901925 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1989901925 Country of ref document: EP |