WO1989009410A1 - Test fixture for tab circuits and devices - Google Patents

Test fixture for tab circuits and devices Download PDF

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Publication number
WO1989009410A1
WO1989009410A1 PCT/US1989/001206 US8901206W WO8909410A1 WO 1989009410 A1 WO1989009410 A1 WO 1989009410A1 US 8901206 W US8901206 W US 8901206W WO 8909410 A1 WO8909410 A1 WO 8909410A1
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WO
WIPO (PCT)
Prior art keywords
circuit
test
received
test fixture
circuit board
Prior art date
Application number
PCT/US1989/001206
Other languages
French (fr)
Inventor
Robert J. Flatley
David Hobson
Original Assignee
Digital Equipment Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corporation filed Critical Digital Equipment Corporation
Publication of WO1989009410A1 publication Critical patent/WO1989009410A1/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals

Definitions

  • the present invention relates, in general, to a test fixture for high speed and power TAB
  • TAB circuits or devices are formed by attaching a semiconductor circuit die to a supporting film having a plurality of conductor leads etched thereon.
  • the film contains sprocket holes similar to those found on a reel of 35 mm film.
  • the circuit dies or devices are centrally located on the film, and are mechanically and electrically secured to the etched conductor leads which fan out to bonding pads along the outside edges of the film.
  • the present invention seeks to provide a test fixture which meets these criteria.
  • test fixture for reception of a TAB type circuit which includes special circuit boards for maintaining a 50 ohm transmission line to the TAB inner lead bond connections of the circuit, and a thermoelectric heat pump for controllably varying the operating temperature of the circuit.
  • the test fixture receives a film slide type carrier which holds the TAB type semiconductor circuit to be tested.
  • An anvil is utilized to apply weight on the top side of the TAB film through a window in the slide carrier to insure that a good electrical connection is made between test pads on the TAB film, and a plurality of test pins that project vertically from a test fixture main circuit board disposed beneath the slide carrier.
  • the main circuit board is provided with a conventional microstrip design to supply signals and power to the test pins.
  • a second smaller special circuit board is provided to maintain the 50 ohm signal path from the test pins to the inner lead bond area of the TAB circuit.
  • This circuit board includes holes for reception of the test pins, and has its edges metal plated to provide a constant voltage reference plane for the pins. This reference plane also extends along the top surface of the special circuit board, and runs parallel to the circuit conductors that are etched in the TAB film from the test pads to the die bond connections of the circuit die.
  • a thin dielectric sheet separates the TAB film conductors from the reference plane.
  • thermoelectric heat pump is provided to enable the circuit under test to be subjected to a complete range of temperatures to insure that it operates properly over the entire range.
  • a copper thermal chuck is utilized to provide a thermal path between the heat pump and the circuit under test, and a large heat sink is attached to the pump.
  • FIGs. 1A and IB are diagrammatic top and cross sectional side views, respectively, of a TAB circuit and carrier frame
  • FIG. 2 is a diagrammatic cross sectional front view of the test fixture
  • FIG. 3A is a diagrammatic partial cross sectional side view of a special circuit board that forms a part of the test fixture?
  • FIG. 3B is a diagrammatic top view of the special circuit board. Best Mode for Carrying Out The Invention
  • Circuit 10 includes a circuit die
  • a plurality of conductors 20 are etched on the film 18, and provide electrical paths between a plurality of inner lead bond areas 22 of circuit 10 where the conductors are electrically connected to leads (not shown) of die 14, and a plurality of test pads 24 that are disposed around the periphery of circuit 10.
  • a plurality of sprocket holes 26 are provided in film 18 along two of its edges which are used in the manufacture and handling of circuit 10.
  • Carrier frame 12 is formed from any suitable material, such as plastic, and is designed in any suitable manner to securely hold the edges of film 18.
  • a pair of holes 28 are provided in carrier frame 12 to receive test fixture guide rods that help align circuit 10 with the test fixture.
  • FIG. 2 there is illustrated a test fixture 40 for receiving circuit 10 and carrier frame 12 in a circuit side down manner.
  • Fixture 40 includes a layered base structure 41 having a heat sink 42 as its bottom layer, which can be made of any suitable heat conducting material. If desired, heat sink 42 can be cooled by forced air from a fan (not shown). Disposed on top of heat sink 42 near its outer edges, is a layer 44 of thermal insulation.
  • a thermoelectric heat pump 46 is disposed on top of heat sink 42 in an opening in insulation layer 44.
  • the interface between sink 42 and pump 46 can be coated with a thermal grease to reduce the thermal contact resistance.
  • the thermoelectric heat pump 46 is a known type of device which is comprised of an array 47 of two heavily doped semiconductor junctions connected between a pair of smooth ceramic plates. When a dc voltage is applied to the heat pump, one plate of the pump, depending on the polarity of the voltage, will absorb heat at a rate proportional to the current flowing from the power source. The heat absorbed is transferred to the other plate and must be removed by some means of cooling such as heat sink 42. With these devices, it is possible to obtain differences in temperature of up to 70 degrees Celsius between the two plates. Reversing the direction of the current reverses the heat flow direction.
  • These devices can therefore be used for both heating and cooling an object, and are thus suitable for use with the present invention, which is designed to subject the circuits under test to temperatures ranging from 20 to 90 degrees Celsius. It will be understood that any suitable type of programmable power supply can be used to control heat pump 46 to automatically vary the device temperature over this range.
  • thermoelectric heat pump 46 provides an attractive means by which the temperature of a circuit under test can be variably controlled
  • the relatively low efficiency of this type of heat pump indicates that the size of the pump must be considerably larger than the circuit to be able to cool it down to the low end of the specified temperature range.
  • a copper thermal chuck or heat spreader 48 is disposed on top of heat pump 46 which provides a good thermal path between pump 46 and circuit die 14 when the circuit is in position on the test fixture.
  • Chuck 48 is a three tiered structure that includes a large bottom pedestal 48a, a middle pedestal 48b, and a small top pedestal 48c. Bottom pedestal 48a is attached directly to the top of heat pump 46, while top pedestal 48c is designed to contact circuit die 14 when carrier 12 is in position.
  • thermally conductive material 50 is placed on top pedestal 48c.
  • This material is a thermal conductor when placed under pressure, and consists of a thin metal sheet that is coated on both sides with a silicon rubber.
  • Such a material is manufactured by the Bergquist Company of Minneapolis, MN under the name Q-PAD.
  • main circuit board 52 Disposed on top of insulation layer 44, and bottom pedestal 48a, is a horizontally disposed main circuit board 52, for supplying power and test signals to the circuit under test. To maintain a 50 ohm transmission line to the circuit, conventional microstrip design techniques are employed on the main circuit board 52 by providing on embedded constant voltage reference plane (shown by dashed lines 53).
  • test pins 54 are soldered to main circuit board 52 and extend vertically through the top of the board as shown. These test pins are electrically connected to the microstrip circuitry in board 52 so that they can transmit power and control signals to the test pads 24 of circuit 10 when it is in position on the test fixture.
  • a second special circuit board 56 is horizontally disposed on middle pedestal 48b of thermal chuck 48 and on the inner portions of main circuit board 52 over pins 54. This special board serves to maintain a controlled 50 ohm signal path through test pins 54, and all the way to the inner lead bond areas 22 of circuit 10, and is shown in greater detail in FIGs. 3A and 3B. Specifically, in FIG.
  • FIG. 3A there is shown a partial cross sectional view of board 56, which includes an insulating substrate 58.
  • a conductive layer 60 is disposed on all four edges of substrate 58.
  • Each of the test pins 54 (one shown) passes through a corresponding one of a plurality of holes 62 disposed in substrate 58, as illustrated in FIG. 3B.
  • a ground reference plane is established for each of the test pins 54. In this manner, a controlled impedance path is obtained along test pins 54, since each of the pins is disposed parallel to, and at a fixed distance from, this reference plane.
  • Conductive layer 60 also extends along the top of substrate 58 so that a ground reference plane will also be established for circuit conductors 20 when circuit 10 is disposed in position on top of board 56. Also, a voltage reference plane is established b ⁇ second horizontally disposed conductive layer 64 that is embedded within substrate 58. In this manner, a 50 ohm controlled impedance path can also be established along conductors 20 of circuit 10 between test pads 24, and inner lead bond areas 22. To obtain the desired impedance, a thin dielectric polymer layer 66 is disposed over the top portion of first conductive layer 60 to control the spacing between conductors 20 of circuit 10 and the voltage and ground references planes of special circuit board 56, when the circuit 10 is in position on the same.
  • the thickness of the dielectric layer 66 in that region would have to be correspondingly reduced as well.
  • special circuit board 56 includes a rectangular opening 68 in the center thereof so that the top pedestal 48c of thermal chuck 48 can make contact with circuit die 14. Also, conductive layer 60 is shown as extending to only a small number of the test pin holes 62 which are labeled 62a. These are the holes which are to receive the ground test pins.
  • test pins holes 62b Two of the test pins holes, labeled 62b, are also electrically isolated from conductive layer 60, and are connected below to the second conductive layer 64. These holes receive the power supply test pins, and provide for capacitive decoupling of the power supply connections to the circuit under test.
  • Sheet capacitance is provided both in the special circuit board 56 and the main circuit board 52 in this manner by placing both power signals in circuit board layers that are in close physical proximity to one another.
  • a pair of guide rods 70 extend vertically from thermal chuck 48 through main circuit board 52. These guide rods are positioned to pass through the holes 28 in carrier frame 12 to guide the carrier into position on the test fixture 40. When carrier frame 12 is in position, the face down circuit die 14 will rest on top of thermal chuck 48, and, test pads 24 will contact the tops of test pins 54.
  • Anvil 72 is utilized to apply pressure to these areas of the circuit 10.
  • Anvil 72 includes an outer weight 74, and a center weight 76, both of which are independent of one another so that the pressure applied to the test pads 24 is independent of the pressure applied to circuit die 14.
  • outer weight 74 Disposed in the bottom portion of outer weight 74, are two holes 78 for reception of guide rods 70.
  • a pair of cavities 80 are disposed in the upper portion of outer weight 74 that can be filled with lead beads, or other material, to adjust the weight of the outer weight as necessary to obtain the desired level of pressure on test pads 24. Similar cavities can also be disposed in center weight 76 if desired for adjustment of its weight as well.
  • a pair of silicon rubber strips 82 are disposed on the bottom of outer weight 74, which are positioned to contact Kapton film 18 of circuit 10 directly opposite test pads 24. These rubber strips transmit the weight of outer weight 74 to the test pad/test pin connections, and accommodate any dimensional mismatches in the test pins 54.
  • Anvil center weight 76 includes a narrow elongated bottom portion 84 which passes through a centrally disposed opening 86 in outer weight 74. Disposed on the end of bottom portion 84 is another silicon rubber strip 88, which is generally the same size and shape as that of circuit die 14, and is positioned to contact the encapsulation material directly opposite the die. Again, this strip accommodates dimensional mismatches between die 14 and center weight 76, and transmits pressure from the weight to the die 14 to insure good thermal contact between the die and the sheet 50, and between sheet 50 and thermal chuck 48. From the foregoing, it may be thus seen that test fixture 40 provides good electrical connections to the circuit 10 through the use of test pins 54 and anvil 72.
  • Proper signal integrity is obtained by maintaining a 50 ohm transmission line to the circuit die 14 through the use of main and special circuit boards 52 and 56, and their voltage and ground reference planes. Finally, the temperature of the circuit 10 is controllable over a wide range through the use of thermoelectric heat pump 46, thermal chuck 48, and heat sink 42.

Abstract

A test fixture (40) for TAB (Tape Automated Bonding) circuits includes circuit boards (52 and 56) for maintaining a characteristic impedance to inner lead bond areas of a circuit under test (14). A plurality of vertically disposed test pins (54) are soldered to conductors (53) in one of the circuit boards (52), and provide contacts for supplying power and test signals to test pads (24) on a circuit under test (14). A thermoelectric heat pump (46) is thermally connected to a circuit under test (14) with a copper thermal chuck or heat spreader (48), and is used to subject the circuit (14) to a wide range of operating temperatures. A two piece anvil (72) is provided to apply pressure to the test pad/test pin interface and to the circuit die/thermal chuck interface.

Description

Description Test Fixture For TAB Circuits And Devices Technical Field
The present invention relates, in general, to a test fixture for high speed and power TAB
(Automated Bonding) type semiconductor circuits or devices.
Background Art
TAB circuits or devices are formed by attaching a semiconductor circuit die to a supporting film having a plurality of conductor leads etched thereon. The film contains sprocket holes similar to those found on a reel of 35 mm film. The circuit dies or devices are centrally located on the film, and are mechanically and electrically secured to the etched conductor leads which fan out to bonding pads along the outside edges of the film.
The testing of semiconductor circuits in TAB type form presents a combination of formidable engineering problems. Each of the\circuits tested must be subjected to a wide range of temperatures to insure that they will operate properly over their full specified range. In addition, electrical connections and controlled impedance paths to each of the circuits must be provided so that all of their functions can be properly tested.
Disclosure of the Invention The present invention seeks to provide a test fixture which meets these criteria.
It is therefore the object of the present invention to provide a test fixture for TAB type high power semiconductor circuits or devices which provides adequate electrical connections and controlled impedance signal paths to the circuits under test, and can control the temperature to which the circuits are exposed over a wide range.
This, and other objects of the invention are attained through the provision of a test fixture for reception of a TAB type circuit which includes special circuit boards for maintaining a 50 ohm transmission line to the TAB inner lead bond connections of the circuit, and a thermoelectric heat pump for controllably varying the operating temperature of the circuit.
The test fixture receives a film slide type carrier which holds the TAB type semiconductor circuit to be tested. An anvil is utilized to apply weight on the top side of the TAB film through a window in the slide carrier to insure that a good electrical connection is made between test pads on the TAB film, and a plurality of test pins that project vertically from a test fixture main circuit board disposed beneath the slide carrier.
To maintain a 50 ohm transmission line to the circuit under test, the main circuit board is provided with a conventional microstrip design to supply signals and power to the test pins. A second smaller special circuit board is provided to maintain the 50 ohm signal path from the test pins to the inner lead bond area of the TAB circuit. This circuit board includes holes for reception of the test pins, and has its edges metal plated to provide a constant voltage reference plane for the pins. This reference plane also extends along the top surface of the special circuit board, and runs parallel to the circuit conductors that are etched in the TAB film from the test pads to the die bond connections of the circuit die. A thin dielectric sheet separates the TAB film conductors from the reference plane. Both of these reference planes serve to maintain the desired 50 ohm impedance all the way to the TAB inner lead bond connections of the circuit under test. The thermoelectric heat pump is provided to enable the circuit under test to be subjected to a complete range of temperatures to insure that it operates properly over the entire range. A copper thermal chuck is utilized to provide a thermal path between the heat pump and the circuit under test, and a large heat sink is attached to the pump. Through the use of a programmable power supply for the heat pump, the circuit under test can automatically be subjected to a full range of operating temperatures.
Brief Description of Drawings
The foregoing, and additional objects, features, and advantages of the present invention will become apparent from a consideration of the following detailed description of the preferred embodiment thereof, taken in conjunction with the accompanying drawings in which:
FIGs. 1A and IB, are diagrammatic top and cross sectional side views, respectively, of a TAB circuit and carrier frame;
FIG. 2 is a diagrammatic cross sectional front view of the test fixture;
FIG. 3A is a diagrammatic partial cross sectional side view of a special circuit board that forms a part of the test fixture? and,
FIG. 3B is a diagrammatic top view of the special circuit board. Best Mode for Carrying Out The Invention
Turning now to a more detailed consideration of the present invention, there is illustrated in FIGs. 1A and IB, a Tape Automated Bonding (TAB) type integrated circuit 10, and a carrier frame 12 for the same. Circuit 10 includes a circuit die
14 that is surrounded by a body of encapsulation material 16, and is mounted on a Kapton film 18.
A plurality of conductors 20 are etched on the film 18, and provide electrical paths between a plurality of inner lead bond areas 22 of circuit 10 where the conductors are electrically connected to leads (not shown) of die 14, and a plurality of test pads 24 that are disposed around the periphery of circuit 10. A plurality of sprocket holes 26 are provided in film 18 along two of its edges which are used in the manufacture and handling of circuit 10.
Carrier frame 12 is formed from any suitable material, such as plastic, and is designed in any suitable manner to securely hold the edges of film 18. A pair of holes 28 are provided in carrier frame 12 to receive test fixture guide rods that help align circuit 10 with the test fixture. Turning now to FIG. 2, there is illustrated a test fixture 40 for receiving circuit 10 and carrier frame 12 in a circuit side down manner. Fixture 40 includes a layered base structure 41 having a heat sink 42 as its bottom layer, which can be made of any suitable heat conducting material. If desired, heat sink 42 can be cooled by forced air from a fan (not shown). Disposed on top of heat sink 42 near its outer edges, is a layer 44 of thermal insulation. A thermoelectric heat pump 46 is disposed on top of heat sink 42 in an opening in insulation layer 44. The interface between sink 42 and pump 46 can be coated with a thermal grease to reduce the thermal contact resistance. The thermoelectric heat pump 46 is a known type of device which is comprised of an array 47 of two heavily doped semiconductor junctions connected between a pair of smooth ceramic plates. When a dc voltage is applied to the heat pump, one plate of the pump, depending on the polarity of the voltage, will absorb heat at a rate proportional to the current flowing from the power source. The heat absorbed is transferred to the other plate and must be removed by some means of cooling such as heat sink 42. With these devices, it is possible to obtain differences in temperature of up to 70 degrees Celsius between the two plates. Reversing the direction of the current reverses the heat flow direction. These devices can therefore be used for both heating and cooling an object, and are thus suitable for use with the present invention, which is designed to subject the circuits under test to temperatures ranging from 20 to 90 degrees Celsius. It will be understood that any suitable type of programmable power supply can be used to control heat pump 46 to automatically vary the device temperature over this range.
Although thermoelectric heat pump 46 provides an attractive means by which the temperature of a circuit under test can be variably controlled, the relatively low efficiency of this type of heat pump indicates that the size of the pump must be considerably larger than the circuit to be able to cool it down to the low end of the specified temperature range. To solve this problem, a copper thermal chuck or heat spreader 48 is disposed on top of heat pump 46 which provides a good thermal path between pump 46 and circuit die 14 when the circuit is in position on the test fixture. Chuck 48 is a three tiered structure that includes a large bottom pedestal 48a, a middle pedestal 48b, and a small top pedestal 48c. Bottom pedestal 48a is attached directly to the top of heat pump 46, while top pedestal 48c is designed to contact circuit die 14 when carrier 12 is in position.
To provide a cushion, and to correct for any dimensional mismatches, between circuit die 14 and chuck 48, a thin sheet of thermally conductive material 50 is placed on top pedestal 48c. This material is a thermal conductor when placed under pressure, and consists of a thin metal sheet that is coated on both sides with a silicon rubber.
Such a material is manufactured by the Bergquist Company of Minneapolis, MN under the name Q-PAD.
Disposed on top of insulation layer 44, and bottom pedestal 48a, is a horizontally disposed main circuit board 52, for supplying power and test signals to the circuit under test. To maintain a 50 ohm transmission line to the circuit, conventional microstrip design techniques are employed on the main circuit board 52 by providing on embedded constant voltage reference plane (shown by dashed lines 53).
A plurality of test pins 54 are soldered to main circuit board 52 and extend vertically through the top of the board as shown. These test pins are electrically connected to the microstrip circuitry in board 52 so that they can transmit power and control signals to the test pads 24 of circuit 10 when it is in position on the test fixture. A second special circuit board 56 is horizontally disposed on middle pedestal 48b of thermal chuck 48 and on the inner portions of main circuit board 52 over pins 54. This special board serves to maintain a controlled 50 ohm signal path through test pins 54, and all the way to the inner lead bond areas 22 of circuit 10, and is shown in greater detail in FIGs. 3A and 3B. Specifically, in FIG. 3A, there is shown a partial cross sectional view of board 56, which includes an insulating substrate 58. A conductive layer 60 is disposed on all four edges of substrate 58. Each of the test pins 54 (one shown) passes through a corresponding one of a plurality of holes 62 disposed in substrate 58, as illustrated in FIG. 3B. By placing conductive layer 60 along each edge of substrate 58, a ground reference plane is established for each of the test pins 54. In this manner, a controlled impedance path is obtained along test pins 54, since each of the pins is disposed parallel to, and at a fixed distance from, this reference plane.
Conductive layer 60 also extends along the top of substrate 58 so that a ground reference plane will also be established for circuit conductors 20 when circuit 10 is disposed in position on top of board 56. Also, a voltage reference plane is established bγ second horizontally disposed conductive layer 64 that is embedded within substrate 58. In this manner, a 50 ohm controlled impedance path can also be established along conductors 20 of circuit 10 between test pads 24, and inner lead bond areas 22. To obtain the desired impedance, a thin dielectric polymer layer 66 is disposed over the top portion of first conductive layer 60 to control the spacing between conductors 20 of circuit 10 and the voltage and ground references planes of special circuit board 56, when the circuit 10 is in position on the same. If it is desired to maintain the 50 ohm impedance all the way past the inner lead bond areas 22 to the circuit die 14 where the width of conductors 20 reduces as illustrated in FIG. 1A, the thickness of the dielectric layer 66 in that region would have to be correspondingly reduced as well.
As shown in the top view illustrated in FIG. 3B, special circuit board 56 includes a rectangular opening 68 in the center thereof so that the top pedestal 48c of thermal chuck 48 can make contact with circuit die 14. Also, conductive layer 60 is shown as extending to only a small number of the test pin holes 62 which are labeled 62a. These are the holes which are to receive the ground test pins.
Two of the test pins holes, labeled 62b, are also electrically isolated from conductive layer 60, and are connected below to the second conductive layer 64. These holes receive the power supply test pins, and provide for capacitive decoupling of the power supply connections to the circuit under test. Sheet capacitance is provided both in the special circuit board 56 and the main circuit board 52 in this manner by placing both power signals in circuit board layers that are in close physical proximity to one another.
Returning now to FIG. 2, a pair of guide rods 70 extend vertically from thermal chuck 48 through main circuit board 52. These guide rods are positioned to pass through the holes 28 in carrier frame 12 to guide the carrier into position on the test fixture 40. When carrier frame 12 is in position, the face down circuit die 14 will rest on top of thermal chuck 48, and, test pads 24 will contact the tops of test pins 54.
To insure that circuit die 14 is held with sufficient pressure against the pressure responsive thermally conductive sheet 50, and that test pads 24 make good electrical contact with test pins 54, a two piece anvil 72 is utilized to apply pressure to these areas of the circuit 10. Anvil 72 includes an outer weight 74, and a center weight 76, both of which are independent of one another so that the pressure applied to the test pads 24 is independent of the pressure applied to circuit die 14.
Disposed in the bottom portion of outer weight 74, are two holes 78 for reception of guide rods 70. A pair of cavities 80 are disposed in the upper portion of outer weight 74 that can be filled with lead beads, or other material, to adjust the weight of the outer weight as necessary to obtain the desired level of pressure on test pads 24. Similar cavities can also be disposed in center weight 76 if desired for adjustment of its weight as well.
A pair of silicon rubber strips 82 are disposed on the bottom of outer weight 74, which are positioned to contact Kapton film 18 of circuit 10 directly opposite test pads 24. These rubber strips transmit the weight of outer weight 74 to the test pad/test pin connections, and accommodate any dimensional mismatches in the test pins 54.
Anvil center weight 76 includes a narrow elongated bottom portion 84 which passes through a centrally disposed opening 86 in outer weight 74. Disposed on the end of bottom portion 84 is another silicon rubber strip 88, which is generally the same size and shape as that of circuit die 14, and is positioned to contact the encapsulation material directly opposite the die. Again, this strip accommodates dimensional mismatches between die 14 and center weight 76, and transmits pressure from the weight to the die 14 to insure good thermal contact between the die and the sheet 50, and between sheet 50 and thermal chuck 48. From the foregoing, it may be thus seen that test fixture 40 provides good electrical connections to the circuit 10 through the use of test pins 54 and anvil 72. Proper signal integrity is obtained by maintaining a 50 ohm transmission line to the circuit die 14 through the use of main and special circuit boards 52 and 56, and their voltage and ground reference planes. Finally, the temperature of the circuit 10 is controllable over a wide range through the use of thermoelectric heat pump 46, thermal chuck 48, and heat sink 42.
Although the invention has been illustrated in terms of a preferred embodiment, it will be understood that numerous variations and modifications can be made by those of skill in the art without departing from the true spirit and scope thereof as set forth in the following claims.

Claims

Claims
1. A test fixture for semiconductor circuits comprising: means to receive a circuit to be tested; transmission line means having a controlled impedance to supply power and control signals to a received circuit; means to electrically contact said transmission line means to circuit leads of a received circuit and, means to vary the temperature to which a received circuit is exposed.
2. The circuit test fixture of claim 1, wherein said transmission line means comprises: a first circuit board having a characteristic impedance established by a plurality of conductive paths disposed therein; a plurality of vertically extending test pins soldered to said first circuit board and electrically connected to said plurality of conductive paths, and, a second circuit board disposed on said first circuit board which includes:
(a) a plurality of vertically extending holes for reception of said test pins;
(b) a conductive layer plated on a plurality of edges of said circuit board to establish a reference plane for said test pins, and extending along a top surface of said second circuit board; and,
(c) a dielectric layer disposed on said top surface so that when a received circuit having horizontally disposed conductors is placed on top of said second circuit board, said conductive layer extending along said top surface will establish a reference plane for the horizontally disposed conductors of a received circuit so that the characteristic impedance of the conductors can be controlled.
3. The circuit test fixture of claim 2, wherein said means to electrically contact said conductor means to a plurality of circuit leads of a received circuit comprises said test pins, and means to hold the circuit leads of a received circuit in contact with said test pins.
4. The circuit test fixture of claim 3, wherein said means to hold comprises a weight for placement on top of a received circuit when it is in position on said second circuit board and said test pins.
5. The circuit test fixture of claim 1, wherein said means to vary the temperature of a received circuit comprises: a heat pump; and, thermally conductive means attached to said heat pump having means to contact a received circuit.
6. The circuit test fixture of claim 5, further including heat sink means attached to said heat pump.
7. The circuit test fixture of claim 5, wherein said heat pump is a thermoelectric heat pump comprised of an array of semiconductor junctions.
8. The circuit test fixture of claim 5, wherein a thermally conductive sheet of material is disposed between a received circuit and said means to contact on said thermally conductive means.
9. The circuit test fixture of claim 5, wherein said thermally conductive means is a thermal chuck having a bottom portion for contacting said heat pump, and a top portion for contacting a received circuit.
10. The circuit text fixture of claim 9, wherein said thermal chuck is made of copper.
11. A test fixture for TAB type semiconductor circuits comprising: means to receive a TAB circuit for testing; means to electrically contact a plurality of test pads on a received TAB circuit for supplying power and test signals to a received circuit; transmission line means to supply power and test signals to a received circuit, said transmission line means including means to maintain a controlled impedance to the inner lead bond areas of a received TAB circuit; and, means to vary the temperature to which a received TAB circuit is exposed.
12. The test fixture of claim 11, wherein said means to receive a TAB circuit comprises a base structure including two spaced vertically extending guide rods for passing through corresponding holes in, and thereby aligning with said base structure, a carrier frame for a TAB circuit.
13. The test fixture of claim 11, wherein said means to electrically contact comprises a plurality of test pins positioned to contact the test pads of a received TAB circuit, and weight means to hold the test pads of a received TAB circuit in secure engagement with said test pins.
14. The test fixture of claim 13, wherein said transmission line means comprises: a first horizontally disposed circuit board having embedded conductors disposed therein for supplying power and signals to a received circuit, said embedded conductors establishing a characteristic impedance for said first circuit board, and said test pins being soldered to said first circuit board, electrically connected to said embedded conductors, and extending vertically from said first circuit board; and, a second horizontally disposed circuit board placed generally on top of said first circuit board, and having a substrate with a plurality of holes for reception of said test pins, said second circuit board including: a) a first conductive layer disposed on a plurality of edges thereof and including a top portion extending along a top surface thereof, said first conductive layer establishing a reference plane for said test pins to maintain a characteristic impedance therefore; b) a dielectric layer disposed over the top portion of said first conductive layer to space a received TAB circuit from said conductive layer when it is positioned on said second circuit board, and thereby establish a characteristic impedance for conductor leads of a received circuit; and, c) a second conductive layer that is horizontally embedded in said substrate to establish another reference plane for a received TAB circuit, said second conductive layer being electrically connected to at least one of said test pins when said second circuit board is in position on said first circuit board.
15. The test fixture of claim 11, wherein said means to vary the temperature to which a received TAB circuit is exposed comprises: a heat pump for supplying heat to, and drawing heat away from, a received circuit; and, a thermal chuck having a top portion for contacting an encapsulated circuit die body of a received TAB circuit, and a bottom portion for contacting said heat pump.
16. The test fixture of claim 15, further including heat sink means attached to said heat pump.
17. The test fixture of claim 15, wherein said heat pump is a thermoelectric heat pump comprised of a plurality of semiconductor junctions.
18. The test fixture of claim 15, further including weight means to apply pressure between an encapsulated circuit die body of a received TAB circuit, and said thermal chuck.
19. The test fixture of claim 15, wherein said thermal chuck has a multiple tiered configuration, and said top portion includes a small top pedestal, and said bottom portion includes a large bottom pedestal.
20. The test fixture of claim 19, wherein said thermal chuck is made of copper.
\
PCT/US1989/001206 1988-03-29 1989-03-28 Test fixture for tab circuits and devices WO1989009410A1 (en)

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US07/174,697 US4839587A (en) 1988-03-29 1988-03-29 Test fixture for tab circuits and devices
US174,697 1988-03-29

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Publication number Priority date Publication date Assignee Title
US4512821A (en) * 1982-12-20 1985-04-23 Procedyne Corp. Method for metal treatment using a fluidized bed
BE1000697A6 (en) * 1987-10-28 1989-03-14 Irish Transformers Ltd Device for testing integrated electrical circuits.
MY103847A (en) * 1988-03-15 1993-09-30 Yamaichi Electric Mfg Laminated board for testing electronic components
US5036380A (en) * 1988-03-28 1991-07-30 Digital Equipment Corp. Burn-in pads for tab interconnects
US5189363A (en) * 1990-09-14 1993-02-23 Ibm Corporation Integrated circuit testing system having a cantilevered contact lead probe pattern mounted on a flexible tape for interconnecting an integrated circuit to a tester
US5124639A (en) * 1990-11-20 1992-06-23 Motorola, Inc. Probe card apparatus having a heating element and process for using the same
US5196785A (en) * 1990-12-12 1993-03-23 Hewlett-Packard Company Tape automated bonding test apparatus for thermal, mechanical and electrical coupling
US5122736A (en) * 1990-12-17 1992-06-16 Intelmatec Corporation Apparatus for and method of pressing pins of an IC for testing
US5124644A (en) * 1990-12-19 1992-06-23 Vlsi Technology, Inc. System for positioning a semiconductor chip package with respect to a testing device
US5086269A (en) * 1991-03-08 1992-02-04 Hewlett-Packard Company Burn-in process and apparatus
GB2257849B (en) * 1991-06-28 1995-11-22 Digital Equipment Int Semiconductor chip test jig
JPH06510122A (en) * 1991-08-23 1994-11-10 エヌチップ インコーポレイテッド Burn-in techniques for unpackaged integrated circuits
US5541524A (en) * 1991-08-23 1996-07-30 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5227717A (en) * 1991-12-03 1993-07-13 Sym-Tek Systems, Inc. Contact assembly for automatic test handler
US5331273A (en) * 1992-04-10 1994-07-19 The United States Of America As Represented By The Secretary Of The Navy Thermal fixture for testing an integrated circuit
US5345170A (en) * 1992-06-11 1994-09-06 Cascade Microtech, Inc. Wafer probe station having integrated guarding, Kelvin connection and shielding systems
US5440231A (en) * 1993-04-19 1995-08-08 Motorola, Inc. Method and apparatus for coupling a semiconductor device with a tester
US5451866A (en) * 1994-08-26 1995-09-19 The United States Of America As Represented By The Secretary Of The Army Quick-mount measuring device for evaluating the electrical characteristics of ferroelectric materials
JPH08254567A (en) * 1995-03-16 1996-10-01 Advantest Corp Lead press part mechanism of handler for ic tester
JPH1038966A (en) * 1996-07-29 1998-02-13 Ando Electric Co Ltd Ic-measuring mechanism
US5914613A (en) 1996-08-08 1999-06-22 Cascade Microtech, Inc. Membrane probing system with local contact scrub
US6392431B1 (en) * 1996-10-23 2002-05-21 Aetrium, Inc. Flexibly suspended heat exchange head for a DUT
GB2346703B (en) * 1997-10-07 2002-06-19 Reliability Inc Burn-in board with adaptable heat sink device
IL135485A0 (en) * 1997-10-07 2001-05-20 Reliability Inc Burn-in board capable of high power dissipation
US6049217A (en) * 1997-12-30 2000-04-11 Intel Corporation Thermally enhanced test contactor
US6072322A (en) * 1997-12-30 2000-06-06 Intel Corporation Thermally enhanced test socket
US6256882B1 (en) 1998-07-14 2001-07-10 Cascade Microtech, Inc. Membrane probing system
US6279832B1 (en) 1999-03-31 2001-08-28 Melexis Nv Temperature control system
US6215323B1 (en) 1999-05-28 2001-04-10 Melexis N.V. Method and apparatus for temperature-controlled testing of integrated circuits
US6445202B1 (en) 1999-06-30 2002-09-03 Cascade Microtech, Inc. Probe station thermal chuck with shielding for capacitive current
DE10001117A1 (en) * 2000-01-13 2001-07-26 Infineon Technologies Ag Test device for a semiconductor device
JP3659132B2 (en) * 2000-06-16 2005-06-15 株式会社村田製作所 Load control type actuator
US6965226B2 (en) 2000-09-05 2005-11-15 Cascade Microtech, Inc. Chuck for holding a device under test
US6914423B2 (en) 2000-09-05 2005-07-05 Cascade Microtech, Inc. Probe station
DE20114544U1 (en) 2000-12-04 2002-02-21 Cascade Microtech Inc wafer probe
US6636062B2 (en) * 2001-04-10 2003-10-21 Delta Design, Inc. Temperature control device for an electronic component
US6628132B2 (en) * 2001-08-10 2003-09-30 Teradyne, Inc. Methods and apparatus for testing a semiconductor structure using improved temperature desoak techniques
WO2003052435A1 (en) 2001-08-21 2003-06-26 Cascade Microtech, Inc. Membrane probing system
US7057404B2 (en) 2003-05-23 2006-06-06 Sharp Laboratories Of America, Inc. Shielded probe for testing a device under test
US7492172B2 (en) 2003-05-23 2009-02-17 Cascade Microtech, Inc. Chuck for holding a device under test
KR100541730B1 (en) * 2003-06-26 2006-01-10 삼성전자주식회사 Inspecting apparatus for semiconductor device
US7250626B2 (en) 2003-10-22 2007-07-31 Cascade Microtech, Inc. Probe testing structure
JP2007517231A (en) 2003-12-24 2007-06-28 カスケード マイクロテック インコーポレイテッド Active wafer probe
US7187188B2 (en) 2003-12-24 2007-03-06 Cascade Microtech, Inc. Chuck with integrated wafer support
US6982566B1 (en) * 2004-04-01 2006-01-03 Altera Corporation Method and apparatus for operating a burn-in board to achieve lower equilibrium temperature and to minimize thermal runaway
DE202005021435U1 (en) 2004-09-13 2008-02-28 Cascade Microtech, Inc., Beaverton Double-sided test setups
WO2006076315A1 (en) * 2005-01-14 2006-07-20 Delta Design, Inc. Heat sink pedestal with interface medium chamber
US7656172B2 (en) 2005-01-31 2010-02-02 Cascade Microtech, Inc. System for testing semiconductors
US7535247B2 (en) 2005-01-31 2009-05-19 Cascade Microtech, Inc. Interface for testing semiconductors
US7372285B1 (en) * 2005-05-25 2008-05-13 National Semiconductor Corporation Socket-less test board and clamp for electrical testing of integrated circuits
US7764072B2 (en) 2006-06-12 2010-07-27 Cascade Microtech, Inc. Differential signal probing system
US7723999B2 (en) 2006-06-12 2010-05-25 Cascade Microtech, Inc. Calibration structures for differential signal probing
US7403028B2 (en) 2006-06-12 2008-07-22 Cascade Microtech, Inc. Test structure and probe for differential signals
JP2008128838A (en) * 2006-11-21 2008-06-05 Shinko Electric Ind Co Ltd Probe device
KR101344348B1 (en) * 2007-01-22 2013-12-24 삼성전자주식회사 Test socket of semiconductor device and test method using the same
US7876114B2 (en) 2007-08-08 2011-01-25 Cascade Microtech, Inc. Differential waveguide probe
US7888957B2 (en) 2008-10-06 2011-02-15 Cascade Microtech, Inc. Probing apparatus with impedance optimized interface
US8410806B2 (en) 2008-11-21 2013-04-02 Cascade Microtech, Inc. Replaceable coupon for a probing apparatus
US8319503B2 (en) 2008-11-24 2012-11-27 Cascade Microtech, Inc. Test apparatus for measuring a characteristic of a device under test
US20110035540A1 (en) * 2009-08-10 2011-02-10 Adtron, Inc. Flash blade system architecture and method
US8935466B2 (en) 2011-03-28 2015-01-13 SMART Storage Systems, Inc. Data storage system with non-volatile memory and method of operation thereof
US9098399B2 (en) 2011-08-31 2015-08-04 SMART Storage Systems, Inc. Electronic system with storage management mechanism and method of operation thereof
US9021319B2 (en) 2011-09-02 2015-04-28 SMART Storage Systems, Inc. Non-volatile memory management system with load leveling and method of operation thereof
US9063844B2 (en) 2011-09-02 2015-06-23 SMART Storage Systems, Inc. Non-volatile memory management system with time measure mechanism and method of operation thereof
US9239781B2 (en) 2012-02-07 2016-01-19 SMART Storage Systems, Inc. Storage control system with erase block mechanism and method of operation thereof
US8949689B2 (en) 2012-06-11 2015-02-03 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9671962B2 (en) 2012-11-30 2017-06-06 Sandisk Technologies Llc Storage control system with data management mechanism of parity and method of operation thereof
US9123445B2 (en) 2013-01-22 2015-09-01 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9214965B2 (en) 2013-02-20 2015-12-15 Sandisk Enterprise Ip Llc Method and system for improving data integrity in non-volatile storage
US9329928B2 (en) 2013-02-20 2016-05-03 Sandisk Enterprise IP LLC. Bandwidth optimization in a non-volatile memory system
US9183137B2 (en) 2013-02-27 2015-11-10 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9470720B2 (en) 2013-03-08 2016-10-18 Sandisk Technologies Llc Test system with localized heating and method of manufacture thereof
US9043780B2 (en) 2013-03-27 2015-05-26 SMART Storage Systems, Inc. Electronic system with system modification control mechanism and method of operation thereof
US10049037B2 (en) 2013-04-05 2018-08-14 Sandisk Enterprise Ip Llc Data management in a storage system
US9170941B2 (en) 2013-04-05 2015-10-27 Sandisk Enterprises IP LLC Data hardening in a storage system
US9543025B2 (en) 2013-04-11 2017-01-10 Sandisk Technologies Llc Storage control system with power-off time estimation mechanism and method of operation thereof
US10546648B2 (en) 2013-04-12 2020-01-28 Sandisk Technologies Llc Storage control system with data management mechanism and method of operation thereof
US10013033B2 (en) 2013-06-19 2018-07-03 Sandisk Technologies Llc Electronic assembly with thermal channel and method of manufacture thereof
US9898056B2 (en) 2013-06-19 2018-02-20 Sandisk Technologies Llc Electronic assembly with thermal channel and method of manufacture thereof
US9313874B2 (en) 2013-06-19 2016-04-12 SMART Storage Systems, Inc. Electronic system with heat extraction and method of manufacture thereof
US9367353B1 (en) 2013-06-25 2016-06-14 Sandisk Technologies Inc. Storage control system with power throttling mechanism and method of operation thereof
US9244519B1 (en) 2013-06-25 2016-01-26 Smart Storage Systems. Inc. Storage system with data transfer rate adjustment for power throttling
US9146850B2 (en) 2013-08-01 2015-09-29 SMART Storage Systems, Inc. Data storage system with dynamic read threshold mechanism and method of operation thereof
US9431113B2 (en) 2013-08-07 2016-08-30 Sandisk Technologies Llc Data storage system with dynamic erase block grouping mechanism and method of operation thereof
US9361222B2 (en) 2013-08-07 2016-06-07 SMART Storage Systems, Inc. Electronic system with storage drive life estimation mechanism and method of operation thereof
US9158349B2 (en) 2013-10-04 2015-10-13 Sandisk Enterprise Ip Llc System and method for heat dissipation
US9152555B2 (en) 2013-11-15 2015-10-06 Sandisk Enterprise IP LLC. Data management with modular erase in a data storage system
US9549457B2 (en) 2014-02-12 2017-01-17 Sandisk Technologies Llc System and method for redirecting airflow across an electronic assembly
US9497889B2 (en) 2014-02-27 2016-11-15 Sandisk Technologies Llc Heat dissipation for substrate assemblies
US9348377B2 (en) 2014-03-14 2016-05-24 Sandisk Enterprise Ip Llc Thermal isolation techniques
US9519319B2 (en) 2014-03-14 2016-12-13 Sandisk Technologies Llc Self-supporting thermal tube structure for electronic assemblies
US9485851B2 (en) 2014-03-14 2016-11-01 Sandisk Technologies Llc Thermal tube assembly structures
TWI709521B (en) * 2019-12-12 2020-11-11 鴻勁精密股份有限公司 Attaching mechanism of conveying device and testing equipment for its application
TWI709520B (en) * 2019-12-12 2020-11-11 鴻勁精密股份有限公司 Attaching mechanism of conveying device and testing equipment for its application

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003591A1 (en) * 1984-12-10 1986-06-19 Aseco Corporation Contact set for test apparatus for testing integrated circuit package

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643201A (en) * 1970-02-09 1972-02-15 Amp Inc Impedance matching microstrip connector
US3710251A (en) * 1971-04-07 1973-01-09 Collins Radio Co Microelectric heat exchanger pedestal
US3979671A (en) * 1975-03-06 1976-09-07 International Business Machines Corporation Test fixture for use in a high speed electronic semiconductor chip test system
DE3263256D1 (en) * 1981-07-08 1985-05-30 Fujitsu Ltd Device for testing semiconductor devices at a high temperature
US4402185A (en) * 1982-01-07 1983-09-06 Ncr Corporation Thermoelectric (peltier effect) hot/cold socket for packaged I.C. microprobing
US4616178A (en) * 1982-05-27 1986-10-07 Harris Corporation Pulsed linear integrated circuit tester
FR2541779B1 (en) * 1983-02-24 1985-06-07 Commissariat Energie Atomique DEVICE FOR CONTROLLING MOBILE ELECTRICAL LOADS IN AN INTEGRATED CIRCUIT IN MOS TECHNOLOGY
US4560962A (en) * 1983-08-30 1985-12-24 Burroughs Corporation Multilayered printed circuit board with controlled 100 ohm impedance
US4727720A (en) * 1986-04-21 1988-03-01 Wernicki Paul F Combination ice mold and ice extractor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003591A1 (en) * 1984-12-10 1986-06-19 Aseco Corporation Contact set for test apparatus for testing integrated circuit package

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US4839587A (en) 1989-06-13
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JPH02500222A (en) 1990-01-25

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