WO1989009439A1

WO1989009439A1 - Four phase shifter

Info

Publication number: WO1989009439A1
Application number: PCT/US1989/001312
Authority: WO
Inventors: Hubert Bruce Butts, Jr.; David Merril Robinson
Original assignee: Digital Equipment Corporation
Priority date: 1988-04-01
Filing date: 1989-03-30
Publication date: 1989-10-05
Also published as: JPH02500312A

Abstract

The disclosure is directed to a serial in, serial out data shifter. Generally, the data shifter comprises a latch based design (L1-L4) with a four phase clock system (CLK1-CLK4). The latches (L1-L4) are coupled in series and the four phases of the clock (CLK1-CLK4) are coupled to the clock ports of the latches in a predetermined order whereby only four latches are needed to shift and temporarily store three bits of data.

Description

FOUR PHASE SHIFTER

Field of the Invention

The invention is directed to computer technology and, more particularly, to a serial in, serial out data shif er.

Background of the Invention

In many modern computer systems, a fast buffer is required as a temporary storage space for data while certain components of the system meant to receive the temporarily stored data are busy. Typically, the buffer is arranged in a gate array between the memory system and central processing unit of the computer system. When a large amount of data must be temporarily stored in such a buffer, the buffer mechanism occupies a large amount of cells in the gate array causing space constraint problems within the gate array. A serial in, serial out shifter is an advantageous mechanism to temporarily store large amounts of data while minimizing the number of cells in the gate array required for the buffer. There are several known configurations for a serial in, serial out shifter. One known shifter comprises several master-slave flip flops arranged in series wherein data is shifted one bit position on the transition of each shift pulse. Data normally resides in the slave flip flop of each master-slave arrangement. On the rising or positive edge of each shift pulse, data is transferred from each slave flip flop to the master flip flop of the next in series master-slave flip flop arrangement. On the falling or negative edge of each shift pulse, the master flip flop of each master-slave flip flop arrangement sends its data to its slave. Accordingly, each shift pulse shifts all the data then residing in the series of master-slave flip flops one bit position.

A latch based design for the above described master- slave flip flop serial in, serial out shifter can be implemented with a two phase clock system. In such an implementation, several latches are arranged in series with adjacent latches of the series being opened or loaded on a different phase of the two phase clock or, in other words, A latches and B latches. The two phase clock system provides non-overlapped pulses, one for each phase, during each cycle.

Accordingly, during each clock cycle, one bit is loaded into the first A latch during the A clock pulse and transferred to the next in series B latch during the B clock pulse of the clock cycle. Once the shifter is full, each clock cycle will shift one bit in and one bit out. This arrangement requires two latches per bit to be shifted.

Summary of the Invention

It is a primary objective of the present invention to provide a latch based design, serial in, serial out shifter which increases the bit per latch ratio to reduce the number of latches required for the temporary storage of a given amount of bits of data. Generally, the invention comprises a clock system having n clock phases per cycle with n > 2, and wherein the clock ports of each group of n series arranged latches are coupled to the clock phases in the order 1, n, n-1 ... n-(n-2). The n phases of each clock cycle are transmitted as non-overlapped pulses in the order.1, 2 ... n per cycle. The above-described latch based design increases the total number of bits which can be shifted by a given number n of latches.

For example, in one embodiment of the invention, a four phase clock system is coupled to four series arranged latches with clock pulse 1 coupled to the clock port of the first latch, clock pulse 4 coupled to the clock port of the second latch, clock pulse 3 coupled to the clock port of the third latch and, finally, clock pulse 2 coupled to the clock port of the fourth latch.

During the first cycle of operation of the shifter, a first bit of data is loaded into the first latch and transferred to the second latch. During the second cycle, a second bit of data is loaded into the first latch, the first bit is transferred from the second latch to the third latch and the second bit of data is • transferred from the first latch to the second latch. Further, during the third cycle of operation, a third bit of data is loaded into the first latch, the first bit of data is transferred from the third latch to the fourth latch, the second bit of data is transferred from the second latch to the third latch and the third bit of data is transferred from the first latch to the second latch. Subsequent cycles of operation cause a continuing shifting of bits from the input to the first latch to the output of the fourth latch. Significantly, three bits of data are stored in the shifter for each four latches. Accordingly, pursuant to the invention, thirty two words of thirty two bits each, for example, would require only 1366 latches in the shifter whereas the prior art two phase clock system would require 2,048 latches. This represents a significant percentage decrease in the number of latches which must be placed in the gate array thereby significantly alleviating space constraint problems within the gate array.

For a better understanding of the above and other features and advantages of the invention, reference should be made to the following detailed description and to the accompanying drawings.

Brief Description of the Drawings

Fig. 1 is a block diagram of a shifter in accordance with the present invention.

Fig. 2 is a timing diagram illustrating the four phase clock utilized in the shifter of Fig. 1.

Detailed Description

Referring now to the drawings, and initially to Fig. 1, four latches Ll L2, L3, L4 are arranged in series with a data input line Din coupled to the input port of the first la.ch LI and a data output line Dout coupled to the output port of the fourth latch L4. A line 10 couples the output port of the first latch LI to the input port of the second latch L2. A line 20 couples the output port of the second latch L2 to the input port of the third latch L3 and, finally, a line 30 couples the output port of the third latch L3 to the input port of the fourth latch L4. In this manner, the four latches L1-L4 are coupled to one another in a configuration which permits the continuous shifting of bits of data from the input line Din serially through each of the four latches L1-L4 to the output line Dout with the four latches L1-L4 providing a temporary storage space for a certain number of bits during the shifting operation of the latches L1-L4. As discussed above, it is a primary objective of the present invention to maximize the number of bits which are stored by the latches L1-L4 during the shifting operation.

Accordingly, pursuant to the invention, a four phase clock system is provided for a synchronized operation of the four latches L1-L4 such that three bits are temporarily stored by the four latches L1-L4 during operation of the serial in, serial out shifter formed by the latches. More specifically, as illustrated in Fig. 2, the four phase clock system provides four non- overlapped pulses per cycle with the sequence of pulses identified as CLK1, CLK2, CLK3, CLK4. Although the embodiment is described with respect to non-overlapped clock pulses, the latch arrangement according to the invention is operable with overlapped clock pulses if the overlap is small enough such that the data in each latch is stable for the set up time of the next series latch. Set up time is defined as the time data must be stable at the input of a latch.

Referring once again to Fig. 1, the four phases CLK1, CLK2, CLK3, CLK4 are coupled to the clock ports of the latches L1-L4 in the order CLK1 to the clock port of latch LI, CLK4 to the clock port of latch L2, CLK3 to the clock port of latch L3 and CLK2 to the clock port of latch L4.

In the operation of the serial in, serial out shifter of latches L1-L4, during each clock cycle, each latch is opened only during the pulse CLK1-CLK4 of the four phase clock which is connected to its clock port. When a latch is opened, data at its input will change its state and thereby change the signal present at its output port. When a latch is closed, the signal present at its input port does not change the state of the latch and the output of the latch remains constant in accordance with the state of the latch caused by the signal present at its input port during the clock, phase which last opened the latch.

During cycle one, the latch LI is open during the pulse CLK1 and a first bit of data present at Din changes the state of latch LI such that the first bit of data is present on line 10, which couples the output port of the latch LI to the input port of the latch L2. The first bit of data is transferred to latch L2 via line 10 when the pulse CLK4 opens latch L2 causing the first bit of data to be present on line 20, which couples the output port of the latch L2 to the input port of the latch L3.

During cycle two, a second bit of data is placed on the line Din to change the state of the latch LI during phase CLK1 of cycle two. The first bit of data in the latch L2 is transferred to the latch L3 via line 20 during clock phase CLK3 of cycle two and the second bit of data in the latch LI is transferred to the latch L2 during the clock phase CLK4 of cycle two through line 10.

During cycle three, a third bit of data is placed on line Din and changes the state of the latch LI during clock pulse CLK1 of cycle three. The first bit of data in the latch L3 is transferred to the latch L4 during clock phase CLK2 and appears on the output line Dout two clock cycles after first being placed on the line Din. Thus, the data was temporarily stored for two cycles before being output to further components of the computer system.

Moreover, also during cycle three, the second bit of data is transferred from the latch L2 to the latch L3 during clock phase CLK3 and the third bit of data is transferred from the latch LI to the latch L3 during clock phase CLK4. The serial feeding of data through the serial in, serial out shifter of the latches L1-L4 continues for ongoing cycles with three bits of data being stored in the four latches.

The total number of latches in series may be any multiple of four latches with the sequence of clocks repeating over and over in the CLK1, CLK4, CLK3, CLK2 sequence. In addition, it should be noted that the invention is not limited to a four phase clock system, but may include any number of phases, n, with n>2, and the sequence of phases inputted to the clock ports of n-sized groups of series arranged latches in the repeating clock phase sequence of 1, n, n-1, ...n-(n-2) . What is significant is that the serial in, serial out shifter of the invention increases the total amount of data that may be temporarily stored by the n latches of the shifter.

■ Generally, it may be stated that the number of latches required to store a given number of bits is represented by the equation: number of latches = (-_-γ) * (number of bits to be stored) where n = number of clock phases and n> 2.

Claims

What Is Claimed Is;

1. A serial in, serial out data shifter, which comprises:

a multiple phase clock system having regularly repeating clock cycles with each cycle including n clock pulses, wherein n>2;

a plurality of at least n series coupled state devices, each of said state devices having an input port, an output port and a clock port;

a data input line coupled to the input port of a first-in-series state device of the plurality of series coupled state devices;

a data output line coupled to the output port of an nth last-in-series state device of the plurality of series coupled state devices;

the output port of each remaining state device of the plurality of series coupled state devices being coupled to the input port of a next-in-series state device of the plurality of series coupled state devices;

the n clock pulses of the multiple phase clock system being coupled to the clock ports of the n series coupled state devices in the sequence: clock pulse 1 to the clock port of the first-in-series state device, clock pulse n to the clock port of a second-in-series state device of the series coupled state devices, clock pulse n-1 to a third-in-series state device of the series coupled state devices and continuing in decremental clock pulse order and incremental state device order to clock pulse n- (n-2) to the nth last-in-series state device.

2. The serial in, serial out data shifter of claim 1 wherein the n clock pulses are n non-overlapped clock pulses.

3. The serial in, serial out data shifter of claim 1 wherein each of the state devices comprises a latch.

4. The serial in, serial out data shifter of claim 3 wherein n=4.

5. The serial in, serial out data shifter of claim 1 wherein the plurality of at least n series coupled state devices comprises a predetermined multiple of n series coupled state devices and the sequence of clock pulse couplings to the state devices repeating for every group of n series coupled state devices.