WO1990000331A1

WO1990000331A1 - Statistical measurement equipment and communication system using same

Info

Publication number: WO1990000331A1
Application number: PCT/EP1988/000594
Authority: WO
Inventors: Peter Frans Adelaïde JOOS
Original assignee: Alcatel N.V.; Bell Telephone Manufacturing Company, Naamloze Vennootschap
Priority date: 1988-06-30
Filing date: 1988-06-30
Publication date: 1990-01-11
Also published as: BE1002050A3; IT1230948B; IT8921030A0; AU3661789A

Abstract

Statistical measurement equipment used in a communication system wherein individual cell streams with variable cell rates are multiplexed on a same link. The equipment includes a common circuit (CCC) with a first counter (CR1/8) counting a first number (A.B) of first cells of the multiplexed cell stream, and individual circuits (MMC, VMC, PMC) checking the mean, variance and peak of the probability distribution function of the variable cell rate. For instance, the MMC includes a second counter (MC) which counts the second cells of an individual cell stream and is reset by the first counter when the latter has counted the first number, the ratio of a second number of these cells and the first number constituting an expected value of the mean. As a consequence when the second number is counted this is indicative of the fact that the expected value of the mean is exceeded.

Description

STATISTICAL MEASUREMENT EQUIPMENT AND COMMUNICATION SYSTEM USING SAME

The present invention relates to a statistical measurement equipment for checking the relation between the measured and expected values ^of a parameter which is function of a first set of elements and of a second set of elements included in said first set.

Such a statistical measurement equipment is already the subject of the French patent application NO 8707556 filed on May 26, 1987.

Therein the parameter checked is the mean of the variable cell or packet rate of an individual cell stream which is part of a plurality of individual cell streams multiplexed on a same link of a communication system, the cells of these multiplexed and individual streams constituting the above mentioned first and second sets of elements respectively. The purpose of the checking operation is to check if the source of the individual cell stream operates within the traffic limits on the basis of which its multiplexing on the link was allowed. In this equipment the expected value of the mean is equal to 1/MN wherein M is an integer and N is the total number of individual cell streams on all the links.

Use is made of a counter which starting from an initial value A.M. where A is also an integer, is incremented by 1 at a predetermined frequency, i.e. for each set of N cells, and decremented by M each time a cell of the individual cell stream is received. Because the initial value from which the counter starts counting is a multiple of M the number - equal to 1 - of cells of an individual cell stream expected per number of N.M cells may be exceeded a number of times, a cell being only discarded when the contents of the counter become zero. In the preferred embodiment described M=3 and A=5.

A drawback of this known measurement equipment is that the choice of the mean is limited because its maximum value is equal to 1/N and both M and N are integers.

A statistical measurement equipment similar to the one just described is the subject of the French patent application No 8707555 also filed on May 26, 1987. Therein, M is equal to 1. A statistical measurement equipment of the above described type and used in a communication system of the same type as the one described in the above mentioned French patent applications, is the subject of the Belgian patent application no 08701481 filed on December 23, 1987. Therein the measurement equipment calculates the instantaneous value of the mean and the variance of each individual cell stream at the receipt of each cell of this individual cell stream, on the basis of the number of cells of the individual cell stream and of the number of cells of the multiplexed cell stream, received until then and starting with the first cell. The thus measured values of the'mean and variance are then compared with the respective expected values thereof and depending on the result of this comparison the received cell is either allowed for further processing or discarded. Because a considerable number of cells has to be received before a relatively accurate mean or variance can be calculated the last mentioned decision has to be postponed at the beginning of a cell stream unti a sufficient number of cells has been received. An object of the present invention is to provide a statistical measurement equipment of the above type, but which does not present the above mentioned drawbacks.

According to the invention this ob ect is achieved due to the fact that said equipment includes means for checking if a predetermined second number which is function of elements of said second set has been counted before a predetermined first number of elements of said first set has been counted, the ratio of said second and first predetermined numbers being function of said expected value of the parameter.

Another characteristic feature of the present statistical measurement equipment is that said second number is constituted by elements of said second set and said ratio is equal to said expected value of the parameter .

Hence, if the second number of elements has not been counted before the first number of elements has been the measured parameter value which is equal to the ratio of the counted number of elements and the first number is smaller than the expected parameter value. In the opposite case the expected parameter value is exceeded. The present measurement equipment thus allows an easy verification of the above relation between the measured and expected values of a parameter and no special measure have to be taken at the beginning of a mesurement. Indeed-, in the beginning as well as afterwards the checking means operates in a same way.

Another characteristic feature of the present statistical measurement equipment is that said first and second numbers are adjustable.

Because both the denominator and numerator of the parameter value are thus adjustable a large number and range of parameter values can be measured. Moreover, because a number of cells corresponds to a certain time interval this adjustment allows the measurement to be carried out over an adjustable time interval corresponding to the first number. Thus the measurement time interval may be chosen in function of the type of parameter to be checked. As will be explained it may also be selected in function of the time character of the individual cell stream.

Still another characteristic feature of the present statistical measurement equipment is that said parameter checking means includes first counting means for counting elements of said first set, second counting means for counting said second number, first detection means associated to said first counting means for detecting when the latter has counted said first number and for then providing a reset signal for said second counting means, and second detection means associated to said second counting means for detecting when the latter has counted said second number and for providing an output signal indicative of said relation.

Because the second counter is reset after the first one has counted the first number of elements the second counter only counts the second number if this number is larger than the first one, e.g. when the measured value is larger than the expected value of the parameter. Hence, when the second counter reaches the position corresponding to the second number this is indicative of a predetermined relation between the measured and expected parameter values. More particularly it may is thus be indicated that expected value of the parameter has been exceeded.

Still another characteristic feature of the present statistical measurement equipment is that it includes at least one of three of said parameter checking means for checking a respective one of the mean, the variance and a peak of a same probability distribution function.

In this way the mean, variance and peak may all be measured using in each case similar checking means. Yet another characteristic feature of the present statistical measurement equipment is that the value of said first number used by said peak checking means is considerably smaller than the value of said first number used by said mean checking means.

In this way the peak is measured over a time interval which is much smaller than that over which the mean is measured. Thus, one may take measures after a short time interval when the peak is exceeded and only after a long time interval if the mean is exceeded. A still further characteristic of the present statistical measuring equipment is that said probability distribution function is that of a variable cell rate of an individual cell stream which is part of a plurality of individual cell streams multiplexed on a same communication link of a communication system on the basis of at least one of said parameters, said first set being constituted by the cells of said multiplexed cell stream and said second set being constituted by the cells of said individual cell stream.

Thus it may be easily checked if the source of each individual cell stream operates within the traffic parameter limits on the basis of which its multiplexing on the link was allowed. The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein : Fig. 1 is schematical diagram of a statistical measurement equipment SME and of part of a communication system in which it is included both according to the invention, '

Fig. 2 shows part of the memory MEM of Fig. 1 in more detail; Figs. 3 to 5 respectively represent in detail a common control circuit CCC, a mean measurement circuit MMC, and a peak measurement circuit PMC together with a variance measurement circuit VMC all forming part of the statistical measurement equipment SME of Fig. 1

Referring to Fig. 1 the ATM (Asynchronous Transfer Mode) data packet or data cell communication system shown therein includes a digital switching network DSN which is for instance of the type disclosed in the Belgian patent No 905 982 CDe Prycker et al 2-2). This digital switching network DSN has a plurality of inputs II to IN and outputs 01 to ON which are coupled to user stations Cnot shown) via input and output multiplex links and statistical measurement equipments . For instance, a user station is connected to the input II of DSN via an input multiplex link ML and a statistical measurement equipment SME having an input I and an output II.

The statistical measurement equipment SME comprises a receive port RX and a transmit port TX which are connected in cascade between the input I and the output II. The receive port RX includes a receive buffer RBUF, a processor PR, a memory MEM, a statistical measurement circuit SMC and a clock extraction circuit CEC, whilst the transmit port TX includes a transmit buffer TBUF. The receive and transmit buffers RBUF and TBUF are connected in cascade between the input I and output II. The processor PR has access to these buffers as well as to the statistical measurement circuit SMC and the memory MEM via connections which although represented by a single wire are in fact constituted by a plurality of these. The clock extraction circuit CEC is connected to the input I and has a bit clock output BCL and a cell clock output CL which are both connected to the measurement circuit SMC. The latter is itself connected to PR via the leads DCA, PA, TC. The user station (not shown) connected to the input multiplexer link ML is able to multiplex thereon a plurality of streams of data cells or packets. The cells of a same data stream belong to a same communication and are identified by a same label. Each time this user station wants to transmit such a data stream towards a destination user station via the input link ML, the statistical measurement equipment SME and the digital switching network DSN in cascade, it starts a virtual path setup operation by transmitting towards the DSN a path setup control cell containing a distinct label, e.g. LI, and the values of various other parameters defining the data cell stream to be subsequently transmitted on the path to be established and if the path setup operation is successful. These parameters are for instance the mean m and variance v of the probability distribution function of the variable bitrate of this data stream and a peak value p thereof, as well as a parameter s defining the type of service provided by the user station. More particularly the parameter s indicates the time character of the individual cell stream, i.e. the order of magnitude of the fluctuations of the cell rate around the mean cell rate. For instance s = 1 millisecond, 10 milliseconds, etc.

When for the data cell stream the bitrate on the lin ML is for instance equal to 600 Megabits/sec the expected values of m, p and v are e.g. :

120

(1)

600

280

(2)

600

40

— exp2 C3)

600

When such a path setup control cell is received in the measurement equipment SME it is stored in the receive buffer RBUF thereof and processed by the processor PR. When the latter finds out that a path setup control cell is concerned it allocates a portion of the memory MEM to the communication with label LI and determines from the expected values of the traffic parameters m, p and v and from the service parameter s the following other parameters CS (counter select) : a 3-bit counter selection parameter to select the one of eight counters CR1 to CR8 (to be considered later) which is best suited for counting the data cells of the communication with label LI which will possibly be transmitted on the link ML subsequent to the transmission of the control cell i.e. the counter which is able to count both the mean and the peak of the individual cell stream. These counters are able to count distinct unit time intervals UTI having a duration of A = 2 exp (8 + 2a) data cells, with a = 0 to a = 7 respectively. By means of CS the processor PR thus in fact selects a value of A and a, e.g. CS = 000 corresponding to a = 0 and A = 256.

When the highest bitrate is 600 Megabits/sec the counters CR1 to CR8 are preferably respectively selected for the following ranges : CR1 : from 600 to 120 Megabits/sec CR2 : from 120 to 30 ^π " i.e. from 0.8 to 0.2 times 600/2 exp 2

CR7 : from 117 to 29 kilobits/sec i.e. from 0.8 to 0.2 times 600/2 exp 12 CR8 : below 29 kilobits/sec.

CLA (class) : a 2-bit class selection parameter to select, for the counter selected by means of CS, one of measurement time intervals. These time intervals have a duration of B = 2 exp (14 + 3b) unit time intervals counted by that counter, with b = 0 to b = 3. By mean of CLA the processor PR thus in fact selects a value of b e.g. CLA = 01 corresponding to b = 1. To be noted that this choice is based on the value of the above mentioned service parameter s. an 8-bit parameter which is such that the expected value of the mean m is M

(4)

2 exp (8 + 2a) an 8-bit parameter which is such that

P = P2 - M and (5) that the expected value of the peak p is P2

(6)

2 exp (8 + 2a) a 16-bit parameter which is such that the expected value of the variance v is V

(7)

2 exp 16

With the above given expected values of m, p and v and because a=0 one obtains : M = 52 (8)

P2 = 120 (9)

P = 68 (10)

V = 292 (11)

Subsequent to the storage operation of the above values of the parameters in the memory MEM the processor PR controls the transmission of the path setup control cell to the transmit buffer TBUF of the transmit port TX which afterwards transfers the control cell to the digital switching network DSN. In a manner similar to the one described in the Belgian patent No 08701481, in each stage of this network an output link is selected and it is calculated if the control cell - and the data cells of the same communication following it - may be multiplexed on this output link. This calculation makes use of the mean and variance parameters and v contained in the control cell. Assuming that a virtual path may thus be set up to the destination user station, the latter transmits a confirmation cell to the originating user station which may then start the transmission of the corresponding data cell stream with label LI on the multiplex link ML. For this data stream the statistical measurement equipment SME checks if it operates within the traffic limits defined by the parameters which were stored in the memory MEM in the way described above. Before describing this operation reference is made to Figs. 3 to 5 which show the statistical measurement circuit SMC of the SME in more detail. This circuit SMC includes -a common control circuit CCC (Fig. 3), a mean measuring circuit MMC (Fig. 4), a peak measuring circuit PMC (Fig. 5) and a variance measuring circuit VMC (Fig. 5). CCC has inputs connected to the outputs CL and BCL of the clock extraction circuit CEC, to the outputs PA and DCA of the processor PR and to the outputs MS, PS and VS of MMC, PMC and VMC respectively. It also has outputs ST1, ST2 and TC connected to MMC, PMC and PR respectively.

The common control CCC circuit CCC includes a timing circuit TC, an address counter AC, an address register AR, divider circuits DIV1 to DIV8, a set of 8 unit time interval counters CR1 to CR8 each with two associated comparators and an associated demultiplexer and of which only counter CR1 and the associated comparators C01 and C02 and demultiplexer DEMUX1 are shown, a counter LI, registers CLA, CS and ST, toggle flipflop TFF , demultiplexers DEMUX2 and DEMUX3 and AND-gates Gl to G5 and OR gate OR. The mean measuring circuit MMC shown in Fig. 4 includes a cell counter Ml, a mean counter MC comprising subcounters MC(l) and MC(2), register M, comparators C03 and C04 and AND-gates G6 and G7.

The peak measuring circuit PMC represented in Fig. 5 includes a cell counter PI, a register P, a comparator C05 and AND-gate G8.

Finally, the variance measuring circuit VMC also shown in Fig. 5 includes registers V, VI and MVR, subtractor circuit SUB, variance counter VC comprising subcounters VC(1) and VC(2), demultiplexer DEMUX5, comparator C06, summing circuit SUM, a table TSQ and AND-gates G9 to G14.

All the above circuits included in the statistical measurement circuit SMC are interconnected as shown and are controlled in a way which will become clear from the following description of the operation of SMC following the receipt of a data cell with label LI in the buffer circuit RBUF of the receive port RX. When the processor PR detects the presence of such a data cell in this buffer RBUF it transmits a "data cell available" control signal DCA and a partial memory address PA which is function of the label LI contained in the data cell, to the measurement circuit SMC. More particularly, DCA is applied to the timing circuit TC and to the address counter AC which are thus both reset, whilst PA is applied to the address register AR.

Meanwhile the clock extraction circuit CEC extracts a bit clock BCL and a cell clock CL from the incoming data cell stream and applies both BCL and CL to the timing circuit TC which in reponse thereat provides at its outputs TO to T15 a set of 16 successive non-overlapping timing pulses TO to T15 (not shown) which cover a period equal to the duration of the received data cell and which are used to control various circuits of the SMC.

With a bitrate of the incoming cell stream equal to 600 Megabits/sec and with cells having a length of 280 bits, BCL and CL are respectively equal to 600 Megabits/sec and 2.14 Megacells/sec . In this case each cell has a duration of 466.67 nanoseconds and TO to T15 each have a duration of l/16th of this value. The cell clock signal CL is also applied to the divider circuit DIVl which is connected in cascade with the divider circuits DIV2 to DIV8. The divider circuit DIVl realises a division by 256 or 2 exp 8 so that the resulting clock signal CL1 increments the unit time interval counter CR1 by 1 each time a unit time interval equal to the duration of 2 exp 8 cells has been counted. Because the divider circuits DIV2 to DIV8 each realise a division by 4 or 2 exp 2, so that the clock signals CL2 to CL8 have a frequency equal -to l/4th of CL1 to CL7 respectively, the associated counters (not shown) are incremented by 1 each time an interval corresponding to 2 exp (8 + 2), 2 exp (8 + 4), ..., 2 exp (8 + 14) data cells has been counted respectively. In other words, the 8 counters CR1 to CR8 are incremented by 1 each time a unit time interval equal to A = 2 exp (8 + 2a) data cells with a = 0, ...» 7 has been counted respectively.

The pulse DCA and the timing pulses Tl to T15 together step the address counter AC two times through its successive positions 0 to 7 and the latter then applies the corresponding 3-bit partial addresses 000 to 111 to the address register AR wherein they are combined with the partial address PA to form two times in succession the successive memory addresses PA, PA + 1,..., PA + 7 of the 8 lines of the memory portion shown in Fig. 2, allocated to the label LI.^'

As already described above this memory portion stores the parameters CS, CLA, M, V and P, which were loaded therein after the receipt of the path setup control cell with label LI and containing the parameters m, v, p and s. It also stores the following parameters which are updated upon the receipt of the data cells, as will become clear later: LI : a 3-bit counter value indicating the unit time interval counted by CRl/8 during which the last data cell having label LI was received; TFF : a comparison bit which is alternately brought in the condition 0 and 1 when a measurement time interval has elapsed; ST : a status bit which is normally equal to 1 and is brought in the condition 0 when the data cell which is being processed has not to be transmitted to the transmit port TX; MC(1) and MC(2) : the contents of two parts of a counter

MC used to count the number of times the mean value M is reached during a" measurement time interval;

VC(1) and VC(2) : the contents of two parts of a counter VC used to count the number of time the variance value V is reached during the measurement time interval; Ml : the contents of a cell counter Ml used in the MMC; PI : the contents of a cell counter PI used in the PMC; VI : the contents of a register VI used in the VMC.

To facilitate the understanding of the measurement circuit SMC the effect of the timing pulses TO to T15 on the CCC, the MMC, the PMC and the VMC are considered separately.

The common control circuit CCC (Fig. 3) Timing pulse TO

The parameters LI, CS, CLA, TFF and ST are loaded in the like named circuits of CCC:

CS : because this parameter is equal to 000 - as was previously assumed - only the output of the comparator C01 associated to the unit time interval counter CR1 is connected to the output UTI (Unit Time Interval) of the demultiplexer DEMUX2. Also only the output of the comparator C02 associated to the counter CR1 (via DEMUX1) is connected to the output MTI (Measurement Time Interval) of the demultiplexer DEMUX3; CLA : because this parameter is equal to 01 - as was previously assumed - so that the selection leads clal and cla2 are on 0 and 1 respectively, only the output of the stage 17 of the counter CRI is connected to the associated comparator C02. This means that the counter CRl is used to count all the data cells LI in steps or unit time intervals each having a duration of

A = 2 exp (8+0) data cells, and during a measurement time interval having a duration of B = 2 exp 17 such unit time intervals.

In other words, each measurement time interval has a duration of A.B = 2 exp (8+0+14+3) data cells. Because of the selection of counter CRl and of the stage 17 thereof the other counters CR2/8 and the other stages of CRl are no longer considered hereinafter. It should be noted that because the counter CRl is never reset the stage 17 is alternately brought in the 0 to 1 condition for a duration of 2 exp 17 unit time intervals. Obviously the same is true for the other counters CR2/8 and the other stages 14, 20, 23. the 3-bit value LI identifying the last unit time interval during which a data cell with label LI was received. This value is compared with the value stored in the stages 0, 1 and 2 of the counters CRl to CR8 and constituting the identity of the respective unit time interval during which the data cell which is being processed is received. If both the values compared by C01 are equal the output thereof is on 0 and the same is true for the output

UTI of DEMUX2. In this case the parameter LI indicates the identity of the present unit time interval. On the contrary, when both the compared values are different the output UTI is on 1 indicating that the unit time interval has elapsed and that the value LI has to be updated. TFF : this bit is compared with the bits stored in the stages 17 of the counters CRl to CR8. If both the values compared by C02 are equal, indicating that the measurement time interval has not yet elapsed, the output thereof is on 0 and the same is true for the output MTI of DEMUX3. On the contrary, when both the compared values are different the output MTI is on 1 indicating that the measurement time interval has elapsed and that accordingly the bit

TFF has to be changed. It should be noted that it is necessary to reverse the bit TFF after each measurement time interval because the bit 17 also reverses after each such interval as the counter CRl is not reset.

ST : the condition 1 or 0 of this status bit indicates that the previous cell with label LI was allowed to be transmitted further or discarded respectively. Timing pulse T4 By this pulse the AND-gate Gl is enabled so that its output signal MTIl either remains on 0 indicating that the end of the measurement time interval has not yet been reached or becomes 1 indicating that this end has been attained. In the latter case the condition of the bit TFF is reversed so that also the output of the comparator C02 and the output MTI of the demultiplexer DEMUX2 then become 0. TFF thus remains in the condition wherein it has just been brought. When activated (1) the output signal MTIl also resets the counters MC and VC of MMC and VMC respectively.

Timing pulse T6

The AND-gate G2 is enabled so that the condition of the status bit ST appears at the output STl and is applied to the increment input STl of the counter Ml of MMC which will be considered later. Timing pulse T7

The AND-gate G3 is enabled so that its output UTI1 either remains on 0 indicating that the value LI is correct or becomes 1 indicating that it is incorrect. In the latter case the counter storing the value LI is incremented by 1 and the counter PI of PMC is reset.

It is clear that when no data cells with label LI were received during a number of successive unit time intervals the value of LI may still be incorrect after a first increment. But since it will be incremented at the receipt of each data cell with label LI it will finally be brought in a condition wherein it indicates the correct unit time interval.

It should be noted that only the, last three bits of CRl are used to define the identity of the unit time interval because it is assumed that at least during one of the eight unit time intervals a data cell with label LI will be received.

In this connection it should be noted that in principle it would be possible to extend the use of CLA to the case B = 1 so that an output signal UTI1 would be given for every unit time interval counted by the counter CRl.

However one would then each time have to reset the count value PI in memory and this is a very time consuming operation. This is avoided by the use of LI.

Timing pulse T8

The AND-gate G4 is enabled so that the condition of the status bit ST appears at the output ST2 and is applied to the increment input ST2 of the counter PI of PMC which will be considered later.

Timing pulse T9

The AND-gate G5 is enabled so that the condition of the bit ST is also generated at the output TC and applied to the processor PR. Timing pulse T10 The parameters LI, CS, CLA, TFF and ST are loaded in the memory portion allocated to label LI.

The mean measurement circuit MMC (Fig. 4) Timing pulse TO Because CLA has been loaded in the like named register of CCC and is equal to 01 the output leads clal in cla2 of this register are on 0 and 1 respectively. As a consequence the demultiplexer DEMUX4 only applies the condition of the bit stored in the stage 17 of the counter MCC2) to the input of the comparator C0 .

By means of the CLA it is obviously possible to operate the DEMUX4 in such a way that it connects the output of one of other the stages 14, 20 and 23 to the comparator C04. Timing pulses Tl and T2

The counter values MC(1) and MC(2) are loaded in the like named counters MC(1) and MC(2) which together constitute the mean counter MC of MMC. Timing pulse T4 As described above in relation to the common control circuit CCC the output signal MTIl of the gate Gl thereof is on 1 or 0 if the measurement time interval has elapsed or not respectively. In the former case the counter MC is reset . Timing pulse T5

The previous counter value Ml, i.e. the number of cells with label LI counted until now, is loaded in the like named counter Ml. Timing pulse T6 The mean value M, i.e. 52, is loaded in the like named register M.

The output signal STl provided by CCC is applied to the increment input of the counter Ml. Assuming that this output signal STl is activated, i.e. when the status bit ST in on 1, the value stored in the counter Ml is incremented by 1, thus counting the data cell with label LI which is being processed.

The thus updated value of Ml is compared with the mean value M to check if a number of data cells equal to this mean value has been counted or not. In the negative the output of C03 is on 0, whereas in the positive it is o Timing pulse T7

The AND-gate G6 is enabled so that the output signal 0/1 of the comparator G6 is applied to the reset input R o the counter M as well as to the increment-by-1 output of the mean counter MC. This means that when Ml has counted number of cells equal to the mean value M—-i-t—is reset and the mean value M is counted^ny MC. If this counter MC was reset by MTIl during T4 it is thus brought in the position Timing pulse T9

The AND-gate G7 is enabled so that the output MS of this gate is on 0 or 1 depending on the values compared by the comparator C04 being different or equal respectively. This means that the output MS is only activated (1) when the bit of stage 17 of the counter MC is on 1, i.e. when this counter has counted a number M of data cells a number of times at least equal to B = 2 exp 17 before the measuring time interval equal to the duration of B = 2 exp 17 unit time intervals A counted by CRl has elapsed. Because each of these unit time intervals has a duration equal to that of A = 2 exp 8 data cells it is thus checked if a number of cells with label LI equal to M.B has been counted or not before a total number of data cells equal t A.B has been counted or that M.B is larger or smaller than A.B. In other words it is checked if at the end of a measurement time interval corresponding to A.B cells the expected value M/A is exceeded or not.

If the output MS remains de-activated (0) indicating that the expected mean value is not exceeded when the measurement time interval A.B has elapsed the de-activated condition of the output of the OR-gate OR (Fig. 3) is not affected. If also the outputs PS and VS of the PMC and the VMC remain de-activated the status bit ST remains on 1. By the timing pulse T9 the output of the gate G5 of CCC (Fig. 3) then becomes activated to inform the processor PR that the data cell being processed may be transmitted to the transmit port TX.

On the contrary, if the output MS of the AND-gate G7 is activated (1) indicating that the mean is exceeded at the end of the measuring time interval A.B the condition of the status bit ST (Fig. 3) is changed from 1 to 0 through the OR-gate OR. In this case the output TC of the gate G5 of CCC is de-activated thus informing the processor PR that the data cell being processed should be discarded. Time intervals Til, T12 and T15

The contents of MC(l) and MC(2) and Ml are loaded in the memory MEM.

From the above it follows that the parameter CS allows the selection of one of the counters CRl/8, i.e. the selection of one of the 8 values of A = 2 exp (B + 2a), whilst the parameter CLA permits the selection of one of the 4 values of B, i.e.

2 exp 14, 2 exp 17, 2 exp 20 or 2 exp 23 of the selected counter. By the selection of A various values of the mean may be established and by the selection of A and B various mesurement time intervals A.B may be realized . Indeed, for instance :

- if CRl is selected the expected value of the mean is equal to M/A with A = 2 exp 8. Hereby M is selectable between 0 and 255 and it is measured over a measuring time interval equal to A.B with A.B = 2 exp (14+3b) wherein b = 0, 1, 2 or 3;

- if CR2 is selected the expected value of the mean m is equal to M/A with A = 2 exp (8+2). M is again selectable between 0 and 255 and again measured over a measuring time interval equal to A.B but longer than in the previous case; - in general, the expected value of the mean m established by CRl/8 is equal to M/A with A = 2 exp (B+2a) and it is measured over a measuring time interval equal to A.B with B = 2 exp (14+3b) wherein b = 0, 1, 2, 3. Hence, the expected value of the mean may be adjusted over a large range, and cells are only discarded when the mean is exceeded over a relatively long and selectable measurement time interval. In other words the mean may be exceeded during unit time intervals which are considerably shorter than the measuring time interval. However, this is only allowed on condition that the peak is not exceeded during such a unit time interval. This is detected by the peak measuring circuit PMC which will now be considered and it is done in order not to disturb the traffic on the link ML by such peaks. The peak measurement circuit PMC (Fig. 5) Timing pulse T5 The counter value PI is loaded from the memory MEM in the like named 8-bit counter PI. As will become clear from the following this counter value is equal to the number of data cells P3 received within a unit time interval less the value M because the counter starts counting from minus M. To this end the first stage of the counter is a sign bit stage and the counter counts from -127 to +128. Timing pulse T6

The peak value P, with P=P2-M wherein P2 is the expected value of the peak P is loaded in the like named register P (see the above relations (5) and (6) ] Timing pulse T7

As described above in relation to the common control circuit CCC, when the value LI has to be updated, indicating that the data cell is received in a new unit time interval, the output of gate G3 is activated (1) due to which the counter PI is reset to its initial value equal to minus M. Timing pulse T8

As also described above, when the status bit ST is on 1 - as is assumed - the output ST2 of the gate G4 is activated. As a consequence the counter value PI is incremented by 1. This means that if the data cell received is the first one of a new time interval the PI is brought in the position -M+l. Timing pulse T9

The AND-gate G8 is enabled so that the result of the comparison of PI and P appears at the output PS of G8. This output PS remains de-activated (0) if before the unit time interval has elapsed, i.e. before PI is reset, the value PI (equal to the number of data cells P3 less M) is smaller than the value P (equal to the expected peak less M). On the contrary when PI is larger than P meaning that the expected value of the peak has been exceeded during the unit time interval UTI, the output PS is activated (1). In the latter case the status bit ST (Fig. 3) is brought in the condition 0 via the OR gate OR so that also the output TC of the gate G5 is then de-activated. As a consequence the processor PR is informed of the fact that the data cell which is being processed should be discarded.

Timing pulse T15

The counter value PI is stored in the memory MEM. The variance measurement circuit VMC (Fig. 5) Timing pulse TO Because the selection signal value CLA has been loaded in the like named register of CCC and is equal to 01 the input leads clal and cla2 of this register are on 0 and 1 respectively. As a consequence the demultiplexer DEMUX5 only applies the output of the AND-gate G10 to the input of the comparator C06. The inputs of these gates are connected to the output of the stage 17 of the counter VC as well as to the output b of the stage 15 of the counter MC of the MMC.

By means of the CLA it is obviously possible to operate the DEMUX5 in such a way that it connects the output of one of the other gates G2, Gil and G12 to the comparator C06. As shown, the inputs of these gates are connected to the outputs 14, 20 and 23 of the counter VC and to the outputs a, c and d of the stages 12, 18 and 21 of the counter MC.

Timing pulses Tl and T3

The counter values VC(1) and VC(2) are loaded in the corresponding counters MC(1) and MC(2) Timing pulse T4 The counter value MV is loaded in the registers MV and MVR. Timing pulse T6

The above mentioned value P1=P3-M which is present in the counter PI is used as an address for the squaring table TSQ which stores the squares of various values of PI. By the timing pulse T6 the square of PI is applied to the summing circuit SUM to be added to the previous value VI stored in MVR. However, the summing operation is only enabled at the end of the unit time interval UTI1 and upon the occurrence of timing pulse T7. To be noted that since the counter PI counts from minus M and cannot count more than 255 (from -127 to +128) the value PI stored therein is equal to the deviation from M during a time interval equal to 255 cells. When squared it is therefore a mesure of the variance according to the relation (7). Timing pulse T7

The expected variance value is loaded in the like named register V.

When the unit time interval LI is a new one, i.e. when the output UITl of the gate G3 (Fig. 3) is activated, the operation of the summing circuit SUM is enabled and the thus calculated new variance value VI is loaded in the register VI under the control of the signal UITl and substituted for the value stored therein. On the contrary, when the unit time interval is not a new one the summing circuit SUM remains non-active. Timing pulse T8

The substractor SUB is enabled and therefore subtracts the expected value V of the variance from the calculated variance value VI and stores the difference value V-Vl.

The AND-gate G13 is enabled so that if the result of the subtraction is positive the output of this gate becomes activated (1) as a consequence of which this result is loaded in the register VI as a new value VI. In this case also the variance counter VC is incremented by 1. On the contrary, when the result of the subtraction is not positive the value VI is not affected and also the counter VC is not incremented. One thus subtracts V from VI as long as this gives a positive result and counts the number of times V is subtracted. When Vl-V would become negative the value VI is maintained and then used later to be added to the newly calculated value of the variance. Timing pulse T9 The AND-gate G14 is enabled so that the output of the gate G10 is compared with the value 1. Thus it is checked if both the counters VC and MC have counted the value 2 exp 17 and 2 exp 15 respectively. Only in this case the output VS of the gate G14 becomes activated, as a consequence of which the status bit ST (Fig. 3) is reset so that the data cell being processed will then be discarded.

Without the connection of the gates G9 to G12 to the mean counter MC the operation of the counter VC, DEMUX5, C06, G14 is similar to that of the counter MC, DEMUX4, C04, G7. This means that it is checked if during a measurement time interval A.B equal to 2exp (8+17) data cells the variance value V has been exceeded B = 2 exp 17 times or not.

In the positive the data cell being processed would then be discarded. However it may happen that the variance is exceeded but that the value of the mean is considerably lower than the expected one. Because this is not a dangerous situation the decision to discard a data cell is therefore made dependent on the value of the mean at that moment and the cell is only discarded when this value exceeds a dangerous level. This is the reason why the gates G9 to G12 have inputs controlled by the respective stages 12, 15, 18 and 21 of the mean counter MC. As a consequence in the present case a data cell will only be discarded when simultaneously VC has counted 2 exp 17 and MC has reached the value 2 exp 15.

From the above it follows that the present statistical measuring equipment includes a mean checking means CCC, MMC, a variance checking means CCC, VMC, and a peak checking means CCC, PMC which include a common circuit CCC and three individual circuits MMC, VMC and PMC. The common circuit CCC includes a first counting means CRl/8 to which a first detection means DEMVX1/3, C01/2, LI, TFF, CLA, CS as associated. Each of the circuits MMC VMC and PMC also includes a respective second counting means Ml, M, C03, MC; VI, V, SUB, VC and PI to which a respective second detection means DEMUX4, C04; DEMUUX5, C06; and C05 is associated. The circuits MMC and VMC are relatively similar in that the second counting means thereof includes a respective third counting means Ml, M, C03 and VI, V, SUB and a respective fourth counting means MC VC. On the contrary the circuit PMC does not include such a fourth counting means.

From the above it also follows tht in the mean measuring circuit MMC as well as in the peak measuring circuit PMC it is checked if a predetermined second number M.B or P of cells of an individual cell stream has been counter before a predetermined first number A.B of cells of the multiplexed cell stream has been counted. The ratio of the second and first numbers is equal to the expected value of the mean or peak given by the relations (4) and (6). In the variance measuring circuit VMC it is checked if a predetermined second number M.B which is function of the elements of an individual cell stream has been counted before the last mentioned first number. The ratio of the second and first numbers is function of the expected value of the variance given by the -relation (7).

While tFfe- p inciples of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

Claims

1. Statistical measurement equipment for checking the relation between the measured and expected values of a parameter (m, v» p) which is function of a first set of elements and of a second set of elements included in said first set , characterized in that it includes parameter checking means (CCC, MMC; CCC VMC; CCC PMC) for checking if a predetermined second number (M.B; V.B; P) which is function of elements of said second set has been counted before a predetermined first number (A.B; A.B; A) of elements of said first set has been counted, the ratio (M/A; V/A; P/A) of said second and first predetermined numbers being function of said expected value of the parameter (m, v. p).

2. Statistical measurement equipment according to claim 1, characterized in that said second number (M.B; P) is constituted by elements of said second set and said ratio (M/A; P/A) is equal to said expected value of the parameter (m, p).

3. Statistical measurement equipment acording to claim 1, characterized in that said first (A.B, A.B, A) and second (M.B, V.B, P) numbers are adjustable.

4. Statistical measurement equipment according to claim 1, characterized in that said parameter checking means (CCC, MMC; CCC VMC; CCC PMC) includes first counting means (CRl/8) for counting the elements of said first set, a second counting means (Ml, M, C03, MC; VI, V, SUB, VC; PI) for counting said second number, first detection means (DEMUX1/3), C01/2, LI, TFF, CLA, CS) associated to said first counting means (CRl/8) for detecting when the latter has counted said first number (A.B; A.B; A) and for then providing a reset signal (MTIl; MTIl; UTI1) for said second counting means, and second detection means (DEMUX4, C04; DEMUX5, C06; C05) associated to said second counting means for detecting when the latter has counted said second number (M.B; V.B; P) and for providing an output signal (MS; VS; PS) indicative of said relation .

5. Statistical measurement equipment according to claim 1, characterized in that it includes at least one of three parameter checking means (CCC, MMC; CCC VMC; CCC PMC) for checking a respective one of the mean (m), the variance (v) and a peak (p) of a same probability distribution function.

6. Statistical measurement equipment according to claims 2 and 5, characterized in that said parameter is at least one of said mean and peak parameters.

7. Statistical mesurement equipment according to claims 4 and 5, characterized in that the output signal (VS) provided by said variance checking means (CCC, VMC) is also function of the mean mesured by said mean checking means (CCC PMC).

8. Statistical measurement equipment according to claim 5, characterized in tlTat the value (A) of said first number used by said peak checking means (CCC PMC) is considerably smaller than the value (A.B) of said first number used by said mean checking means (CCC, MMC).

9. Statistical measurement equipment according to claim 5, characterized in that the value (A.B) of said first number used by said variance parameter checking means (CCC, VMC) is substantially equal to the value (A.B) of said firstecond number used by said mean checking means ( CCC , MMC) .

10. Statistical measurement equipment according to claims 3 and 4, characterized in that said first counting ^• means (CRl/8) is able to count said adjustable first number (A.B; AB; A) of elements of said first set in an adjustable third number (B; B; 1) of steps each corresponding to an adjustable fourth number (A; A; A) of elements of said first set, said third (B; B; I) and fourth (A; A; A) numbers when different from 1 being adjustable under the control of a first (CLA) and second (CS) selection signal respectively.

11. Statistical measurement equipment according to claim 10, characterized in that said first counting means (CRl/8) is selectable, under the control of said second selection signal (CS), among a plurality of first counting means which are stepped for distinct values [2 exp (8+2a) ] of said fourth number (A).

12. Statistical measurement equipment according to claim 11, characterized in that for a first parameter type (m, v) said third number (B; B) is different from 1, so that said first number is equal to the product of the third and fourth numbers, and each of said first counting means (CRl/8) has a first set of stages (14, 17, 20, 23) corresponding to a first set of distinct values [2 exp (14+3b)] of said adjustable third number (B), that said first detection means (DEMUX1/3, C01/2, LI, TFF, CLA, CS) includes a first demultiplexer (DEMUX1), the inputs of which are coupled to respective outputs of the stages of said first set and which is controlled by said first selection signal (CLA) to select one of said multiplexer inputs or stages for connection to the first input of a first comparator (C02) whose second input is controlled by a first comparator bit (TFF) stored in a first register (TFF), and that the outputs of the first comparators (C02) associated to said first counting means (CRl/8) are connected to respective inputs of a second demultiplexer (DEMUX3) which is controlled by said second selection signal (CS) allowing a selected one of said first comparators (C02) to provide, when the compared values are equal, an activated first reset signal (MTIl) for said second counting means, said first reset signal also constituting a signal to change said comparator bit (TFF).

13. Statistical measurement equipment according to claim 11, characterized in that for a second parameter type (p) said third number is equal to 1 and each of said first counting means (CR1/9) has a second set of stages (0, 1, 2) storing the least significant bits of the number of steps counted by said first counting means, that said first detection means (DEMUX1/3, C01/2, LI, TFF, CCA, CS) includes a second comparator (COl) the first inputs of which are coupled to respective outputs of said second set of stages and the second inputs of which are coupled to third counting means (LI) storing a counter value (LI) previously stored in said second set of said first counting means, and that the outputs of the second comparators (COl) associated to said plurality of first counting means (CRl/8) are connected to respective inputs of a third demultiplexer (DEMUX2) which is controlled by said second selection signal (CS) allowing a selected one of said second comparators (COl) to provide, when the compared values are different, an activated second reset signal (UTI1) for said second counting means, said second reset signal als constituting an increment signal for said third counting means (LI).

14. Statistical measurement equipment according to claim 12, characterized in that for said first parameter type (m, v) said second number (M.V; V.B) is equal to the product of an adjustable fifth number (M; V) and said third number (B; B) and said parameter checking means is of a first type wherein said second counting means (Ml, M, C03, MC, VI, V, SUB, VC) includes fourth counting means (Ml, M, C03; VI, V, SUB) providing an activated count signal when said fifth number (M; V) has been counted and fifth counting means (MC; VC) which is coupled to the output of said fourth counting means and counts said third number (B) in steps equal to said fifth number (M; V), said fifth counting means providing said output signal (MS; VS) when said second number has been counted and being reset by said first reset signal (MTIl).

15. Statistical measurement equipment according to claim 14, characterized in that said fifth counting means (MC; VC) has a third set of stages (14, 17, 20, 23) corresponding to said first set of distinct values of said adjustable third number (B) and that said second detection means (DEMUX4; C04, DEMUX5, C06) includes a fourth demultiplexer (DEMUX4; DFEMUX5) the inputs of which are coupled to respective outputs of said third set of stages and which is controlled by said first selection signal (CLA) to select one of of said multiplexer inputs or stages for connection to the first input of a third comparator

(C04; C06) whose second input is connected to a reference value (1) and which provides said output signal (MS; VS).

16. Statistical measurement equipment according to claim 13, characterized in that for said second parameter type (p) said parameter checking means is of a second type wherein said second detection means (P, C05) includes a second register (P) for storing said second number (P) and a fourth comparator (C05) for comparing the contents of said second register (P) and of said second counting means (PI) and which is reset by said second reset signal (UTI1) and provides an activated output signal (PS) when the compared values are equal, thus indicating that said second number (P) has been counted.

17. Statistical measurement equipment according to claims 4, characterized in that it has a plurality of checking means which include individual second counting means and associated second detection means and a common first counting means and associated first detection means, the outputs (MS, VS, PS) of all second detection means controlling a status register (ST) the condition of which is indicative of the relations checked.

18. Statistical measurement equipment according to claims 5, 14 and 16, characterized in that said mean and variance parameters checking means are of said first type whereas said peak checking means is of said second type.

19. Statistical measurement equipment according to claims 16 and 18, characterized in that both said second register (P) and said second counting means (PI) used in said peak checking means (CCC, PMC) have an initial value equal to minus said fifth number (M) used in said mean checking means (CCC MMC).

20. Statistical measurement equipment according to claim 18, characterized in that in said mean checking means said fourth counting means (Ml, M, C03) includes sixth counting means (Ml) for counting the elements of said first set, a third register (M) for storing said fifth number (M) and a fifth comparator (C09) which compares the contents of said sixth counting means and of said third register (M) and provides an increment output to said fifth counting means (MC) and a reset output (R) to said sixth counting means (Ml) each time the compared values are equal, and that the output signal of said third comparator (C04) is activated when the value stored in said selected stage corresponds to said reference value. 21. Statistical measurement equipment according to claims 18 and 20, characterized in that in said variance checking means the fourth counting means (VI, V, SUB) includes a fourth register (VI) for storing a calculated variance (VI), a fifth register (V) for storing said fifth number (V) and a subtractor (SUB) which subtracts said fifth number (V) from the contents of said fourth register (VI) and provides an increment output signal to said fifth counting means (VC) and a write signal to write the contents of the subtractor (SUB) in said fifth register (VI), and that the output of said third comparator (C06) is activated when the value stored in said selected stage as well as the value stored in a stage (12, 15, 18,

21) of said fifth counting means (MC) of said mean checking means, both correspond to said reference value.

22. Statistical measurement equipment according to claims 19 and 21, characterized in that it includes means t S^~Q, MVR, SUM) to calculate, at the occurrence of said second reset signal (UTI1), said variance value (VI) from the contents of said second counting means (PI) by squaring the contents of said second counting means and adding thereat the contents of said subtractor (SUB).

23. Statistical measurement equipment according to claim 5, characterized in that said probability distribution function is that of the variable cell rate of an individual cell stream which is part of a plurality of individual cell streams multiplexed on a same communication link (ML) of a communication system on the basis of at least one of said parameters, said first set being constituted by the cells of said multiplexed cell stream and said second set being constituted by the_ cells of said individual cell stream.

24. Statistical measurement equipment according to claims 10 and 23, characterized in that said parameters (m, v, p) of said probability distribution function are traffic parameters communicated to said equipment from a user station and via said link (ML) together with a service parameter (s) indicative of the duration of the fluctuations, with respect to the mean, of the cell stream generated by said user station, and that said equipment includes means (PR) to derive said first selection signal (CLA) from one or more of said traffic parameters (m, v, p) and to derive said second selection signal (CS) from said service parameter (s).

25. Statistical measurement equipment according to claim 23, characterized in that it includes a processor

(PR) and a memory (MEM) storing for each of said individual cell streams a plurality of information which are loaded by said processor in said checking means upon the receipt of each cell of said individual cell stream and loaded back in said memory after having been processed by said checking means.

26. Statistical mesurement equipment according to claims 10, 12, 16, 17 and 21, characterized in that said information includes said first (CLA) and second (CS) selection signals, said counter value (LI), said comparator bit (TFF) the contents (ST) of said status register (ST), for said peak the contents of said first counting means (PI) and of said second register (P), for the mean the contents of said third register (M) and of said fifth (MC) and sixth (Ml) counting means, and for the variance the contents of said fourth (VI) and fifth (V) registers and of said fifth counting means (VC) and that the contents of said first (PI) and sixth (Ml) counting means are incremented by 1 upon the receipt of said cell.