WO1990000476A1 - Planarized interconnect etchback - Google Patents

Planarized interconnect etchback Download PDF

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Publication number
WO1990000476A1
WO1990000476A1 PCT/US1989/002929 US8902929W WO9000476A1 WO 1990000476 A1 WO1990000476 A1 WO 1990000476A1 US 8902929 W US8902929 W US 8902929W WO 9000476 A1 WO9000476 A1 WO 9000476A1
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WO
WIPO (PCT)
Prior art keywords
metal
metal layer
layer
interconnect
dielectric layer
Prior art date
Application number
PCT/US1989/002929
Other languages
French (fr)
Inventor
David B. Tuckerman
Original Assignee
The Regents Of The University Of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Regents Of The University Of California filed Critical The Regents Of The University Of California
Publication of WO1990000476A1 publication Critical patent/WO1990000476A1/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the invention relates generally to planarized interconnects for integrated circuit structures and more particularly to the formation of fully planarized interconnects.
  • U.S. Patents 4,674,176 and 4,681,795 to Tuckerman describe thin film metal layer planarization processes for multilevel interconnect.
  • the metal layer is planarized by heating for a brief, controlled time related to the spatial period of the features to be planarized.
  • the entire planarization process, for forming t e planarized interconnect includes forming a thin film metal layer on a dielectric layer, and briefly heating the metal layer to produce a flat surface on the metal layer. An additional dielectric layer can then be deposited and ttie process repeated as many times as necessary to produce the required number of levels.
  • planarization process in which dielectric planarization is unnecessary. This can be achieved by fabricating planarized metal interconnects which are flush with the dielectric layers. It is also desirable to develop a process in which further processing time is rapid and in which multiple interconnects can be processed simul aneously in a batch process.
  • the invention is a method of fabricating planarized thin film metal interconnects in which the planarized metal layer is etched back to the surrounding dielectric layer, preferably by electropol ishing; the invention also includes the resulting etched back planarized interconnect.
  • a dielectric layer is first patterned or etched to form either a trench for the metal interconnect or a via to an underlying metal layer or a combination of a trench and a via, and then metallized or coated with an adhesion layer (if necessary) and a metal layer which, to some extent, follows the surface contours of the etched dielectric layer.
  • the metal layer is then planarized to form a metal layer with a substantially flat surface which fills the trench and extends over the dielectric layer.
  • the flat metal layer is then etched back to the lev nowadays of the dielectric layer by el ectropol ishing or ion milling or other etchback techniques, leaving a metal interconnect with a flat surface filling the trench or via and flush with the dielectric surface.
  • the electropolishing can be carried out rapidly in a batch process in which a plurality of wafers on which planarized metal layers have been formed are electrically connected to a voltage source and placed in an electropolishing solution. In addition to performing the etchback, the electropolishing may also further planarize the metal layer.
  • the etchback can be performed in minutes by electropolishing.
  • Figures 1A-D illustrate a process for forming a planarized metal layer for an interconnect, including etching back the planarized layer.
  • Figure 2 is a perspective cutaway view of a planarized etched back interconnect structure formed with trenches, vias, and combinations thereof.
  • Figure 3 illustrates an electropolishing apparatus for performing etchback of wafers with planarized metal layers.
  • a method for fabricating planarized thin film metal interconnects for integrated circuits, and the resulting structures, is illustrated in Figures 1A-D.
  • a trench or via 10 is etched or otherwise formed in a dielectric layer 12, typically made of Si0 2 , of a circuit structure, at the location where a metal interconnect is to be formed.
  • the etched or patterned dielectric layer 12, including trench 10 is then coated by conventional methods such as sputtering or electroplating with an adhesion layer 15 (if necessary), followed by a metal layer 14 which substantially follows the surface contours of the etched dielectric layer and fills the trench.
  • the metal layer is typically about 1 to 5 microns thick and made of gold, copper, silver, or aluminum.
  • the adhesion layer is typically titanium or chromium.
  • Metal layer 14 is then planarized, e.g. by pulsed laser pulses, to form a substantially flat metal layer 16 which completely fills the trench and extends over the dielectric layer.
  • the planarization step is performed by controlled heating and melting of the metal layer, using lasers or other pulsed energy sources, for. a time related to the spatial period of the features being planarized, as further described to U.S. Patents 4,674,176 and 4,681,795, which are herein incorporated by reference.
  • the planarized metal layer 16 is etched back to the dielectric layer to form an etched back thin film metal interconnect 18.
  • the etchback is performed by electropolishing.
  • the metal layer to be etched back is made the anode in an electric circuit.
  • the metal is placed in an electrolytic bath and an electric current is run through the bath to cause anodic dissolution of the metal layer.
  • the etchback step can also be performed by ion milling or other processes. However, the ion milling etchback step is very time consuming, often greater than one hour per wafer. Also only one wafer can generally be processed at a time by ion mil 1 ing.
  • an additional, layer of dielectric is formed over the structure of Figure ID and the process is repeated.
  • the invention has been described with respect to planarizing and etching back a metal interconnect in a trench formed in a dielectric layer, the invention is also applicable to the formation of interconnects through vias (holes) extending through a " dielectric layer to an underlying metal layer, or to a combination of a trench with vias extending therefrom to an underlying metal layer.
  • the dielectric layer is first patterned with the appropriate trenches, vias, or combinations thereof; the patterned dielectric layer is then metallized, planarized, and etched back to form the interconnect.
  • a trench 33 is formed in a dielectric layer 34.
  • Dielectric layer 34, including trench 33 are then coated with metal , which is then planarized and etched back to the surface 36 of dielectric layer 34, forming a metal interconnect 32 in trench 33 which is flush with the surface 36 of dielectric layer 34.
  • An additional dielectric layer 38 is formed on layer 34 and vias 40, 42 are formed through dielectric layer 38 to underlying metal interconnect 32; the dielectric layer 38, including vias 40, 42, are then metallized.
  • the metallization is planarized and etched back to the surface 44 of dielectric layer 38, forming solid plugs of metal 41 , 43, respectively, within vias 40, 42 which are flush with the surface 44.
  • dielectric layer 46 with a trench 49 is formed on dielectric layer 38, and a metal, layer is deposited, planarized, and etched back to form an interconnect 48 in trench 49 which is flush with the surface 50 and which contacts plugs 41 , 43 in vias 40, 42.
  • Dielectric layers 38, 46 may be formed as a single layer on dielectric layer 34, and the single layer patterned with a trench 49 extending partly though the single dielectric layer (corresponding to upper layer 46) and with vias 40, 42 from the trench 49 to the underlying metal interconnect 32. The combination trench and vias are then metallized in a single operation, and the metal interconnect is planarized and etched back to upper surface 50.
  • An electropolishing apparatus 20 for carrying out the etchback of planarized metal layers on wafers in a batch process is illustrated in Figure 3.
  • a plurality of wafers 22 are placed in a tank 24 filled with electroplating solution (electrolyte) 26 and connected to the positive terminal (anode) of an applied DC voltage source 23 while electrodes 30, which resist chemical interaction with the electrolyte, e.g. carbon, are connected to the negative terminals.
  • the electrolyte is often an acid.
  • Source 28 produces the required current density for the particular metal. Gold, silver, copper and aluminum can all be electropol ished.
  • the electropolishing performs not only the etchback step but in some cases may further planarize the metal layer if the initial planarization was incomplete.
  • the operator halts the electropolishing as soon as the metal is removed from the main (non-trenched) areas of the dielectric layers, leaving only an adhesion layer (if present) on the main areas.
  • This adhesion layer may be removed by wet chemical etching.
  • the remaining metal interconnect is in the trenches and is flush with the dielectric surface.
  • Planarization is desirable to form thick multilevel metal interconnects of high integrity.
  • Performing the etchback by electropolishing reduces processing time from hours to minutes.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a process for fabricating planarized thin film metal interconnects (18) for integrated circuit structures, a planarized metal layer (14) is etched back to the underlying dielectric layer (12) by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers (22, 30). The etched back planarized thin film interconnect (18) is flush with the dielectric layer (12).

Description

PLANARIZED INTERCONNECT ETCHBACK
The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the U. S. Department of Energy and the University of California, for the operation of Lawrence Li ermore National Laboratory.
BACKGROUND OF THE INVENTION
The invention relates generally to planarized interconnects for integrated circuit structures and more particularly to the formation of fully planarized interconnects. U.S. Patents 4,674,176 and 4,681,795 to Tuckerman describe thin film metal layer planarization processes for multilevel interconnect. In the fabrication of multilevel integrated circuit structures, the planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers, particularly where vias are located. The metal layer is planarized by heating for a brief, controlled time related to the spatial period of the features to be planarized. The entire planarization process, for forming t e planarized interconnect, includes forming a thin film metal layer on a dielectric layer, and briefly heating the metal layer to produce a flat surface on the metal layer. An additional dielectric layer can then be deposited and ttie process repeated as many times as necessary to produce the required number of levels. However, in order to achieve fully planar multilevel interconnects, it is still necessary to planarize the dielectric layer.
Thus it is desirable to develop a planarization process in which dielectric planarization is unnecessary. This can be achieved by fabricating planarized metal interconnects which are flush with the dielectric layers. It is also desirable to develop a process in which further processing time is rapid and in which multiple interconnects can be processed simul aneously in a batch process.
SUMMARY OF THE INVENTION
Accordingly, it 1s an object of the invention to provide an improved •raet'hod of forming a thin film planarized metal interconnect which does not require any dielectric planarization.
It is also an object of the invention to provide an improved planarization process which is very rapid and can process multiple wafers simultaneously. It is another object of the invention to provide an improved thin film planarized metal interconnect. It is a further object of the invention to provide an improved thin film planarized metal interconnect which is flush with the surrounding dielectric layer.
The invention is a method of fabricating planarized thin film metal interconnects in which the planarized metal layer is etched back to the surrounding dielectric layer, preferably by electropol ishing; the invention also includes the resulting etched back planarized interconnect. A dielectric layer is first patterned or etched to form either a trench for the metal interconnect or a via to an underlying metal layer or a combination of a trench and a via, and then metallized or coated with an adhesion layer (if necessary) and a metal layer which, to some extent, follows the surface contours of the etched dielectric layer. The metal layer is then planarized to form a metal layer with a substantially flat surface which fills the trench and extends over the dielectric layer. The flat metal layer is then etched back to the lev?! of the dielectric layer by el ectropol ishing or ion milling or other etchback techniques, leaving a metal interconnect with a flat surface filling the trench or via and flush with the dielectric surface. The electropolishing can be carried out rapidly in a batch process in which a plurality of wafers on which planarized metal layers have been formed are electrically connected to a voltage source and placed in an electropolishing solution. In addition to performing the etchback, the electropolishing may also further planarize the metal layer. The etchback can be performed in minutes by electropolishing.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
Figures 1A-D illustrate a process for forming a planarized metal layer for an interconnect, including etching back the planarized layer.
Figure 2 is a perspective cutaway view of a planarized etched back interconnect structure formed with trenches, vias, and combinations thereof. Figure 3 illustrates an electropolishing apparatus for performing etchback of wafers with planarized metal layers. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
A method for fabricating planarized thin film metal interconnects for integrated circuits, and the resulting structures, is illustrated in Figures 1A-D. A trench or via 10 is etched or otherwise formed in a dielectric layer 12, typically made of Si02, of a circuit structure, at the location where a metal interconnect is to be formed. The etched or patterned dielectric layer 12, including trench 10, is then coated by conventional methods such as sputtering or electroplating with an adhesion layer 15 (if necessary), followed by a metal layer 14 which substantially follows the surface contours of the etched dielectric layer and fills the trench. The metal layer is typically about 1 to 5 microns thick and made of gold, copper, silver, or aluminum. The adhesion layer is typically titanium or chromium. Metal layer 14 is then planarized, e.g. by pulsed laser pulses, to form a substantially flat metal layer 16 which completely fills the trench and extends over the dielectric layer. The planarization step is performed by controlled heating and melting of the metal layer, using lasers or other pulsed energy sources, for. a time related to the spatial period of the features being planarized, as further described to U.S. Patents 4,674,176 and 4,681,795, which are herein incorporated by reference. In order to remove the metal above the dielectric layer so that the metal interconnect is flush with the surface of the dielectric layer, the planarized metal layer 16 is etched back to the dielectric layer to form an etched back thin film metal interconnect 18. In a preferred embodiment of the invention, the etchback is performed by electropolishing. The metal layer to be etched back is made the anode in an electric circuit. The metal is placed in an electrolytic bath and an electric current is run through the bath to cause anodic dissolution of the metal layer. The etchback step can also be performed by ion milling or other processes. However, the ion milling etchback step is very time consuming, often greater than one hour per wafer. Also only one wafer can generally be processed at a time by ion mil 1 ing.
To form multilevel interconnects, an additional, layer of dielectric is formed over the structure of Figure ID and the process is repeated. Although the invention has been described with respect to planarizing and etching back a metal interconnect in a trench formed in a dielectric layer, the invention is also applicable to the formation of interconnects through vias (holes) extending through a " dielectric layer to an underlying metal layer, or to a combination of a trench with vias extending therefrom to an underlying metal layer. In each case, the dielectric layer is first patterned with the appropriate trenches, vias, or combinations thereof; the patterned dielectric layer is then metallized, planarized, and etched back to form the interconnect.
The various types of interconnect structures are illustrated in Figure 2. A trench 33 is formed in a dielectric layer 34. Dielectric layer 34, including trench 33, are then coated with metal , which is then planarized and etched back to the surface 36 of dielectric layer 34, forming a metal interconnect 32 in trench 33 which is flush with the surface 36 of dielectric layer 34. An additional dielectric layer 38 is formed on layer 34 and vias 40, 42 are formed through dielectric layer 38 to underlying metal interconnect 32; the dielectric layer 38, including vias 40, 42, are then metallized. The metallization is planarized and etched back to the surface 44 of dielectric layer 38, forming solid plugs of metal 41 , 43, respectively, within vias 40, 42 which are flush with the surface 44. Another dielectric layer 46 with a trench 49 is formed on dielectric layer 38, and a metal, layer is deposited, planarized, and etched back to form an interconnect 48 in trench 49 which is flush with the surface 50 and which contacts plugs 41 , 43 in vias 40, 42. Dielectric layers 38, 46 may be formed as a single layer on dielectric layer 34, and the single layer patterned with a trench 49 extending partly though the single dielectric layer (corresponding to upper layer 46) and with vias 40, 42 from the trench 49 to the underlying metal interconnect 32. The combination trench and vias are then metallized in a single operation, and the metal interconnect is planarized and etched back to upper surface 50. An electropolishing apparatus 20 for carrying out the etchback of planarized metal layers on wafers in a batch process is illustrated in Figure 3. A plurality of wafers 22 are placed in a tank 24 filled with electroplating solution (electrolyte) 26 and connected to the positive terminal (anode) of an applied DC voltage source 23 while electrodes 30, which resist chemical interaction with the electrolyte, e.g. carbon, are connected to the negative terminals. The electrolyte is often an acid. Source 28 produces the required current density for the particular metal. Gold, silver, copper and aluminum can all be electropol ished. The electropolishing performs not only the etchback step but in some cases may further planarize the metal layer if the initial planarization was incomplete. The operator halts the electropolishing as soon as the metal is removed from the main (non-trenched) areas of the dielectric layers, leaving only an adhesion layer (if present) on the main areas. This adhesion layer may be removed by wet chemical etching. The remaining metal interconnect is in the trenches and is flush with the dielectric surface.
Planarization is desirable to form thick multilevel metal interconnects of high integrity. Performing the etchback by electropolishing reduces processing time from hours to minutes.
Changes and modifications in the specifically described embodiments can be carried out without departing from the scope of the invention which is intended to be limited only by the scope of the appended claims.

Claims

1. Method of forming a planarized thin film metal interconnect in a dielectric layer on an integrated circuit wafer, comprising: forming a trench or via in the dielectric la er for the metal interconnect; depositing a metal layer on the dielectric layer; planarizing the metal layer to form a metal layer with a substantially flat surface which fills the trench or via and extends over the surrounding dielectric layer; etching back the flat metal layer to the dielectric layer.
2. The method of Claim 1 wherein the metal is etched back by electropolishing.
3. The method of Claim 1 wherein the metal is etched back by ion milling.
4. The method of Claim 1 wherein the trench or via is formed in the dielectric layer by etching.
5. The method of Claim 1 wherein the planarization of the metal layer is performed by controlled heating and melting of the metal layer for a time related to the spatial period of the features being pi anarized.
6. The method of Claim 5 wherein the controlled heating and melting is performed by applying pulsed energy to the metal layer.
7. The method of Claim 6 comprising applying laser pulses.
8. The method of Claim 1 further comprising forming the metal layer of gold, silver, copper, or aluminum.
9. The method of Claim 1 further comprising, forming the metal layer with a thickness in the range of about 1 to 5 microns.
10. The method of Claim 2 wherein the etching back by electropolishing is performed by: connecting the wafer to the anode of a DC voltage source; placing the wafer in an electrolyte; flowing a DC current of sufficient current density through the wafer.
11. The method of Claim 2 further comprising performing the etching back by electropolishing on a plurality of wafers simultaneously.
12. The method of Claim 1 further comprising forming an additional dielectric layer over the etched back metal interconnect and repeating the steps of forming a trench or via, depositing a metal layer, planarizing the metal layer and etching back the metal layer to form a multilevel interconnect.
13. The method of Claim 12 wherein the metal layer is etched back by electropolishing.
14. The method of Claim 12 wherein the metal layer is etched back by ion milling.
15. In an integrated circuit structure, a metal interconnect comprising an etched back planarized thin film metal interconnect formed in a dielectric layer of the circuit structure and having a planarized flat surface which is flush with the dielectric layer.
16. The etched back metal interconnect of Claim 15 wherein the metal interconnect is formed of gold, copper, silver, or aluminum.
17. The etched back metal interconnect of Claim 15 wherein the metal interconnect has a thickness of about 1-5 microns.
18. The etched back metal interconnect of Claim 5 arranged in a multilevel interconnect.
PCT/US1989/002929 1988-07-12 1989-07-10 Planarized interconnect etchback WO1990000476A1 (en)

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Application Number Priority Date Filing Date Title
US21791588A 1988-07-12 1988-07-12
US217,915 1988-07-12

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0471664A1 (en) * 1989-05-08 1992-02-26 United States Department Of Energy Electrochemical planarization
DE4219016A1 (en) * 1991-06-10 1992-12-17 Micron Technology Inc METHOD THAT FILLS A DEEP IN THE ESSENTIAL
US5312770A (en) * 1991-06-06 1994-05-17 Lsi Logic Corporation Techniques for forming isolation structures
WO2000003426A1 (en) * 1998-07-09 2000-01-20 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US6248222B1 (en) 1998-09-08 2001-06-19 Acm Research, Inc. Methods and apparatus for holding and positioning semiconductor workpieces during electropolishing and/or electroplating of the workpieces
US6391166B1 (en) 1998-02-12 2002-05-21 Acm Research, Inc. Plating apparatus and method
US6447668B1 (en) 1998-07-09 2002-09-10 Acm Research, Inc. Methods and apparatus for end-point detection
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
RU2631575C2 (en) * 2010-11-22 2017-09-25 МЕТКОН, ЭлЭлСи Electrolyte solution and electrochemical methods for surface modification

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849270A (en) * 1971-10-11 1974-11-19 Fujitsu Ltd Process of manufacturing semiconductor devices
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
US4800179A (en) * 1986-06-13 1989-01-24 Fujitsu Limited Method for fabricating semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849270A (en) * 1971-10-11 1974-11-19 Fujitsu Ltd Process of manufacturing semiconductor devices
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
US4800179A (en) * 1986-06-13 1989-01-24 Fujitsu Limited Method for fabricating semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0471664A1 (en) * 1989-05-08 1992-02-26 United States Department Of Energy Electrochemical planarization
EP0471664A4 (en) * 1989-05-08 1993-02-10 United States Department Of Energy Electrochemical planarization
US5312770A (en) * 1991-06-06 1994-05-17 Lsi Logic Corporation Techniques for forming isolation structures
DE4219016A1 (en) * 1991-06-10 1992-12-17 Micron Technology Inc METHOD THAT FILLS A DEEP IN THE ESSENTIAL
US6391166B1 (en) 1998-02-12 2002-05-21 Acm Research, Inc. Plating apparatus and method
WO2000003426A1 (en) * 1998-07-09 2000-01-20 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US6440295B1 (en) 1998-07-09 2002-08-27 Acm Research, Inc. Method for electropolishing metal on semiconductor devices
US6447668B1 (en) 1998-07-09 2002-09-10 Acm Research, Inc. Methods and apparatus for end-point detection
US7136173B2 (en) 1998-07-09 2006-11-14 Acm Research, Inc. Method and apparatus for end-point detection
US6248222B1 (en) 1998-09-08 2001-06-19 Acm Research, Inc. Methods and apparatus for holding and positioning semiconductor workpieces during electropolishing and/or electroplating of the workpieces
US6495007B2 (en) 1998-09-08 2002-12-17 Acm Research, Inc. Methods and apparatus for holding and positioning semiconductor workpieces during electropolishing and/or electroplating of the workplaces
US6749728B2 (en) 1998-09-08 2004-06-15 Acm Research, Inc. Methods and apparatus for holding and positioning semiconductor workpieces during electropolishing and/or electroplating of the workpieces
RU2631575C2 (en) * 2010-11-22 2017-09-25 МЕТКОН, ЭлЭлСи Electrolyte solution and electrochemical methods for surface modification

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