WO1990009062A1 - Transceiver with serial control port - Google Patents

Abstract

A CEPT transceiver (115, 125) wherein a serial control port (130) permits close microprocessor-based control. A RAM-based architecture (140) is used for the control and status registers, with access restrictions on the serial port (130) side to prevent access collisions. The transmit and receive clocks (110, 120) are allowed to be totally asynchronous to the serial port's clock, and no status updates are ever missed.

Description

TRANSCEIVER WITH SERIAL

CONTROL PORT

BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates to integrated circuits for communications applications, and particularly to transceivers for highly defined communications standards as CEPT or Tl.

The present invention provides a transceiver which also includes a serial control port. This serial control port allows access to fourteen on- chip control and status registers,. This allows an external processor to control such features as error logging, per-channel code manipulation and alteration of receive synchronize algorithm and various other modes.

The presently preferred embodiment provides three clocks on the chip: one clock is used for transmitter operation, one clock is used for receiver operation, and one clock is used for access to the serial port.

The control registers control operation of the transmit and receive operations, while the status registers report various transmit and receive status information. This poses a unique synchronization problem for the serial port operation.

The port registers are externally accessed via CS*, SDI, SDO signals, (and signal SCLK is used to regulate data transfer). However, the transmitter logic needs to run off the TCLK signal. Thus, if the transmit- side registers are updated using the SCLK (when written into by an external processor), then the register bits will be changing asynchronously to the TCLK. Therefore, to avoid unreliable operation, these control register bits must be synchronized to the TCLK before they can be used inside the transmit logic. Similarly, the receive side status registers (and the receive side error counters) are updated by the receive logic, which is running off the receive clock RCLK Before these registers can be accessed by an external processor (which has only SCLK to work with), they must be synchronized to the serial-port clock SCLK.

Thus each bit in the fourteen registers needs to be synchronized to SCLK as well as to RCLK or TCLK. If this synchronization is not done, then the following undesirable consequences will occur: 1) When the registers are updated by an external source, the logic driven by the updated register bits will have a glitch, and possibly could propagate an improper state throughout the rest of the chip (in a worst case scenario).

2) When the status registers are updated by the receive logic, or error counters are changing on RCLK edges, then if a read occurs

(from an external source) invalid data can be read. Alternatively, if update of the status registers and error counter is inhibited during port reads by the external processor, then the error counter may miss errors.

Another requirement of the serial port is that data is read and written serially by the external source (using SCLK). Each register is 8 bits wide internally. If the 8-bit data for those registers is updated serially (or readout serially) one bit at a time, then various undesirable consequences may result:

First, suppose the 8 bit error counter is changing (e.g. from 7F_H to 80_H), and this counter is being read out serially, with the LSB first. In this example, instead of reading 7F_H or 80_H the apparent value read might be 81_H, 83_H, 87_H, 8F_H, 9F_H, BF_H, or FF_H. To prevent this, the counter updates may have to be inhibited during port reads, which could result in missing valuable error events. Because the SCLK could run very slowly (even, for example, as slow as about 100 Hz), while the RCLK runs (in the preferred embodiment) at 2.048 MHz, many errors could be missed.

Similarly, if control bits are updated one at a time, then the 8 bit control register could go through various illegal data words before the correct word is entered. This could also put the chip in an illegal state, and cause an external pin signal to have distorted values during port writes.

This means that, for unhindered reliable operation, 8 bits should be read or updated during the same clock cycle. This creates a difficult requirement that, depending on who is updating the register (e.g. a TCLK source, RCLK source or an SCLK source), and who is reading or using the register (again, this could be an RCLK, TCLK, or SCLK target), the 8-bit data has to be delayed or held for proper operation. Another problem which must be considered is chip layout complexity. A conceptually simple method (but a designer's nightmare) would be to design the port to read/write information through serial port signals SCLK, SDI, SDO, and CS*, and to route each individual register bit output (using a drive buffer for each bit) to the logic where it will be used. For example, several of the register bits control respective multiplexers, which are connected to select one of several data inputs. One technique which has been previously used is to build a giant multiplexer, with all data sources and all control register bits routed to decoding logic. This decoding logic decodes all of these inputs, to produce gating signals to transmission gates which route the various data sources accordingly. This technique requires routing many metal and polysihcon lines out of the register file - one line for every control bit. Substantial area is also required for the logic and wiring of the giant multiplexer.

The transmitter can be regarded as a very complex multiplexer, with one serial output and many input sources. Various modes and options make it very complex, as the source may change bit by bit. Many combinations may be created by the different modes and options which can be selected by the control registers.

The present invention solves these problems by integrating port and transceiver logic into one major block, to provide a universal synchronization method and minimize the wiring requirements. This innovation has simplified the complex multiplexer, which would otherwise be required, into a veiy simple structure. The messy wiring (which would otherwise be required) has been simplified, and data flow is very streamlined. Instead of the register-based architecture conventionally used, the present invention uses a RAM-based architecture. A dual-ported memory array is used to store the control and status bits. The serial control port can interface to this array only through serial/parallel conversion logic (so that all eight bits of an accessed word are accessed at the same instant). One port of this array is connected to the serial control port, and the other port is connected to the transmit or receive control logic. (Some bits are connected to the transmit control logic, and some bits are connected to the receive control logic.) Access collision is prevented by allowing serial port access only when the other port is not being accessed.

Advantages of this innovative architecture include:

1. Silicon area consumption is greatly reduced, due to the reduced demands of wiring and associated routing.

2. The use of individual synchronization logic (at least one full flip-flop) for each register bit can now be avoided. Since there are 112 bits in the 14 registers, this too leads to a significant savings in silicon area.

3. No error or status events will be lost.

4. A triple access port is realized, where all three accesses are totally asynchronous to each other, and there is no data corruption.

5. The simplified layout provided by the present invention has resulted in an area savings, for comparable geometries, of nearly 50%.

6. The present invention results in a veiy regular organization. This speeds the design cycle time, since layout and verification can be performed much more quickly.

In the presently preferred embodiment, the register file is configured as two dual-ported subarrays: one which is accessed by the serial port and the transmit side, and one subarray which is accessible by the serial port and the receive side. The serial port accesses the register bits through a serial/parallel conversion register. All read and write access by the serial/parallel register is gated by the low state of the complementary clock. That is, in a control register which affects the transmit operation, the serial/parallel register (and therefore the serial port) cannot write data in unless the transmit clock TCLK is low. This means that access by the two sides of the dual-ported register is automatically interleaved, so that access collisions cannot occur.

A further advantage is that the full eight bits of each control word are transferred in parallel. This avoids the problem of "stringing out" discussed above, which could lead to impossible control states.

A further innovative teaching is that some of the outputs of the transmitter control logic, which control other circuits on-chip, are combined on a common 8-bit bus.

A further innovative teaching is that a comparator, for generating off- chip interrupts, is integrated with the control logic. This further economizes on interconnect area requirements.

The presently preferred embodiment is an integrated circuit which is especially adapted to send and receive signals in the CEPT protocol (for example, for interface to telephone company trunk lines in Europe). However, it should be recognized that this architecture can be adapted to other applications with analogous needs. In general, this architecture can used to provide improved microprocessor-based control of many application where an interface has its own timing requirements which must not be disturbed. Additional logic is used for the clock phases which do not involve data transfer. For example, the bit lines on the transmit side may be being precharged while the serial/parallel register is writing. However, the data transfer phases are completely interleaved.

BRIEF DESCRIPTION OF THE DRAWING

The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

Figure 1 shows the overall architecture of the integrated circuit of the presently preferred embodiment.

Figure 2 shows greater detail of the configuration of the Register block 140. Figures 3A and 3B show a more detailed view of the circuit of the serial port control register 130. The serial/parallel conversion logic is shown in greater detail in Figure 3C.

Figures 4A, 4B, 4C, and 4D are a single circuit diagram, which shows important parts of the transmit control logic 220. Figure 4E shows elements used, in the transmit control logic 210, to access the memory array 200.

Figures 5A and 5B (which are a single circuit diagram in two parts) show a further feature which is preferably connected to the bus SPB0/NPB0-SPB7/NSPB7. Figure 6A shows a portion of the left side of memory array 200.

Figure 6B shows a direct-wired receive control register 650. Figure 6C shows an additional feature which is, in the presently preferred embodiment, combined with the layout of the array 200.

Figgure 7C shows an innovative CRC bit generation architecture. Figure 7D shows a conventional architecture. Figure 7A is a detailed circuit diagram of the CRC encoding logic, in the presently preferred embodiment. Figure 7B is a detailed circuit diagram of the CRC decoding logic, in the presently preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS

The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment, wherein these innovative teachings are advantageously applied to the particular problems of a CEPT transceiver. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. Figure 1 shows the overall architecture of the integrated circuit of the presently preferred embodiment.

The transmit timing logic 110 provides output signals TMO, TAF, TSTS, and TCHCLK in accordance with input signals TCLK (the transmit clock), TFSYNC, and TMSYNC. The transmit timing logic 110 also, through align word generator 112, controls the data selector 114, which selects an output data stream from the sources TSER, TSD, TIND, and TXD. (All of these signals are discussed in greater detail below.) An alarm generator 113 also provides an input to the selector 114, so that alarm signals can be transmitted if necessary.

The output of the selector 114 is encoded by an HDB3 coder 115, to provide output signals TPOS and TNEG. These signals would normally be connected off-chip, to control a line interface chip, such as the DS2186. (This chip, and its data sheet in a "1989 Telecom Products" Data Book, available from Dallas Semiconductor Corporation, 4350 Beltwood Parkway, Dallas TX 75244, are both hereby incorporated by reference.)

Similarly, signals RPOS, RNEG, and RCLK would be received (for example) from a receive line interface chip, such as the DS2187. (This chip, and its data sheet in a "1989 Telecom Products" Data Book, available from Dallas Semiconductor Corporation, 4350 Beltwood Parkway, Dallas TX 75244, are both hereby incorporated by reference.) An HDB3 decoder 125 decodes these signals, and synchronizer logic 122 receives the decoded signals (and the read clock RCLK). A loopback block 129 also permits the output of coder 115 to be connected directly to decoder 125. The outputs of the synchronization control logic 122 are supplied to the receive timing logic 120, and to the alarm detection logic 123. A data demultiplexer provides outputs RSER and RSD. (Note that the operation of blocks 120, 126, and 123 too is controlled by the clock signal RCLK.) Serial Port Control Logic 130 interfaces to the serial control port (pins

SDI, SDO, SCLK, and CS*).

The Control, Status, and Alarm Registers 140 provide a key control block in this architecture. The registers 140 interface to data selector 114, to the synchronizer 122, to loopback connection 129, to the serial port control logic 130, to the alarm logics 113 and 123, and to the coder 115 and decoder 125. The configuration, connection and operation of these registers will be described in detail below.

Figure 2 shows greater detail of the configuration of the Register block 140. The actual data storage is contained in a memory array 200, which contains 14 8-bit words. This array includes two subarrays, both dual-ported: one subarray is dual-ported between the serial port control logic 130 and the receive control logic 220; the other subarray is dual- ported between the serial port control logic 130 and the transmit control logic 210. (The receive control logic 220 is partly the same as the block shown as synchronizer 122 in Figure 1. Similarly, the transmit control logic 210 partly overlaps with the alarm generator logic 113 and the selector 114. However, Figure 2 has been drawn with slightly different block boundaries than Figure 1, for clearer discussion of the interface to the control, status and alarm registers 200.) Figures 3A through 6D provide extremely detailed circuit diagrams of the presently preferred embodiment, including the circuit context of the presently preferred embodiment. It will be understood by those skilled in the art that these diagrams include a tremendous amount of detail which is not strictly necessary for the understanding of the present invention. Therefore, the following description will point out important features in these drawings, but will not point out every feature.

Figures 3A and 3B show a more detailed view of the circuit of the serial port control register 130. Note that a data input SSDI is provided as input to serial/parallel logic 320 (which can also receive parallel inputs deriving from the memory array 200). Note also that logic 310 generates a signal MEMCLK, which will be active only when TCLK (or RCLK, depending on the register being addressed) is low. Since the signal MEMCLK conditions access to the array 200 by the serial port controller 130, this logic prevents collision between the two ports of the memory array 200, as described above. The serial/parallel conversion logic is shown in greater detail in Figure 3C.

Figures 4A, 4B, 4C, and 4D are a single circuit diagram. (The dotted line shows boundaries between these four segments. Some overlap is also shown, to permit the wiring relations to be clearly perceived.) This four- part circuit diagram shows important parts of the transmit control logic 220. Twelve-bit counter chain 410, driven by TCLK, provides bit position (TBP0-TBP2), channel (TCH0-TCH4), and frame (TFR0-TFR3) position outputs, to track the channel and frame definitions required by the CEPT protocol. Note that column decode logic 420 provides Column address outputs COL00, COL01, COL10, and COL11 in accordance with outputs of this counter. Note also that logic related to cyclic redundancy generation is shown in area 430.

Figure 4E shows elements used, in the transmit control logic 210, to access the memory array 200. Area 450 shows the precharge and load devices for each of the column pairs TBO/NTBO - TB7/NTB7. Column select logic 440 selects one of eight columns, in accordance with bits COLOO-COLll mentioned above combined with the column-address LSB COLEVEN and its complement COLODD.

The logic used to perform these functions on the receive side is, in general, closely analogous. However, since no on-the-fly bit-stuffing is needed, the logic for the receive side logic 220 is somewhat simpler than the transmit-side logic.

Figure 6A shows a portion of the left side of memory array 200. Note that this figure shows one row (in area 610) where data values have been hardwired in. This provides overhead bits, defined in the CEPT protocol, which may be stuffed into the appropriate time slots in the transmitted signal. Row 620 shows a more normal column, where each bit of data is stored in a cross-coupled latch 604, accessible by a first pair of pass transistors 601 (controlled, for the specific cell shown, by transmit-side word line TINRTB), and also by a second pair of pass transistors 602 (controlled, for the specific cell shown, by serial-side word line TINRSB). Whenever line TINRTB goes high, the two nodes of this particular latch 604 will be connected to a first complementary pair of column lines (in this example, lines TB4 and NTB4); and, independently of this, whenever line TINRSB goes high, the two nodes of this particular latch 604 will be connected to a second complementary pair of column lines (in this example, lines SPBB4 and NSPB4).

In fact, the eight column-line-pairs SPB0/NSPB0 through SPB7/NSPB7 run all the way across the array 200. In most of the left subarray, these will be paralleled by eight other column-line-pairs TBO/NTBO through TB7/NTB7, and in most of the right subarray, the eight column-line-pairs SPB0/NSPB0 through SPB7/NSPB7 will be paralleled by eight other column-line-pairs RB0 NRB0 through RB7/NRB7. However, some of the registers have significantly different organizations, as will be described below.

In the configuration of Figure 6A, in the presently preferred embodiment, row 620 is used for international/national data. Row 640 (which has some bits hard-wired low) is used for multi-frame synchronization. Area 630 is the transmit signalling register. Figure 6B shows a direct-wired receive control register 650. Note that the bit outputs of this register are not connected through the memory access logic (as are, for example, the outputs of row 620), but are directly wired to provide fully static digital outputs. However, access collision is still avoided, since the elements which receive these direct-wired control signal outputs will be clocked by RCLK. Thus, even though the direct- wired control outputs will transition immediately when a write access occurs from the serial port logic 130, these transitions will be guaranteed to occur when RCLK is low, so that the transient states which may occur cannot possibly propagate. Figure 6C shows an additional feature which is, in the presently preferred embodiment, combined with the layout of the array 200. A mask register 660 holds a set of eight interrupt mask values, and compare logic 670 generates a complemented interrupt output NINTOUT if any high bit in the mask register 660 matches a high bit in the status register 680. Figures 5A and 5B (which are a single circuit diagram in two parts) show a further feature which is preferably connected to the bus SPB0/NPB0-SPB7/NSPB7. The logic shown provides frame error counting and CRC error counting. The overall chip architecture has following notable features (some of which are innovative):

Single chip primary rate transceiver meets CCITT standards: G.704

Supports new CRC4 based framing standards and CAS and CCS signalling standards;

Simple serial interface used for device configuration and control in "processor" mode

"Hardware" mode requires no host processor; intended for stand-alone applications Comprehensive on-chip alarm generation, alarm detection and error logging logic

5V supply, low power CMOS technology.

The chip of the presently preferred embodiment is designed for use in CEPT networks and supports all logical requirements of CCITT Red Book Recommendations G.704 and G.732. The transmit side generates framing patterns and CRC4 codes, formats outgoing channel and signalling data and produces network alarm codes when enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and

CRC4 multiframe alignments. Once synchronized, the device extracts channel, signalling and alarm data.

A serial port allows access to 14 on-chip control and status registers in the processor mode. In this mode, a host processor controls such features such as error logging, pre-channel code manipulation and alternation of the receive synchronizer algorithm. The hardware mode is intended for preliminary system prototyping and/or retrofitting into existing systems. This mode requires no host processor and disables special features available in the processor mode.

TRANSMIT PIN DESCRIPTION PINSYMBOL TYPE DESCRIPTION 1 TMSYNC 1 Transmit Multiframe Sync Low-high transition establishes start of CAS and/or CRC4 multiframe. May be tied to low, allowing internal multiframe counter to run free.

2 TFSYNC 1 Transmit Frame Sync. Low high transition every frame period establishes frame boundaries. May be tied low, allowing TMSYNC to establish frame boundaries. 3 TCLK 1 Transmit Clock. 2.048 MHz primary clock. 4 TCHCLK 0 Transmit Channel Clock. 256 kHz clock which identifies timeslot boundaries. Useful for parallel to serial conversion of channel data. 5 TSER Transmit Serial Data. NRZ data input, sampled on falling edges of TCLK. 6 TMO 0 Transmit Multiframe Out, Output of multiframe counter, high during frame 0, low otherwise. 7 TXD Transmit Extra Data. Sampled on falling edge of TCLK during bit times 5, 7, and 8 of timeslot 16 in frame 0 when CAS signalling is enabled.

8 TSTS 0 Transmit Signalling Timeslot High during timeslot 16 of every frame, low otherwise.

9 TSD Transmit Signalling Data. CAS signalling data input; sampled on falling edges of TCLK for insertion into outgoing timeslot 16 when enabled. 10 TND Transmit International and National Data. Sampled on falling edge of TCLK during bit 1 time of timeslot 0 every frame (international) and/or during bit times 4 thru 8 of timeslot 0 during non-align frames (national) when enabled. 11 TAF Transmit Alignment Frame. High during frames containing the frame alignment signal, low otherwise.

12 TPOS 0 Transmit Bipolar Data Outputs.

13 TNEG Updated on rising edge of TCLK.

RECEIVE PIN DESCRIPTION

PINSYMBOL TYPE DESCRIPTION

21 RRA 0 Receive Remote Alarm. Transitions high when alarm detected, returns low when alarm cleared.

22 RDMA 0 Receive Distant Multiframe Alarm.

Transitions high when alarm detected, returns low when alarm cleared. 23 RAF 0 Receive Alignment Frame. High during frames containing the frame alignment signal, low otherwise.

24 RCLK 1 Receive Clock. 2.048 MHz primary clock.

25 RCHCLK 0 Receive Channel Clock. 256 kHz clock, identifies timeslot boundaries; useful for serial to parallel conversion of channel data.

26 RSER 0 Receive Serial Data. Received NRZ data, updated on rising edges of RCLK. 27 RFSYNC 00 Receive Frame Sync. Trailing edge indicates start of frame.

28 RMSYNC 0 Receive Multiframe Sync. Low-high transition indicates start of CAS multiframe, held high during frame 0. 29 RSD 0 Receive Signaling Data. Extracted timeslot

16 data, updated on rising edge of RCLK.

30 RSTS 0 Receive Signaling Timeslot. High during timeslot 16 of every frame, low otherwise. 31 RCSYNC 0 Receive CRC4 Sync. Low-high transition indicates start of CRC4 multiframe, held high during CRC4 frames 0 thru 7 and held low during frames 8 through 15.

33 RST* Reset. Must be asserted during device power-up and when changing to/from the hardware mode.

34 RPOS Receive Bipolar Data.

35 RNEG Sampled on falling edges of RCLK. 36 RCL Receive Carrier Loss. Low-high transition indicates loss of carrier.

37 RBV 0 Receive Bipolar Violation. Pulses high during detected bipolar violations.

38 RFER 0 Receive Frame Error. Pulses high when frame alignment, CAS multiframe alignment or CRC4 words received in error.

39 RLOS Receive Loss of Sync. Indicates synchronizer status; high when frame, CAS and/or CRC4 multiframe search underway, low otherwise.

PORT PIN DESCRIPTION PINSYMBOL TYPE DESCRIPTION

14 INT* 0 Receive Alarm Interrupt. Flags host controller during alarm conditions. Active low, open drain output.

15 SDI Serial Data In. Data for on-chip control registers; sampled on rising edge of SCLK.

16 SDO 0 Serial Data Out. Control and status data from on-chip registers. Updated on falling edge of SCLK, tristated during port write or when CS is high. 17 CS* 1 Chip Select. Must be low to write or read the serial port.

18 SCLK 1 Serial Data Clock. Used to write or read the serial port registers. 19 SPS 1 Serial Port Select. Tie to V_DD to select the serial port. Tie to V_ss to select the hardware mode.

POWER AND TEST PIN DESCRIPTION

s for normal

REGISTER SUMMARY NAME ADDRESS T/R¹ DESCRIPΗON/FUNCTION RIMR 0000 R Receive Interrupt Mask Register. Allows masking of alarm generated interrupts.

RSR 0001 R² Receive Status Register. Reports all receive alarm conditions. BVCR 0010 R Bipolar Violation Count Register. 8 bit presettable counter which records individual bipolar violations.

CECR 0011 R CRC4 Error Count Register. 8 bit presettable counter which records individual CRC4 errors.

FECR 0100 R Frame Error Count Register. 8 bit presettable counter which logs individual errors in the received frame alignment signal. RCR 0101 R Receive Control Register. Establishes receive side operating characteristics. CCR 0110 T/R Common Control Register. Establishes additional operating characteristics for transmit and receive sides.

TCR 0111 T Transmit Control Register. Establishes transmit side operation characteristics.

T Transmit Idle Register.

Designates which outgoing timeslots are to be substituted with idle code.

TTNR 1100 Transmit International and National Register. When enabled via the TCR, contents inserted into the outgoing national and/or international bit positions. TXR 1101 Transmit Extra Register. When enabled via the TCR, contents inserted into the outgoing extra bit positions.

Notes:

1. Transmit or receive side register.

2. RSR is a read only register, all other registers are read write.

3. Reserved bit locations must be programmed to zero.

SERIAL PORT INTERFACE:

Pins 14 thru 18 of the chip of the presently preferred embodiment serve as a microprocessor/microcontroller compatible serial port. 14 on- chip registers allow the user to update operational characteristics and monitor device status via a host controller, minimizing hardware interfaces. Port read write timing is unrelated to the chip transmit and receive timing, allowing asynchronous reads and/or writes by the host. The timing set is identical to that of "8051 type" microcontrollers operating in serial port mode 0. For proper operation of the port and the transmit and receive registers, the user should provide TCLK and RCLK as well as

SCLK. ADDRESS/COMMAND:

An address/command byte write must precede any read or write of the port registers. The first bit written (LSB) of the address/command byte specifies read or write. The following nibble identifies register address. The next two bits are reserved and must be set to zero for proper operation. The last bit of the address/command word enables the burst mode when set; the burst mode allows consecutive reading or writing of all register data. Data is written to and read from the port LSB first

CHIP SELECT AND CLOCK CONTROL: All data transfers are initiated by driving the CS* input low. Data is sampled on the rising edge of SCLK and must be valid during the previous low period of SCLK to prevent momentary corruption of written register contents. Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are terminated and SDO tristated when CS* returns to high.

CLOCKS:

To access the serial port registers both TCLK and RCLK are required along with the SCLK. The TCLK and RCLK are used to access internally the transmit and receive registers respectively. The CCR is considered a receive register for this purpose.

DATA I/O:

Following the 8 SCLK cycles that input the address/command byte, data at SDI is strobed into the addressed register on the next 8 SCLK cycles (register write) or data is presented at SDO on the next 8 SCLK cycles (register read). SDO is tristated during writes and may be tied to SDI in applications where the host processor has bidirectional I/O capability.

BURST MODE:

The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This feature minimizes device initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the address nibble is 0000. All registers must be read or written during the burst mode. If CS* transitions high before the burst is complete, data validity is not guaranteed.

ACB; ADDRESS COMMAND BYTE SYMBOL POSITION NAME AND DESCRIPTION

BM ACB.7 Burst Mode. If set (and ACB.l thru ACB.4=0) burst read or write is enabled. eserved, must be 0 for proper operation. eserved, must be 0 for proper operation. MSB of register address.

LSB of register address.

Read/Write select 0=Write addressed register. l=Read addressed register. TCR: TRANSMIT CONTROL REGISTER SYMB: POSITION NAME AND DESCRIPTION TUAl TCR.7 Transmit Unframed All Is 0=Noπnal operation. l=Replace outgoing data at TPOS and TNEG with unframed all Is code. TSSTCR.6 Transmit Signalling Select¹

0=Signalling data embedded in the serial bit stream is sampled at TSER during timeslot 16. l=Signalling data is channel associated and sampled at TSD as shown in Table 6. TSM TCR.5 Transmit Signalling Mode¹

0=Channel Associated Signalling (CAS) l=Common Channel Signalling (CCS)

INBS TCR.4 International Bit Select

0=Samρle international bit at TIND l=Outgoing international bit=TINR.7 NBS TCR.3 National Bit Select 0=Samρle national bits at TIND

1= Source outgoing national bits from TINR.4 thru TINR.0 XBS TCR.2 Extra Bit Select

0=Sample extra bits at TXD l=Source extra bits from TXR.0 thru TXR.1 and

TXR.3 TSA1 TCR.1 Transmit Signalling All "Is"

0=Noπnal operation l=Force contents of timeslot 16 in all frames to all "Is" ODM TCR.0 Output Data Mode

0=TPOS and TNEG outputs are 100% duty cycle. l=TPOS and TNEG outputs are 50% duty cycle. NOTE: 1. When the common channel signalling mode is enabled (TCR.5=1), the TSD input is disabled internally; all timeslot 16 data is sampled at TSER. CCR: COMMON CONTROL REGISTER

SYMBOL POSITION NAME AND DESCRIPTION

CCR.7 Reserved,must be 0 for proper operation.

TAFP CCR.6 Transmit Align Frame Position¹

When clear, the CAS multiframe begins with a frame containing the frame alignment signal. When set, the CAS multiframe begins with a frame not containing the frame alignment signal. THDE CCR.5 Transmit HDB3 Enable

0=Outgoing data at TPOS and TNEG is AMI coded. l=Outgoing data at TPOS and TNEG is HDB3 coded. TCE CCR.3 Transmit CRC4 Enable When set, outgoing international bit positions in frames 0 thru 12 and 14 are replaced by CRC4 multiframe alignment and checksum words. RCE CCR.2 Receive CRC4 Enable 0=Disable CRC4 multiframe synchronizer l=Enable CRC4 synchronizer, search for CRC4 multiframe alignment once frame alignment complete. CCR.0 Local Loopback 0=Noπnal operation l=Inteπιally loop TPOS, TNEG and TCLK to RPOS, RNEG and RCLK.

NOTES

1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3=1); its state does not affect CCS framing (RCR.5=1).

2. CCR is considered a receive register and operates from RCLK and SCLK

RCR; RECEIVE CONTROL REGISTER SYMBOL POSITION NAME AND DESCRIPTION — RCR.7 Reserved, must be 0 for proper operation.

RCR.6 Reserved, must be 0 for proper operation.

RSM RCR.5 Received Signalling Mode

0=Channel Associated Signalling (CAS) 1= Common Channel Signalling (CSS) CMSC RCR. CAS Multiframe Synch Criteria

0=Declare sync when fixed sync criteria met l=Declare sync when fixed criteria are met and two additional consecutive valid multiframe alignment signals are detected. CMRC RCR.3 CAS Multiframe Resync Criteria

0=Utilize only fixed resync criteria l=Resync if fixed criteria met and/or if two consecutive timeslot 16 words have values of zero in the first four MSB positions (OOOOxxxx) C RCR.2 Frame Resync Criteria

0= Utilize only fixed resync criteria l=Resync if fixed criteria met and/or if bit 2 in timeslot 0 of non-align frames is received in error on 3 consecutive occasions.

SYNCE RCR.1 Sync Enable

If clear, the synchronizer will automatically begin resync if error criteria are met. If high, no auto resync occurs. RESYNC RCR.0 Resync

When toggled low to high, the receive synchronizer will initiate immediately. The bit must be cleared, then set again for subsequent resyncs.

CEPT FRAME STRUCTURE:

The CEPT frame is made up of 32 8-bit channels (timeslots) numbered from 0 to 31. The frame ahgnment signal in bit positions 2 thru 8 of timeslot 0 of every other frame is independent of the various multiframe modes described below. Outputs TAF and RAF indicate frame which contain the ahgnment signal. Timeslot 0 of frames not containing the frame ahgnment signal is used for alarm and national data.

CAS SIGNALING:

CEPT networks support Channel Associated Signalling (CAS) or Common Channel Signalling (CCS). These signalling modes are independently selectable for transmit and receive sides.

CAS (selected when TCR=5=0 and/or when RCR.5=0) is a bit oriented signalling technique which utilizes a 16 frame multiframe. The multiframe ahgnment signal (0-hex), extra and alarm bits occupy timeslot 16 of frame 0. Timeslot 16 of the remaining 15 frames is reserved for channel signalling data. Four signalling bits (A,B,C and D) are transmitted once per multiframe as shown in Figure 7, Input TMSYNC establishes the transmitted CAS multiframe position. Signalling data may be sourced from input TSD (TCR.6=1) or multiplexed in TSER (TCR.6=0).

CCS STGNAT I.TNG:

CCS (selected when TCR.5=1 and/or when RCR.1=1) utilizes all bit positions of timeslot 16 in every frame for "message oriented" signalling data transmission. In CCS mode one can use either timeslot 16 or any one of the other 30 data channels for message oriented signalling. The CCS mode has no multiframe structure and the insertion of CAS multiframe ahgnment, distant multiframe alarm and/or extra bits into timeslot 16 is disabled. TSER is the source of timeslot 16 data.

CRC4 CODING:

The need for enhanced error monitoring capability and additional protection against emulators of the frame ahgnment word has led to the development of a cyclic redundancy check (CRC) procedure. When enabled via CCR.2 and/or CCR3, CRC4 coding replaces the international bit positions in frames 1 thru 12 and 14 with a CRC4 multiframe ahgnment pattern and associated checksum words. The CRC4 multiframe must begin with a frame containing the frame ahgnment signal (CCR.6=0). A rising edge at TMSYNCH establishes the CRC4 multiframe ahgnment (TMSYNC will also estabhsh outgoing CAS multiframe ahgnment in enabled via TCR.5).

Incoming CRC4 multiframe ahgnment is indicated by RCSYNC. Detected CRC4 checksum errors are reported at output RFER and logged in the CECR.

RECEIVE SYNCHRONIZER:

The fixed characteristics of the receive synchronizer may be modified by use of programmable characteristics resident in the RCR and CCR.

Sync criteria must be met before synchronization is declared. Resynch criteria establish error occurrences which will cause an auto-resynch event when enabled. (RCR.1=0).

The receive synchronizer searches for the frame ahgnment pattern first. Once identified, the output timing set associated with the framing pattern (all outputs except RCSYNC) is updated to that new ahgnment. If enabled, the synchronizer then begins CAS and/or CRC4 multiframe search, outputs RMSYNC and/or RCSYNC are then updated. Output RLOS is held high during the entire resynch process, then transitions low after the last output timing update indicating resynch is complete.

FIXED FRAME SYNCH CRITERIA:

Vahd frame synch is assumed when the correct frame ahgnment signal is present in frame N and frame N+2 and not present in frame N+l (Bit

2 of Timeslot 0 of Frame N+l is also checked for "1"). CAS and/or CRC4 multiframe ahgnment search is initiated when the frame search is complete if enabled via RCR.5 and/or CCR.2.

FIXED CAS MULTIFRAME SYNC CRITERIA:

CAS multiframe sync is declared when the multiframe ahgnment pattern is properly detected and timeslot 16 of the previous frame contains code other than zeros. If no vahd pattern can be found in 12 to 14 milliseconds, frame search is restarted.

FIXED CRC4 MULTIFRAME SYNC CRITERIA:

CRC4 multiframe sync is declared if at least two vahd CRC4 multiframe ahgnment signals are found within 12 to 14 milliseconds after frame ahgnment is completed. If not found within 12 to 14 milliseconds, frame search is restarted. The search for the multiframe ahgnment signal is preformed in timeslot 0 of frames not containing the frame ahgnment signal.

FIXED FRAME RESYNC CRITERIA: When enabled via RCR.1, the device will automatically initiate frame search whenever two consecutive CAS multiframe ahgnment words are received in, error.

FIXED CRC4 MULTIFRAME RESYNC CRITERIA:

When enabled via RCR.1, the device will automatically initiate frame search whenever 64 or fewer individual CRC4 bits of the last 1024 CRC4 words are received without error. Even when the incoming CRC4 code words are random in data, the probability that 64 bits are good out of 1024 words (4096 bits) is almost 100%. The threshold for the CRC4 Multiframe Resync Criteria is chosen such that under most circumstances it will not be triggered.

If the chip of the presently preferred embodiment is used with a processor then the user may choose his own threshold by using the on- chip CRC4 Error Count Register (CECR) that can be only one possible CRC4 word error in 1 ms, the counter can be used to monitor errors for a 255 ms period before saturation. This period can be extended by reading the CECR every 200 ms, clearing it, and accumulating the error count in a host microcontroller. The result is with five 'reads," a one second monitoring period can be established.

For example, a threshold of 915 CRC4 errors in a one second monitoring period can be set this way. The re-synch process can be manually initiated using bit position 0 in the Receive Control Register (RCR.0).

For hardware mode applications of the chip of the presently preferred embodiment, the RFER pin may be used with RCSYNC pin to demultiplex the CRC4 word errors. Errors are then counted externally. The re-[synch process can be manually initiated using the Reset pin.

TTNR; TRANSMIT INTERNATIONAL AND NATIONAL REGISTER SYMBOL POSITION NAME AND DESCRIPTION INB TINR.7 International Bit Inserted into the outgoing data stream when

TCR.4=1. TINR.6 Reserved, must be 0 for proper operation.

TRA TINR.5 Transmit Remote Alarm.

0=Normal operation; bit 3 of timeslot 0 in non- ahgnment frames clear.

1= Alarm condition; bit 3 of timeslot 0 in non- align frames set. NB4 TINR.4 Transmit National Bits.

NB5 TINR.3

Inserted into the outgoing data stream at TPOS and TNEG when TCR.3=

TRANSMIT INTERNATIONAL AND NATIONAL DATA:

Bit 1 of timeslot 0 in all frames is known at the international bit. When TCR.4=1, the transmitted international bit is sourced from TINR.7. When TCR.4=0, the transmitted international bit is sampled at TIND during the first bit period of each frame. The international bit positions in all outgoing frames except 13 and 15 are replaced by CRC4 codewords and the CRC4 multiframe ahgnment signal when CCR.3=1.

Bits 4 thru 8 of timeslot 0 in non-align frames are reserved for national use. When TCR.3=0, the transmitted national bits are sourced from registers locations TINR.4 thru TINR.0. If TCR.3=0, the national bits are sampled at TIND during bit times 4 thru 8 of timeslot 0 in non- align frames.

Reserved bit positions in the TINR must be set to 0 when written; those bits may be 0 or 1 when read.

TXR: TRANSMIT EXTRA REGISTER

SYMBOL POSITION NAME AND DESCRIPTION

Reserved, must be 0 for proper operation.

Reserved, must be 0 for proper operation. eserved, must be 0 for proper operation. eserved, must be 0 for proper operation.

Extra Bit 1

Transmit Distant Multiframe Alarm 0=Normal operation; bit 6 of timeslot 16 in frame 0 clear 1= Alarm condition; bit 6 of timeslot 16 in frame

O set XB2 TXR.1 Extra Bit 2

XB3 TXR.0 Extra Bit 3 TRANSMIT EXTRA DATA:

In the CAS mode, timeslot 16 of frame 0 contains the multiframe ahgnment pattern, extra bits and the distant multiframe alarm. When CAS is enabled (TCR.5=0), the extra bits are sourced from TXR.0, TXR.1 and TXR.3 (TCR.2=1)1 or the extra bits are sampled externally at TXD during the extra bit time (TCR.2=0). The extra bits, ahgnment pattern and alarm signal are not utilized in the CCS mode (TCR.5=1), input TSER "overwrites" all timeslot 16 bit positions.

TTR1-TIR4: TRANSMIT IDLE REGISTERS SYMBOL POSITION NAME AND DESCRIPTION

TS31 TIR4.7 Transmit Idle Registers.

TSO TIR1.0 Each of these bit positions represent a timeslot in the outgoing stream at

TPOS and TNEG; when set the contents of that timeslot are forced to idle code (11010101). NOTE: TSO and TS16 are not affected by the idle register.

TRANSMIT TIMING:

A low-high transition at TMSYNC once per multiframe (eveiy 2 milliseconds) or at a multiple of the multiframe rate estabhshes outgoing

CAS and/or CRC4 multiframe ahgnment. Output TMO indicates that ahgnment. A low-high transition at TFSYNC at the frame rate (125 us.) or at a multiple of the frame rate establishes the outgoing frame position.

Output TAF indicates that ahgnment. TMSYNC and/or TFSYNC may be tied low by the user, in which case the arbitrary frame and multiframe ahgnment established by the device will be indicated at TMO and TAF.

Output TAF also indicates frames containing the frame ahgnment signal. Those frames may be "even or odd" numbering frames of the outgoing CAS multiframe (CCR.6).

RECEIVE SIGNALING: Receive signalling data is available at two outputs: RSER and RSD. RSER outputs the signalling data in timeslot 16 at RSER. The signalling data is also extracted from timeslot 16 and presented at RSD during appropriate timeslots. This "channel associated" signalling simplifies CAS system design.

RCR: RECEIVE STATUS REGISTER

SYMBOL POSITION NAME AND DESCRIPTION

RRA RSR.7 Receive Remote Alarm. Set when bit 3 of timeslot 0 in nonahgn frames is set for three consecutive non-align frames.

RDMA RSR.6 Receive Distant Multiframe Alarm. Set when bit 6 of timeslot 165 in frame 0 set for three consecutive multiframes.

RSA1 RSR.5 Receive Signalling All "Is". Set when contents of timeslot 16 have been all "Is" for two consecutive frames.

RUA1 RSR.4 Receive Unframed All "Is". Set when <3 bit positions of the last align and non¬ ahgn frames received have been 0. FSERR RSR.3 Frame Resync Criteria Met Set when the

Frame Error Criteria is met, also the

Frame Resynch is initiated if RCR.1=0.

MFSERR RSR.2 CAS Multiframe Resync Criteria Met Set whyen the CAS multiframe error criteria is met, also the

Frame Resync is initiated if RCR.1=0.

RLOS RSR.1 Receive Loss of Sync Set when resync is in progress.

ECS RSR.0 Error Count Saturation. Set when any of the on-chip counters at FECR, CECR or BVCR saturates.

NOTES: 1. When in the CCS mode, the RDMA pin have no significance. It will be set when bit 6 of Timeslot 16 in Frame 0 is set for three consecutive multiframes in either CAS or CCS mode.

RIMR: RECEIVE INTERRUPT MASK REGISTER SYMBOL POSITION NAME AND DESCRIPTION

RRA RIMR.7 Receive Remote Alarm

0=lnterrupt enabled l=Interrupt masked

RDMA RIMR.6 Receive Distant Multiframe Alarm. l=Interruρt enabled

0=lnterrupt masked

RSA1 RIMR.5 Receive Signalling All "Is." l=Interrupt enabled

0=lnterrupt masked RUA1 RIMR.4 Receive Unframed All "Is".

1= Interrupt enabled

0=lnterrupt masked

FSERR RIMR.3 Frame Resync Criteria Met l=Interrupt enabled

0=lnterrupt masked

MFSERR RIMR.2 CAS Multiframe Resync Criteria Met l=Interrupt enabled

0=lnterrupt masked

RLOS RIMR.1 Receive Loss of Sync l=Interrupt enabled

0=lnterrupt masked

ECS RIMR.0 Error Count Saturation. l=Interrupt enabled

0=lnterrupt masked

ALARM REPORTING AND INTERRUPT SERVICING: Alarm and error conditions are reported at outputs and the RSR.

Use of the RSR and error count registers simplifies system error monitoring. The RSR may be read in one of two ways: a burst read does not disturb the RSR contents, a direct read will clear all bits set in the RSR unless the alarm condition which set them is still active.

Interrupts are enabled via the RIMR and are generated whenever an alarm or error condition sets an RSR bit. The host controller must service the transceiver in order to clear an interrupt condition. Clearing the appropriate RIMR bit will unconditionally clear an interrupt.

BVCR: BIPOLAR VIOLATION COUNT REGISTER SYMBOL POSITION NAME AND DESCRIPTION

BVD7 BVCR.7 MSB of bipolar violation count.

BVDO BVCR.0 LSB of bipolar violation count.

CECR: CRC4 ERROR COUNT REGISTER SYMBOL POSITION NAME AND DESCRIPTION

CRC7 BVCR.7 MSB of CRC4 Error Count.

CRCO BVCR.0 LSB of CRC4 Error Count.

FECR: FRAME ERROR COUNT REGISTER SYMBOL POSITION NAME AND DESCRIPTION FE7 FECR.7 MSB of frame error count.

FE0 FECR.0 LSB of frame error count.

ERROR LOGGING:

The BVCR, CECR and FECR contain eight bit binary up counters which increment on individual bipolar violations, CRC4 code word errors (when CCR.2-1), and word errors in the frame ahgnment signal. Each counter saturates at 255. Once saturated, each following error occupance will generate an interrupt (RIMR.0=1) until the register is reprogrammed to a value other than FF (hex). Presetting the registers allows the user to establish specific error count thresholds; the counter will count "up" to saturation from the preset value. The BVCR increments at all times (regardless of synch status). CECR and FECR increments are disabled whenever resync is in progress (RLOS high).

ALARM OUTPUTS: Alarm conditions are also reported real time at alarm outputs. These outputs may be used with off-chip logic to complement the on-chip error reporting capability of the chip of the presently preferred embodiment. In the hardware mode, they are the only alarm reporting means available.

RLOS: The RLOS output indicates the status of the receive synchronizer.

When high, frame, CAS multiframe and/or CRC4 multiframe synchronization is in progress. A high-low transition indicates resync is complete. The RLOS bit (RSR.1) is a "latched" version of the RLOS output.

RRA:

The remote alarm output transitions high when a remote alarm is detected. A high-low transition indicates the alarm condition has been cleared. The alarm condition is defined as bit 3 of timeslot 0 set for three consecutive non-ahgn frames. The alarm state is cleared when bit 3 has been clear for three consecutive non-ahgn frames. The RRA bit (RSR.7) is a"latched" version of the RRA output.

RBV:

RBV outputs one RCLK pulse when the accused bit emerges at RSER. RBV will return low when RCLK goes low, and RBV pin Bipolar violations are logged in the BVCR. The RBV pin provides a pulse for every violation which can be counted externally.

RDMA:

RDMA transitions high when bit 6 of timeslot 16 in frame 0 is set for three consecutive occasions and returns low when the bit is clear for three consecutive occasions. The RDMA bit (RSR.6) is a "latched" version of the RDMA output.

RCL:

Transitions high after 32 consecutive "0s" appear at RPOS and RNEG, goes low at next 1 occurrence.

RFER:

The RFER output transitions high when received frame ahgnment, CAS multiframe ahgnment and/or CRC4 code words are in error. The FECR and CECR log error events reported at this output. FECR logs only the Frame Ahgnment errors. CECR logs CRC4 code word errors. To complement the on-chip error logging capabilities of the chip of the presently preferred embodiment, the system designer may use off- chip logic gated by receive side outputs RCHCLK, RAF, RSTS and RCSYNC to demux error states present at RFER.

RESET:

A high-low transition on RST clears all internal registers except the three error counters: a resync is initiated until RST returns high. RST must be held low on system power-up and when switching to/from the hardware mode. Following reset, the host processor should update all on- chip registers to estabhsh desired operating modes.

HARDWARE MODE:

An on-chip hardware control mode simplifies preliminary system prototyping and serves apphcations which do not require the features of the serial port. Tying SPS low disables the serial port, clears all internal registers locations except those shown below and redefines pins 14 thru 18 as mode control inputs. The mode control inputs establish device operational characteristics as shown in Table 8. The hardware mode simplifies device retrofit into existing apphcations where control interfaces are designed with discrete logic.

CRC4 Generation and Check The presently preferred embodiment also contains innovative features relating to the cyclic redundancy check (CRC) calculations. The protocols for CRC calculation are defined by the CEPT standard (and may be altered as the standard is modified in this respect). Normally the CEPT standard inserts four CRC checkbits in each frame, at predefined bit positions. These bits correspond to the CRC calculation for the preceding frame. However, one of the predefined positions is very early in the frame, and this creates a difficulty.

Part of the CRC definition, in the protocol, is that the CRC is to be calculated as if the CRC bits from the previous frame had been zero.

Therefore, to activate the CRC generation hardware 702, a long shift operation is commonly used to stuff zeroes into the appropriate positions, as shown in Figure 7D.

However, in this innovative teaching, an architecture like that of Figure 7C is used instead. An added gate permits the current-frame CRC bit values to be corrected, by appropriate offsetting the CRC values from the previous frame. Thus, it is not necessary to stuff zeroes into the bit positions before starting the CRC generation.

Figure 7A is a detailed circuit diagram of the CRC encoding logic, in the presently preferred embodiment. Figure 7B is a detailed circuit diagram of the CRC decoding logic, in the presently preferred embodiment.

Further Modifications and Variations

It will be recognized by those skilled in the art that the innovative concepts disclosed in the present apphcation can be apphed in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.

Most preferably, the integrated circuit of this embodiment is further connected to control additional integrated circuits which contain the analog circuitry necessary for the send and receive functions, and is further connected to be controlled by a microprocessor. However, it will be recognized by those skilled in the art that this division of functions onto chips could be changed, while still making use of the disclosed teachings. As will be recognized by those skilled in the art, the innovative concepts described in the present apphcation can be modified and varied over a tremendous range of apphcations, and accordingly their scope is not limited except by the allowed claims.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit, for transmit and receive interface to a communications channel under control of a programmable processor, comprising: at least a first and a second subarray of multiport memory cells; serial port control logic, connected to send status signals and receive control signals over an off-chip serial interface connection in accordance with a first clock signal, and comprising serial/parallel conversion logic; transmit control logic, connected to provide signals to control transmit functions in accordance with a second clock which is asynchronous to said first clock; and receive control logic, connected to provide signals to control receive functions in accordance with a third clock which is asynchronous to said first clock and to said second clock; wherein said transmit control logic is connected to read control signals from said first subarray, with a timing determined by said second clock, and to be controlled thereby in providing said signals to control transmit functions; and wherein said receive control logic is connected to write status signals to said second subarray, with a timing determined by said third clock; and wherein said serial port control logic is connected to access said first subarray, through said serial/parallel conversion logic, in accordance with said first clock, but only at times when said second clock indicates that said transmit control logic is not accessing said first subarray; and wherein said serial port control logic is connected to access said second subarray, through said serial/parallel conversion logic, in accordance with said first clock, but only at times when said third clock indicates that said receive control logic is not accessing said first subarray; whereby a programmable processor can control said transmit control logic, and thereby control transmit functions, by writing control signals into said first subarray, through said serial interface connection and said serial port control logic, and can monitor the status information generated by said receive control logic, by reading status signals from said second subarray, through said serial interface connection and said serial port control logic.

2. The integrated circuit of Claim 1, wherein each of said multiport memory cells is dual-ported.

3. The integrated circuit of Claim 1, wherein said control signals include signals which control error logging.

4. The integrated circuit of Claim 1, wherein said control signals include signals which control per-channel code manipulation.

5. The integrated circuit of Claim 1, wherein said first subarray includes exactly seven of said memory cells.

6. The integrated circuit of Claim 1, wherein said second subarray includes exactly seven of said memory cells.

7. The integrated circuit of Claim 1, wherein off-chip serial interface connection consists essentially of a serial-data-in connection, a serial-data- out connection, a connection for said first clock signal, and a chip-select connection.

8. The integrated circuit of Claim 1, wherein said transmit control logic is connected to access said first subarray only when said second clock is high, and said serial port control logic is connected to access said first subarray only when said second clock is low.

9. The integrated circuit of Claim 1, wherein said receive control logic is connected to access said second subarray only when said third clock is high, and said serial port control logic is connected to access said second subarray only when said third clock is low.

10. The integrated circuit of Claim 1, wherein said transmit control logic, connected to provide said control signals off-chip.

11. The integrated circuit of Claim 1, wherein said transmit control logic, connected to conttol transmit functions in accordance with the CEPT protocol.

12. The integrated circuit of Claim 1, wherein said receive control logic is connected to provide said control signals off-chip.

13. The integrated circuit of Claim 1, wherein said receive control logic is connected to control receive functions in accordance with the CEPT protocol.

14. The integrated circuit of Claim 1, wherein said second clock and said third clock both have frequencies in the neighborhood of 2.048 MHz.

15. The integrated circuit of Claim 1, wherein said first clock runs much more slowly than said second clock and said third clock.

16. The integrated circuit of Claim 1, wherein said first clock has a frequency in the neighborhood of 100 Hz, and said second clock and said third clock both have frequencies in the neighborhood of 2.048 MHz.