WO1990015412A1

WO1990015412A1 - A high reliability non-volatile memory circuit and structure

Info

Publication number: WO1990015412A1
Application number: PCT/US1990/003042
Authority: WO
Inventors: Joseph G. Nolan
Original assignee: Sierra Semiconductor Corporation
Priority date: 1989-06-08
Filing date: 1990-05-31
Publication date: 1990-12-13

Abstract

A high reliability, high density, non-volatile memory circuit (10) is disclosed. The circuit comprises a storage cell (19) which has a first MOS enhancement type transistor (12), a second MOS enhancement type transistor (14), a tunnel terminal device (26) and a capacitor (28). The first MOS enhancement type transistor (12) has a source (18), a drain (15) and a gate (16). The second MOS enhancement type transistor (14) has its drain (20) connected to the source (18) of the first MOS transistor (12). The tunnel device (26) has two terminals and has one of the terminals connected to the gate (22) of the second MOS transistor (14), and the other terminal connected to the source (24) of the second MOS transistor (14). A capacitor (28) is coupled to the gate (22) of the second MOS transistor (14). A third MOS transistor (30) of the depletion type is connected to the storage cell (19). The drain (32) of the third MOS transistor (30) is connected to the source (24) of the second MOS transistor (14). The memory circuit (10) can be used in a redundant mode for high reliability and can be densely manufactured on a semiconductive substrate (40).

Description

A HIGH RELIABILITY NON-VOLATILE MEMORY CIRCUIT AND STRUCTURE

Technical Field

The present invention relates to a non-volatile memory circuit and a structure made thereby which is of high reliability. More particularly, the present invention relates to a non-volatile, high reliability memory circuit which can be densely fabricated.

Background of the Invention

Electrically alterable, non-volatile memory devices are well known in the art. One example is the Electrically Erasable Programmable Read-Only Memory (EEPROM) . An EEPROM transistor is a three terminal device, having a gate, a drain, and a source. The EEPROM transistor also has a floating gate. The floating gate has a portion of it insulated from the semiconduσtive substrate by a layer of dielectric less than approximately 100 angstroms in thickness and is generally disposed over the drain region of the transistor. Electrons are placed and removed from the floating gate through the thin dielectric by the mechanism of Fowler-Nordheim tunnelling. See, for example, U.S. Patent Nos. 4,203,158; 4,132,904; 4,477,825 and 4,274,012.

One of the problems of an EEPROM transistor is that it is subject to failure by the rupturing of the oxide layer between the floating gate and the drain after a certain number of charged injection and removal cycles. Further, because of electron trapping in the thin tunnel oxide region between the floating gate and the drain, there is also the possibility of low endurance. The problem of rupturing of the oxide layer between the floating gate and the drain results in the cell being inoperative in an ambiguous conduction or non-conduction mode. Another problem of a prior art EEPROM device is that it is subject to failure of long term data retention. This is often the result of leakage of the charge stored on the floating gate to the gate. Such a failure also results in an unpredictable conduction or non-conduction mode. U.S. Patent No. 4,780,750 assigned to the present assignee, discloses a high reliability electrically alterable non-volatile memory cell in which the failure of a tunnel device or a data retention failure always results in a non-conduction mode. Thus, since the result of failure can be predicted, a parallel redundancy circuit can be implemented so that the failure in the predicted manner does not interfere with data retention or the ability to reprogram the redundant circuit. However, the circuit disclosed in U.S. Patent No. 4,780,750 occupies a considerable amount of silicon area and thus is best suited for the implementation of a non-volatile flip flop or a low bit count non-volatile memory.

Summary of the Invention

In the present invention, a high density, high reliability electrically alterable, non-volatile memory cell is disclosed. The circuit comprises a storage cell which has a first MOS transistor with a source, a drain, and a gate and is of the enhancement type in the absence of any charge on the gate. The storage cell also comprises a second MOS transistor also having a source, a drain, and a gate. The second MOS transistor is also of the enhancement type in the absence of any charge on the gate with the drain of the second MOS transistor connected to the source of the first MOS transistor. Finally, the storage cell has a tunnel device and a capacitive means. The tunnel device has two terminals. One of the terminals of the tunnel device is connected to the gate of the second MOS transistor with the other one of the terminals of the tunnel device being connected to the source of the second MOS transistor. The capacitance means is capacitively coupled to the gate of the second MOS transistor. A third MOS transistor having a source, a drain and a gate has its drain connected to the storage cell at the source of the second MOS transistor.

Brief Description of the Drawings

Figure la is one schematic representation of the circuit of the electrically alterable non-volatile memory cell of the present invention. Figure lb is another representation. Figure 2a is a schematic circuit diagram of one embodiment of the electrically alterable non-volatile memory cell of Figure 1 with redundant storage cells to provide high reliability.

Figure 2b is a schematic circuit diagram of another embodiment of the electrically alterable non¬ volatile memory cell of Figure 1 with redundant storage cells to provide high reliability.

Figure 3 is a cross sectional area of a structure implementing the circuit of the present invention shown in Figure 1.

Detailed Description of the Drawings

Referring to Figure la there is shown one schematic representation of a non-volatile memory circuit 10 of the present invention. The circuit 10 comprises a storage cell 19. The storage cell 19 has a first MOS transistor 12 having a drain 15, a gate 16, and a source 18 and is of the enhancement type in the absence of any charge on the gate 16.

The first storage cell 19 also comprises a second MOS transistor 14 having a drain 20, a gate 22, and a source 24. The drain 20 of the second MOS transistor 14 is connected to the source 18 of the first MOS transistor 12. A tunnel device 26 has two terminals. One of the terminals of the tunnel device 26 is connected to the gate 22 of the second MOS transistor 14. The other terminal of the tunnel device 26 is connected to the source 24 of the second MOS transistor 14. A capacitor 28 is capacitively coupled to the gate 22 of the second MOS transistor 14.

A third MOS transistor 30 which has a drain 32, a gate 34, and a source 36 is connected to the storage cell 19. The drain 32 of the third MOS transistor 30 is connected to the source 24 of the second transistor 14.

In the preferred embodiment, the third MOS transistor 30 is of the depletion type. Further, each of the first, second and third MOS transistors, 12, 14 and 30 respectively, is of the N channel type. The first MOS transistor 12 is of a low voltage enhancement type, typically on the order of five (5) volts. The tunnel terminal device 26 is of a Fowler-Nordheim tunnel device. Finally, the third MOS transistor 30 is of high voltage depletion type transistor, typically on the order of 15 volts.

In the operation of the circuit 10 of the present invention, the following electrical voltages are applied to the respective nodes A, B, C, D and E. "rite prase Fsad

A Float Float ^vSense

B Don't Care Don't Care VDD

C vss VPP VSS D VPP Don't Care VDD

E VPP vss VSS

An alternate schematic representation of the circuit 10 of the present invention is shown in Figure lb. The tunnel terminal device 26 and the capacitive couple 28 and the second MOS transistor 14 are all shown as a single transistor 14 with a floating gate 25.

The circuit 10 is of high reliability, because in the event the tunnel terminal device 26 fails or in the event the floating gate 25 leaks, the circuit 10 would remain in a non-conducting state.

In the event the tunnel terminal device 26 ruptures and a short is presented across the gate 22 and the source 24, because the second MOS transistor 14 is of the enhancement type, the second MOS transistor 14 is rendered inoperative in the open circuit mode. It would be as if there were an open circuit between the drain 20 and the source 24 of the second MOS transistor 14. Thus, the second MOS transistor 14 would remain inoperative in the open circuit mode. The advantage of the second MOS transistor remaining in a non-conducting or open circuit mode in the event of catastrophic failure will be discussed hereinafter. In the event the floating gate 25 leaks, charges would leak through the capacitor 28. Thus The floating gate 25 would reach the same potential as the potential at C. During both read and write operation, the voltage potential at node C is at VSS. Therefore, the voltage potential at the gate is also VSS and transistor 14 is in a non-conducting state.

A further advantage of the memory circuit 10 of the present invention is that with the third MOS transistor 30 being of the depletion type, during programming or the write condition, when voltage Vpp is applied to nodes D and E, all of the V_pp voltage potential can reach the tunnel terminal device 26, thereby improving programming margin. With a depletion transistor 30, a higher programming voltage can be applied through the depletion transistor 30 than through an enhancement transistor which could otherwise be connected to the transistor 14.

Finally, as will be shown hereinafter, the advantage of the memory circuit 10 of the present invention is that it occupies less silicon area than the prior art. Thus, it can be constructed in a semiconductive substrate with resulting high density. Referring to Figure 2a there is shown a high reliability non-volatile memory circuit 110 of the present invention. The high reliability non-volatile memory circuit 110 is substantially identical to the non-volatile memory circuit 10 shown in Figure la. A first and second storage cell 19a and 19b respectively are connected together at the source of the second MOS transistor 14. In addition, a single third MOS transistor 30 has a drain 32 connected to the source of the second MOS transistors 14. Nodes Ai and 2 are connected to two separate sense amplifiers during the read operation.

Referring to Figure 2b there is shown another embodiment of a high reliability non-volatile memory circuit 210 of the present invention. The circuit 210 comprises two identical circuits 10 connected in parallel, with the source 36 of the third MOS transistors connected together. The nodes and A2 are connected to two separate sense amplifiers during the read operation. In the operation of the high reliability non¬ volatile memory circuits 110 and 210, electrical charges are stored and removed from the tunnel terminal device 26 in each of the transistors 14, in tandem. In the event there is a catastrophic failure in the tunnel terminal device 26, for example 26a, connected to one of the transistors 14a, the catastrophic failure of the tunnel terminal device 26a would result in an open circuit condition for the MOS transistor 14a associated with that tunnel terminal device 26a. In the event the tunnel terminal device 26a were to fail, the storage cell 19a would remain in the open circuit condition. The storage of charges and the removal thereof from the tunnel terminal device 26b would continue to function, because it is electrically connected to the storage cell 19a in parallel. The operation of the transistor 14b would not be affected by the catastrophic failure of the tunnel terminal device 26a.

Referring to Figure 3 there is shown a structure for implementing the non-volatile memory circuit 10 of the present invention. The structure comprises a substrate 40, typically of semiconductive material such as silicon. Within the substrate 40 and near the surface thereof are a first well 42, second well 44, third well 46 and fourth well 48, each spaced apart and adjacent to one another. The formation of the first, second, third and fourth wells 42, 44, 46 and 48 is well known in the art. Preferably, the wells 42, 44, 46 and 48 are ion implanted with arsenic and phosphorus dopants sufficient to render it N⁺ conductive. Such technigue is well known in the art. Since the wells 42, 44, 46 and 48 are spaced apart from one another, a first channel 50, a second channel 52 and a third channel 54 is formed in the space between the adjacent wells, respectively. Thus, a first channel 50 is formed between the first and second wells 42 and 44. A second channel 52 is formed between the second and third wells 44 and 46 respectively. A third channel 54 is formed between the third and fourth wells 46 and 48 respectively. The first and second channel 50 and 52 are further doped with arsenic and phosphorus dopants such that the channels 50 and 52 are of the enhancement type, in the absence of any charge on the gate formed respectively over those channels. The third channel 54 is doped with arsenic such that it is of a depletion type in the absence of any charge on the gate 72 over the channel 54.

A first insulating layer 56 is formed over the first channel 50. The first insulating layer is made of silicon dioxide and is approximately 400 angstroms in thickness. A first conductive layer 58 is formed over the first insulating layer 56 and is on the order of 4000 angstroms. The first conductive layer 58 forms the gate to the transistor comprising of the first well 42, second well 44, with the first channel 50.

A second insulating layer 60 is formed over the second channel 52 and over a portion of the third well 46, with the layer over the -third well 46 being thinner than the layer over the second channel 52. Typically, the second insulating layer 60 over "the second channel 52 is on the order of 500 angstroms in thickness. The portion of the second insulating layer 60 over the third well 46 is on the order of 100 angstroms and forms the tunnel oxide for the Fowler-Nordheim device as previously discussed. A second conductive layer 62 is formed conformably over the second insulating layer 60. A third insulating layer 64 is formed over the second conductive layer 62. A third conductive layer 68 is formed over the third insulating layer 64.

A fourth insulating layer is formed over the third channel 54. A fourth conductive layer 72 is formed over the fourth insulating layer 70. Each of the first, second, third and fourth insulating layers is made of an insulating material such as silicon dioxide. Each of the first, second, third and fourth conductive layers 58, 62, 68 and 72 respectively is formed of polysilicon which is doped sufficiently to render it conductive.

The structure shown in Figure 3 corresponds to the circuit shown in Figure la or lb in the following manner. The first MOS transistor 12 as shown in Figure la is comprised of the first well 42 being the drain, the gate 16 of the MOS transistor 12 is the first conductive layer 58, and the source 18 of the first MOS transistor 12 is formed by the second well 44. Similarly, the second MOS transistor 14 has its drain 20 corresponding to the second well 44. The gate of the second MOS transistor 14 is that portion of the second conductive layer 62 which is over the second channel 52. The source 24 of the second MOS transistor 14 is the third well 46. The capacitor 28 is formed by the second conductive layer 62 and the third conductive layer 68. The tunnel terminal device 26 is formed by the second conductive layer 62 and the third well 46 in that region where the second conductive layer 62 extends over the third well 46. Finally, the third MOS transistor 30 has its drain 32 corresponding to the third channel 46. The gate 34 of the third MOS transistor 30 is the fourth conductive layer 72. The source of the third MOS transistor 36 is the fourth well 48. As can be seen in Figure 3, with the non-volatile memory circuit 10 of the present invention a structure having great density can be formed.

Claims

WHAT IS CLAIMED IS:

1. A high reliability non-volatile memory circuit for storing charges therein comprising: A storage cell comprising: a first MOS transistor having a source, a drain, and a gate, and is of the enhancement type in the absence of any charge on the gate; a second MOS transistor having a source, a drain, and a gate, and is of the enhancement type in the absence of any charge on the gate; said drain of said second MOS transistor is connected to the source of the first MOS transistor; a tunnel device having two terminals; one of the terminals of said tunnel device is connected to the gate of said second MOS transistor; the other one of the terminals of said tunnel device is connected to the source of said second MOS transistor; and a capacitance means, capacitively coupled to the gate of the second MOS transistor; and a third MOS transistor having a source, a drain and a gate, said drain of said third MOS transistor is connected to said storage device at the source of the second MOS transistor.

2. The circuit of Claim 1 wherein said third MOS transistor is of the depletion type.

3. The circuit of Claim 2 wherein each MOS transistor is N channel type.

4. The circuit of Claim 1 further comprising a plurality of said storage cells with the source of the second MOS transistor of each storage cell connected to the drain of the third MOS transistor.

5. The circuit of Claim 4 wherein the third MOS transistor of each storage cell is of the depletion type.

6. The circuit of Claim 5 wherein each MOS transistor is N channel type.

7. The circuit of Claim 1 further comprising a plurality of storage cells; a plurality of third MOS transistor, each having a source, a drain and a gate, with the drain of each third MOS transistor connected to a storage cell at the source of the second MOS transistor; and the source of said third MOS transistors are connected together.

8. A semiconductive non-volatile memory structure comprising: a substrate; a first well in said substrate; a second well adjacent to said first well in said substrate, forming a first channel between said first and second wells; a third well adjacent to said second well in said substrate, forming a second channel between said second and third wells; a fourth well adjacent to said third well in said substrate, forming a third channel between said third and fourth wells; a first insulating layer over said first channel; a first conductive layer over said first insulating layer; a second insulating layer over said second channel and over a portion of said third well, with the layer over said third well thinner than the layer over the second channel; a second conductive layer over said second insulating layer; a third insulating layer over said second conductive layer; a third conductive layer over said third insulating layer; a fourth insulating layer over said third channel; and a fourth conductive layer over said fourth insulating layer.

9. The structure of Claim 8 wherein each of the first, second, third and fourth wells is doped to render it N⁺ and each of the first, second and third channels is N type.

10. The structure of Claim 8 wherein each of the first, second, third and fourth insulating layers is silicon dioxide.

11. The structure of Claim 8 wherein each of the first, second, third and fourth conductive layers is polysilicon doped to render it conductive.

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12. The structure of Claim 8 wherein said third channel is doped to render it depletion type.

13. The structure of Claim 8 wherein said first and second channels are doped to render it enhancement type.