WO1991003020A1

WO1991003020A1 - Data processing system and process for controlling it and cpu boards

Info

Publication number: WO1991003020A1
Application number: PCT/DE1990/000643
Authority: WO
Inventors: Thomas Schlage
Original assignee: Digital Equipment Corporation
Priority date: 1989-08-23
Filing date: 1990-08-23
Publication date: 1991-03-07
Also published as: AU6164090A; EP0439591A1; CA2039715A1; JPH06105447B2; JPH04502975A

Abstract

In a data processing system with a central processing unit (CPU), a main store (2) and a system bus (3), which may be connected to the main store (2) may be directly connected to the CPU (1) and there are a first switching unit (5) which controls the connection between the CPU (1) and the main store (2) and a second switching units (5, 7) are so interconnected that only one of them can release the existing connection of the CPU (1) or the system bus (3) to the main store. Here the main store, the first and second circuit and the first and second buffers are fitted on the same board as the CPU (1).

Description

Data processing system and method for its control as well as CPU board

The invention relates to a data processing system and a method for its control, the data processing system having a central computer unit (CPU), a main memory and a system bus which can be connected to the main memory and other functional units. The invention also relates to a CPU board for a data processing system, in which the CPU is arranged on a separate board.

The CPU, the main memory and the input / output units (I / O units) or their controllers are usually each on a board, which is also called a board or card. All the functional units connected to the system bus are controlled centrally by the central computer unit (CPU), for example a microprocessor. Communication between the functional units and the CPU always runs via the system bus. If, for example, an I / O unit wants to perform a data transfer with respect to the main memory, ie wants to read data into the main memory or read data from the main memory, the I / O unit sends a signal to the system bus, on the basis of which the CPU for is "stopped" for a short time, during which the I / O unit is given direct access, which is also referred to as DMA (Direct Memory Access), to the main memory.

Since there is a large number of direct accesses to the main memory, in particular during peak load operation, there are traffic jams and long waiting times, since the system bus is standardized in its time behavior and therefore cannot be accelerated at will, especially since all plug-in cards on the system bus are at specific timings must keep and these can not be changed.

A whole series of techniques are known for processing as many tasks as possible in data processing systems at the same time. So-called cache memories are used, for example, as small, fast buffers, which can be arranged on the same board as the CPU. The CPU reads data from the main memory via the system bus and ^" writes this data to the fast cache memory on the CPU board. If the CPU now wants to access this data again, it must no longer carry out the data transfer from the main memory via the relatively slow system bus, but can directly access the fast cache memory.

Due to the progress of integration technology, it has become possible to arrange the CPü and main memory on one board. However, since communication between the I / O units and the main memory continues to take place via the system bus, this is caused by frequent DMA accesses, i.e. Access by I / O units with direct access to the main memory blocked, so that there are still high waiting times.

In contrast, the object of the invention is to increase the operational behavior of the data processing system in that as many tasks as possible can be processed simultaneously and the waiting times on the system bus are reduced.

This object is achieved in that the main memory can be connected directly to the CPU, a first switching mechanism which controls the connection between the CPU and the main memory, and a second switching mechanism which controls the connection between the system bus and the main memory, wherein the first and the second rear derailleur are connected so that only one of the two Switchgear can release the respective connection of the CPU or the system bus with the main memory.

This makes it possible to selectively access the main memory from the CPU and the system bus, the main memory only having to be blocked for the other side for the period of the actual memory access, but not for the entire access cycle.

The fact that a first buffer, which is controlled by the first switching mechanism, and a second buffer between the system bus and the main memory is provided between the CPU and the main memory, ensures that the data transfer between the CPU and the main memory, on the one hand and the system bus and the main memory on the other hand is done correctly.

The main memory, the first and second switching mechanisms and the first and second buffers are preferably provided on the same board as the CPU.

In a further embodiment of the invention, one or more I / O units without direct memory access are provided, which can be connected directly to the CPU via a CPU bus, the CPU optionally with the main memory or one of the I / O units can be connected without direct memory access. This makes it possible for the CPU can also access I / O units directly when the system bus is blocking the path between main memory and a DMA unit. A further increase in the performance of the data processing system can thereby be achieved.

The CPU board according to the invention, which is described in claims 7 to 11, can be marketed independently of the data processing system, as long as compatibility with the corresponding data processing system is ensured.

The method according to the invention is described in claims 12 to 16.

An embodiment of the invention is described in more detail with reference to the drawings. Show it:

1 shows a schematic block diagram of a data processing system according to the invention;

Fig. 2 is a flow chart for explaining the operation of a first rear derailleur and

Fig. 3 is a flow chart to explain the operation of a second switching mechanism.

As can be seen from FIG. 1, the data processing system according to the invention has a central computer unit (CPU) 1, a main memory 2 and a system bus 3. The CPU 1 is connected to the main memory 2 via a first buffer 4. The control takes place via a first switching mechanism 5.

The main memory 2 is also connected to the system bus 3 via a buffer 6, the control being carried out via a second switching mechanism 7.

The data processing system according to the invention also has a CPU bus 8, through which the CPU 1 is connected to a number of I / O units without direct access, that is to say I / O units without DMA. The embodiment shown is a register set 9, a boot PROM 10, a setup EEPROM 11 and further serial interfaces 12.

The I / O units 9 to 12 are typical I / O units which are connected to the system bus 3 in the known data processing systems. The register set 9 usually has an interrupt controller, a clock generator and a real-time clock. Boot PROM 10 and set EEPROM 11 contain the functions for starting the system, the configuration data, hardware-related functions, diagnostic programs, ^" self-test programs, etc. ^" in a known manner.

The serial interfaces 12 are, for example eight serial interrupt-lines connected to the Svstemkonsole ^', terminals, printers, modems u. Like. Are connected. Furthermore, a floating point unit (not shown) can be connected to the CPU bus in a known manner.

All of the components shown in FIG. 1 are preferably arranged on the CPU board.

In the following _. the operation of the data processing system according to the invention will now be described.

Due to the possible simultaneity of the accesses of the CPU 1 or of I / O units with direct access (DMA units), the technical implementation requires that they are connected to the system bus in the usual way and for the sake of clarity in FIG. 1 are not shown, via the system bus 3 to the main memory 2, two switching mechanisms which control the time sequences in the respective part.

The first switching mechanism 5 controls all processes close to the CPU, such as accesses by the CPU 1 to the main memory 2 and to the I / O units without DMA, which are identified in FIG. 1 by the reference numerals 9 to 12.

The second switching mechanism 7 controls the processing of the DMA System bus 3 requirements, the actual memory accesses of the DMA units and the CPU 1 accesses to the system bus 3.

The first switching mechanism 5 and the second switching mechanism 7 operate in the so-called handshaking process, whereby mutual locking is ensured when access requirements occur simultaneously.

The mode of operation of the first switching mechanism 5 will now be described in more detail with reference to FIG. 2.

Initially, the first switching mechanism 5 is in the waiting position 100. In step 101, a query is made as to whether the CPU 1 should access main memory 2. If this is not the case, a query is made in step 102 as to whether there is a request for or an interrupt from one of the I / O units identified by reference numerals 9 to 12 in FIG. 1 without DMA. If this is the case, the request or the interrupt is processed in step 103.

If it is determined in step 101 that the main memory 2 is to be accessed, the switching mechanism 5 occupies the main memory 2 in step 104 and emits a corresponding occupancy signal to the switching mechanism 7. If it is determined in step 105 that the main memory 2 is occupied, that is to say an access from a DMA unit via the system bus 3 the main memory 2 is present, the process continues until the main memory 2 is free. After that. The storage action is carried out in step 106, the buffer 4 being controlled accordingly by the switching mechanism 5. After the storage action has ended, the main memory 2 is released again in step 107 and a corresponding release signal is sent from the switching mechanism 5 to the switching mechanism 7.

The mode of operation of the second switching mechanism 7 will now be described in more detail with reference to FIG. 3.

Initially, the second switching mechanism 7 is in the waiting position 200. In step 201, a query is made as to whether there is a request from a DMA unit via the system bus 3. If this is the case, the switching mechanism 7 issues the DMA release to the system bus 3 in step 202. A bidirectional connection is then established between the switching mechanism 7 via the system bus 3 to the DMA unit connected to the system bus 3 and the first part of the bus protocol is processed in step 203. The switching mechanism 7 then occupies the main memory 2 and emits a corresponding occupancy signal to the switching mechanism 5. If it is determined in step 205 that the main memory 2 is occupied, ie there is still access from the CPU 1 to the main memory 2, the system waits until the main memory 2 is free is. The storage action is then carried out in step 206, the buffer 6 being controlled accordingly by the switching mechanism 7.

After the storage action has ended, the main memory 2 is released in step 207 and a corresponding release signal is sent from the switching mechanism 7 to the switching mechanism 5. Then in step 208 the second part of the bus protocol is processed in communication between the switching mechanism 7 and the DMA unit.

The two high-speed switching devices 5 and 7, which communicate with one another and work in the handshaking process, therefore decide in each case who can access the main memory 2.

2 and 3 that the main memory 2 is only occupied during the absolutely necessary period. This is identified by the dashed lines in FIG. 2 with the reference number 110 and in FIG. 3 with the reference number 210.

During the remaining time, ie the remaining cycle time of a DMA access or a CPU access to the main memory or also during a CPU access to the I / O units identified by the reference numerals 9 to 12 without DMA access the main memory 2 released and for a new request.

With the embodiment according to the invention it is achieved that the main memory is not occupied during the entire standardized standard cycle time of a DMA access, which runs from steps 201 to 208 in FIG. 3, but only during the absolutely necessary time, which results from steps 204 to 207 in Fig. 3 results. The time referred to as idle time (steps 201 to 203 and step 208 in FIG. 3) between memory allocation (steps 204 to 207 in FIG. 35 and the standard cycle time (steps 201 to 208 in FIG. 3) can be used for other purposes are, for example, for an access of the CPU to the main memory, so that the actual memory accesses can be nested in time.

A further increase in system performance can be achieved in that the CPU can process requests from I / O units without DMA access while the main memory is occupied by the system bus, so that true parallel processing is possible.

Claims

1. Data processing system with a central computer unit (CPU), a main memory and a system bus which can be connected to the main memory and various other functional units, characterized in that the main memory (2) can be connected directly to the CPU (1) that a first switching mechanism (5), which controls the connection between the CPU (1) and the main memory (2), and a second switching mechanism (7) are provided, which controls the connection between the system bus (3) and the main memory (2) controls, the first and second switching mechanisms (5, 7) being connected to one another such that only one of the two switching mechanisms can release the respective connection of the CPU (1) or the system bus (3) to the main memory (2) .

2. Data processing system according to claim 1, wherein between the CPU (1) and the main memory (2) a first buffer (4), which is controlled by the first switching mechanism (5), and between the system bus (3) and the main memory (2 ) a second buffer (6) is provided.

3. Data processing system according to one of claims 1 or 2, wherein the main memory (2), the first and second switching mechanisms (5, 7) and the first and second buffers (4, 6) on the same board as the CPU (1) are provided.

4. Data processing system according to one of claims 1 to 3, in which at least one I / O unit (9, 10, 11, 12) without direct memory access (DMA, abbreviation of direct memory access) is provided, via a CPU bus (8) can be directly connected to the CPU (1).

5. Data processing system according to claim 4, in which a series of I / O units (9, 10, 11, 12) without DMA are provided, which can be connected directly to the CPU (1) via the CPU bus (8).

6. Data processing system according to one of claims 1 to 5, in which the CPU (1) with the main memory (2) or one of the I / O units (9, 10, 11, 12) can be connected without DMA.

7. CPU board for a data processing system on which a CPU (1) is arranged, characterized in that there are provided on the CPU board: a main memory (2), a first switching mechanism (5) which establishes the connection between the CPU (1) and the main memory (2) controls, and a second switching mechanism (7) that connects the

Controls system bus (3) and the main memory (2), the first and second switching mechanisms (5, 7) being connected to one another in such a way that only one of the two switching mechanisms has the respective connection of the CPU (1) or the system bus (3) release the main memory (2).

8. CPU board according to claim 7, on the between the CPU (1) and the main memory (2), a first buffer (4), which is controlled by the first switching mechanism (5), and between the system bus (3) and the main memory (2) a second buffer (6) is provided.

9. CPU board according to one of claims 7 or 8, on which at least one I / O unit (9, 10, 11, 12) without DMA is provided, which via a CPU bus (8) with the CPU (1) is directly connectable.

10. CPU board according to one of claims 7 to 9, on which a number of I / O units (9, 10, 11, 12) are provided without DMA, which are connected via the CPU bus (8) to the CPU (1) can be connected directly.

11. CPU board according to one of claims 7 to 10, on which the CPU (1) optionally with the main memory (2) or one of the I / O units (9, 10, 11, 12) can be connected without DMA.

12. Method for controlling a data processing system with a central computer unit (CPU), a

Main memory, a system bus which is connected to the main memory and other functional units, characterized in that the CPU is connected directly to the main memory, the connection being controlled by a first switching mechanism, the connection between the system bus and the main memory by a second Switchgear is controlled and the first and second switchgear are connected to each other so that only one of the two switchgear the respective

Enables connection of the CPU or the system bus to the main memory.

13. The method of claim 12, wherein a first buffer, which is controlled by the first switching mechanism, and a second buffer between the system bus and the main memory are arranged between the CPU and the main memory.

14. The method according to any one of claims 12 or 13, wherein the CPU is connected via its own bus to an I / O unit without direct memory access.

15. The method according to any one of claims 12 to 14, wherein the CPU is connected to a series of I / O units without direct memory access.

16. The method according to any one of claims 12 to 14, wherein the CPU is optionally connected to an I / O unit without DMA or to the main memory, the control being carried out by the first switching mechanism.