WO1991003912A1

WO1991003912A1 - Digital acoustic switch

Info

Publication number: WO1991003912A1
Application number: PCT/US1989/003815
Authority: WO
Inventors: Carlile R. Stevens
Original assignee: Joseph Enterprises, Inc.
Priority date: 1989-09-01
Filing date: 1989-09-01
Publication date: 1991-03-21

Abstract

The present invention provides a circuit for turning on or off line power to lights or other appliances in response to two closely spaced sounds, such as hand-claps. A microphone (Mic 1) provides the sounds to a filter (U1B) which eliminates sounds which are not loud or sharp like a hand-clap. The output of the filter is used to activate a counter (U3), which counts from the line frequency of the AC signal powering the switch. The filter output is also provided to a gate (U2B) which is enabled when the counter reaches a specified count. Thus, only the second clap sound will activate the gate when the counter achieves the proper number, which forms a clapping window which will be present between one-half and one and one-half seconds after the first sound is detected. The output is then provided to a latch (U4R) which activates a triac (TR1) to provide line power to the load.

Description

DIGITAL ACOUSTIC SWITCH

BACKGROUND Acoustic switches are used to replace manually operated on-off switches such as light switches or switches for household appliances. Acoustic switches are triggered by the presence or absence of sound of a particular type. For instance, U.S. Patent No. 3,949,366 to Spillar et al., discloses a system for turning on and off appliances which is activated by a fixed frequency of sound generated by a transmitter. Another system shown in U.S. Patent No. 4,408,308 to Smith et al., shows a switch which automatically turns off in the event that no sound is detected for a fixed period of time. This type of switch is useful for turning off lights or other appliances when people leave a room.

SUMMARY OF THE INVENTION The present invention provides a circuit for turning on or off line power to lights or other appliances in response to two closely spaced sounds, such as hand-claps. A microphone provides the sounds to a filter which eliminates sounds which are not loud or sharp like a hand-clap. The output of the filter is used to activate a counter, which counts from the line frequency of the AC signal powering the switch. The filter output is also provided to a gate which is enabled when the counter reaches a specified count. Thus, only the second clap sound will activate the gate when the counter achieves the proper number, which forms a clapping window which will be present between one-half and one and one-half seconds after the first sound is detected. The output is then provided to a latch which activates a triac to provide line power to the load. A second latch is preferably used to synchronize the signal from a first latch with the zero level of the line frequency. This is done in order to prevent a high current from being instantly switched across the load, thus risking the burnout of an incandescent filament. Preferably, the next most significant counter output past the output used for activating the triac is fed back to gate the clock input of the counter so that, after a period of time for the clapping window, the input to the counter is disabled. An RC circuit is used at the output of the activating latch to prevent it from reswitching for a period of approximately 3 seconds. This RC circuit prevents a user from inadvertently turning off a fluorescent light with a second set of claps when the light is not yet warmed up enough to turn on.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a digital acoustic switch control circuit according to the present invention; and

Fig. 2 is a timing diagram illustrating the timing of the signals of the circuit of Fig. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the schematic diagram of Fig. 1, the 120 volts, 60/50^' Hz line power enters at the right. The neutral side of the line is connected directly to the load as required by UL. The hot or line side is connected via triac TR1 to the other side of the load, thus allowing the triac to switch the hot or line to the load, on and off. The line side of the triac serves as the positive voltage or VDD for the logic power and triac drive. The negative voltage or VSS for the logic is produced by the rectifying action of diode Dl of the current flowing through dropping resistors R16, R17 and R18. R18 acts as a fuse in the event R16, R17 or Dl should fail in the shorted mode. R18 is a non-flammable resistor which opens in a flameless manner. This type of supply allows the gate of the triac to be drawn negative for turn on, thus operating in Quadrants II and III. This allows for a more rugged triac to be used without unduly increasing the circuit cost. The total circuit current requirement is only 7 milliamperes including the 5 mills for the triac gate. This makes dropping resistors practical without much heat dissipation and eliminates the need for an expensive high voltage dropping capacitor.

Integrated circuit U3 is a 7 bit counter which functions as a timer by counting the number of line frequency cycles between events. The line frequency is supplied to the logic through resistor R13 and U20. Besides supplying the timing pulses, this signal is also used to synchronize the turn on of the triac to the zero crossing of the line frequency voltage as will be discussed shortly.

When a sharp sound or clap is detected by microphone MIC1, the signal appears across Rl. This is shown as a sharp peak in signal MIC1 of the timing diagram of Fig. 2. Operational amplifier U1A and its surrounding components comprise a high pass filter that eliminates the normal voice and background sound frequencies while passing the high frequencies associated with a clap. The filtered output of U1A is supplied to sensitivity control VRl. The output of the sensitive control is amplified by amplifier U1B, whose gain is determined by the values of R9 and RIO. The output of U1B is connected to a NAND gate U2A which is of the schmitt trigger type that conditions the signal for proper logic operation. This conditioned signal is then connected to the reset input of timer U3. See the U2A output signal of Fig. 2. This starts the timer from zero every time a clap is detected. The activation of the timer clock is accomplished by setting output Q7 to zero, which then activates the clock through U2C and U2D. This input to U2D gates the other input, which is the line frequency (60 Hz) . After one-half of one second the Q6 output of the timer U3 goes high^'and stays high for an additional one-half second, as shown in Fig. 2.

If a second clap comes during the time Q6 is high, then the NAND gate U2B toggles the D latch U4B. This calls for a change of output, either on or off. If the second clap arrives too soon, Q6 will not be high and nothing will happen except that the timer will be reset and start the timing over. If the second clap comes too late Q6 will be low and NAND gate U2B will close. Q7 will have gone high and Q7 is inverted by NAND gate U2C. The output of U2C acts in conjunction with NAND gate U2D to gate off the input signal to the counter/timer U3. This shuts the timer off while it waits for a new clap. Each clap starts the timer from zero.

Field experience has shown that if the triac is turned on at random whenever a signal is received it will turn on at peak line voltage as often as not. In the case of an incandescent lamp this creates a sudden high surge of current. The arc formed by the separating filament will produce an even higher current which can destroy the triac. It is necessary then to wait to turn the triac on until the line voltage is at or near zero. This eliminates almost all of this type of failure. This synchronization is accomplished by clocking the state of the first "D" latch U4B to the second "D" latch U4A when the line voltage passes through zero. As can be seen from Fig. 2, the U4A output does not toggle after U4B until the next low state of the clock. The output of this second latch controls the triac. As the CMOS "D" latch does not have enough output capability to drive the triac directly, it is buffered by U1C. This chip has a much higher current sinking capability than that of the 4000 series CMOS. Since the Ul outputs only source current when they are high, R14 is added to keep the triac gate from floating when it is off.

When the clapper is used to operate a fluorescent lamp, some time is required for the heaters at the ends of the fluorescent lamps to warm so that the lamp may light. Some users interpret this delay as improper. They clap again thinking that they did not clap hard enough the first time, thus turning the power off before the lamp has had time to light. To solve this problem, C7 and R21 have been added to prevent the "D" latches from Changing state for about 3 seconds after an "on" condition has been set. This prevents the clapper from being turned off until the lamp has lit. R20 is added to limit current flow on turn off. This is accomplished by connecting the U4A Q complement output to the RC network, and coupling the RC network to the reset input of both U4B and U4A. As can be seen from Fig. 2 , this signal will slowly decay over the 3 second period, holding tfie D latches in the appropriate state and preventing another toggle from a clap in that period.

As will be understood by those familiar with the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, the circuit could be triggered by the amplitude level of a clap, rather than the high frequencies associated with a clap. Accordingly, the disclosure of the preferred embodiment of the invention is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.

Claims

WHAT IS CLAIMED IS: '

1. A sound activated switching circuit for coupling a line power source to an appliance coupled to an output terminal of said switch, comprising: microphone means for detecting the sound and producing an electrical signal in response to said sound; a filter coupled to an output of said microphone means for eliminating all but a desired activating signal; a counter having an activating input coupled to an output of said filter for providing an output which is active for a predetermined window of time; gating means having one input coupled to said counter output and a second input coupled to said filter output to provide a gate output signal when a pulse from said filter is received during said window of time; and switching means having an activating input coupled to an output of said gating means to couple said line power source to said appliance.

2. The switching circuit of claim 1 further comprising a latch having an input coupled to an output of said gating means and an output coupled to an input of said switching means.

3. The switching circuit of claim 1 wherein said switching means is .a triac switch.

4. The switching circuit of claim 1 wherein said counter has a clock input coupled to receive an AC line power signal from said line power source.

5. The switching circuit of claim 4 further comprising a second gating means having one input coupled to receive said line power AC signal, a second input coupled to receive a signal from an output of said counter, and an output coupled to a clock input of said counter.

6. The switching circuit of claim 2 further comprising a second latch having an input coupled to an output of said first latch and having a clocking input coupled to a line power AC signal from said line power source.

7. The switching circuit of claim 1 further comprising means for preventing the output of said gating means from changing for a predetermined period of time after each change.

8. The switching circuit of claim 7 wherein said gating means comprises a AND or NAND gate and a latch, said latch having an input coupled to an output of said NAND or AND gate, said means for preventing comprising an RC circuit coupled to a reset input of said latch.

9. A sound activated switching circuit for coupling a line power source to an appliance coupled to an output terminal of said switch, comprising: microphone means for detecting the sound and producing an electrical signal in response to said sound; a filter coupled to an output of said microphone means for eliminating all but a desired activating signal; a counter having an activating input coupled to an output of said filter for providing an output which is active for a predetermined window of time; gating means having one input coupled to said counter output and a second input coupled to said filter output to provide a gate output signal when a pulse from said filter is received during said window of time; a second gating means having one input coupled to receive said line power AC signal, a second input coupled to receive a signal from an output of said counter, and an output coupled to a clock input of said counter; a first latch having an input coupled to an output of said gating means; a second latch having an input coupled to an output of said first latch and having a clocking input coupled to a line power AC signal from said line power source; and a triac switch having an activating input coupled to an output of said second latch to couple said line power source to said appliance.

10. A sound activated switching circuit for coupling a line power source to an appliance coupled to an output terminal of said switch, comprising: microphone means for detecting the sound and producing an electrical signal in response to said sound; a filter coupled to an output of said microphone means for eliminating all but a desired activating signal; a counter having an activating input coupled to an output of said filter for providing an output which is active for a predetermined window of time; gating means having one input coupled to said counter output and a second input coupled to said filter output to provide a gate output signal when a pulse from said filter is received during said window of time; a second gating means having one input coupled to receive said line power AC signal, a second input coupled to receive a signal from an output of said counter, and an output coupled to a clock input of said counter; a first latch having an input coupled to an output of said gating means; a second latch having an input coupled to an output of said first latch and having a clocking input coupled to a line power AC signal from said line power source; switching means having an activating input coupled to an output of said second latch to couple said line power source to said appliance; and an RC circuit coupled to a reset input of first and second latches.