WO1991010185A1

WO1991010185A1 - Basic building block for massively parallel computers

Info

Publication number: WO1991010185A1
Application number: PCT/HU1991/000001
Authority: WO
Inventors: Tamás LEGENDI; József TÓTH
Original assignee: Cellware Kft.
Priority date: 1990-01-03
Filing date: 1991-01-03
Publication date: 1991-07-11
Also published as: AU7064991A; HU900012D0

Abstract

The present invention refers to a basic building block for massively parallel computers, including a logic unit having control inputs (61) connectable to a control bus (6) and inputs (41) and outputs (11) connectable to processors in the neighbourhood. According to the invention the logic unit includes an internal state storage (5) connected by its output to a comparison input of a maskable equality comparator (4) linked with the inputs (41) of the logic unit, wherein the control inputs (61) of the logic unit connected to the control inputs of the internal state storage (5) and the remaining comparison and masking inputs of the maskable equality comparator (4), further the ouput of the internal state storage (5) are coupled with an input of a J-K logic (3) connected to one of the controil inputs (61). The proposed basic building block can be manufactured in a full modular manner, as many of them as required can be connected into a processor array for parallel computing.

Description

BASIC BUILDING BLOCK FOR MASSIVELY PARALLEL COMPUTERS

FIELD OF INVENTION

The invention refers to a basic building block for massively parallel computers, especially for the implementa¬ tion of bit processors of high performance computers of parallel system, of multiple instruction multiple data (MIMD) type, of non von Neumann principle based on a homogeneous cellular arrangement. This basic building block constitutes an important improvement in the field of the parallel computers and it can be called nanoprocessor.

BACKGROUND OF THE INVENTION

In the field of the parallel computers many kinds of systems have become known which comprise a high number of processors or cells characterized by identical construction, the processors or cells connected in an identical manner. These systems are capable of solving tasks comprising inherent parallelity with high performance. To the object of the present invention the systems lie near which are built up of elementary processors typically operating on 1 bit each and in which the cells are arranged in a square grid or eventually in a hexagonal type lattice. A computer of such construction is shown for example in the US-PS 3,979,728 and in re D. Parkinson: The ICL Distributed Array Processor (Infotech Future Systems, Vol. 2., pp. 389 -402., Infotech International, Maidenhead, Berkshire, 1977) , further in re T. J. Fountain: The Development of the CLIP-7 Image Process¬ ing System (Pattern Recognition Letters, 1 /1983/, pp. 331 - - 339, North Holland). Another known solution being near to this system is the systolic array introduced by H. T. Kung and C. E. Leiserson in "Systolic Arrays (for VLSI)" in re I. S. Duff, G. . Stewart: Sparse Matrix Proceedings (Society for Industrial and Applied Mathematics /1978/) , and shown in US-PS 4,493,048. The systolic arrays consist of a low number of different and simple special processors which form a highly homogeneous system for carrying out in a synchronous way different (e.g. matrix) operations with speed obtainable by the special hardware. It is advantageous to realize the systolic arrays in the form of VLSI type integrated circuits with regard to their massively homogenous structure based on local connections. In its original form the systolic array comes into being by connecting cells solving the step of the so-called inner product, the connection resulting in a system having regular net form. Together with realizing the connection it is ensured that the cell forwards besides the result also the input data to the preselected neighbours, so it can be stated that the data are "pumped through" the systolic array which can be practically considered as a special hardware.

The common feature of the solutions depicted above is that the construction of the elementary processors reflects the type of the special task to be solved (for example image processing) and the control and the organization form is linked with the data structure of the task. This results in the common disadvantage that they are effective only in solving the special task.

The object of the present invention is also near to the cellular automata introduced by Janos Neumann considered as being the model of the parallel computers (John von Neumann: The Theory of Self Reproducing Automata, ed. by A. . Burks, University of Illinois Press, Illinois, Urbana, 1966) . The literature of the art applies the expression "cellular computers" to this kind of arrangements. Such solution is disclosed in the article of I. V. Prangishvili and M. S. Uskach: "Principi postronieniya vichislitelnikh ustroistv i metodi organizatsii vichislitelnikh protsessov

SUBSTITUTESHEET na odnorodnikh strukturakh", in Avtomatika i Vichislitelnaya Tekhnika (March 1972) . The publication shows a cell field consisting of microcells connected to form a matrix. The cell proposed for the realization in the microelectronics is equipped with some fixed function ensured by wires and on this basis a spatially inhomogeneous computing field can be constructed. From among the functions realized by the cell only one can be selected before performing the program, this means, it is impossible to implement all Boolean function. The disadvantage of this solution is the lack of the internal bus, so neither this can be applied for implement¬ ing any Boolean function and thereby any function.

A solution equipped with one control bus is disclosed by T. Kondo et al in the publication: An LSI Adaptive Array Processor (IEEE Journal of Solid-state Circuits, Vol. 18., No 2., pp. 147 - 156, 1983). The solution shown therein includes an 8 * 8 array of cells of Conway-neighbourhood and respective switching networks. Each cell comprises two registers, one arithmetic—logic unit equipped with a carry bit and two data forwarding units. The operation to be carried out by the cell is basically determined by a command (broadcast by a control bus) . The circuit is of single instruction multiple data (SIMD) system and not of the previously mentioned MIMD system. Hence, it is more universal than the system analyzed above, but it is effective only when carrying out homogeneous vector and matrix operations.

SUMMARY OF THE INVENTION

The object of the present invention is to exclude the disadvantages shown above, to realize an elementary processor cell which can be the basis of a spatial and temporal inhomogeneous programmable system and which can implement any kind of transition function without the need of introducing any combination network implementing the selected transition function.

The invention is based on the combinative and syner- getic effect of two recognitions. One of the recognitions lies in the introduction of the internal state of the cell, the storage of which makes it possible to connect the cells into an inhomogeneous system. The other recognition is that by ensuring maskable equality comparison a set of terms prescribing identical function values for state combinations of one cell or more adjacent cells, i.e. a series of neighbourhood states can be selected and grouped together, a set which can be handled as a complex term to be executed in one step.

On the basis of the recognition depicted above the invention is implemented by a cell processor constituting a basic building block for massively parallel computers, including a logic unit having control inputs connectable to a control bus and inputs and outputs connectable to similar or different processors in the neighbourhood, wherein according to the invention the logic unit includes an internal state storage connected by its output to a comparison input of a maskable equality comparator linked with the inputs of the logic unit, the control inputs of the logic unit connected to the control inputs of the internal state storage and the remaining comparison and masking in- puts of the maskable equality comparator, further the output of the internal state storage are coupled with an input of a J-K logic connected to one of the control inputs.

In an especially preferred embodiment of the proposed basic building block in the logic unit having advantageously three, or four or six inputs and outputs a control input of a next state storage is connected with an output of the maskable equality comparator, its data input is linked with an input of the J-K logic, the output of the next state storage is coupled parallelly to an input of an present state storage, to the input of the internal state storage

SUBSTITUTESHEET and to the input of the J-K logic, wherein the output(s) of the present state storage is (are) connected with the output(s) of the logic unit.

The term "nanoprocessor" is intended to differentiate and depict the processor built up according to the invention in the way shown above.

The basic building block, i.e. the nanoprocessor realized according to the invention solves the task selected, by applying it a system being spatial and temporal inhomogeneous can be constructed and it is capable of evaluating any transition function. The spatial inho- mogeneity is ensured by the internal, state storage, further the temporal inhomogeneity and »the implementation of any kind of transition functions are assured by the central generation of the transition function and by the maskable equality comparator.

BRIEF DESCRIPTION OF THE DRAWINGS

The basic building block of the invention will be shown further in more detail on the basis of drawings illustrating a preferred embodiment of the invention by the way of an example only. In the drawings

Figure 1 is the block diagram of the basic building block of the invention as implemented.

DETAILED DESCRIPTION OF THE INVENTION AND THE PREFERRED EMBODIMENTS

The basic building block of the invention shown in Figure l is connected through control inputs 61 to a control bus 6 and through outputs 11, further inputs 41 to respective outputs and inputs of other adjacent basic building blocks connected also to the control bus 6 and forming the neighbourhood of this block. In the basic building block a control input 21 of a next state storage 2 is connected with an output of a maskable equality comparator 4 and a data input 22 thereof with an output of a J-K logic 3. The output of the next state storage 2 is parallely connected with an input of a present state storage 1 and the input of the J-K logic 3 and preferably an input of an internal state storage 5. The outputs 11 of the basic building block of the invention are constituted by the outputs of the present state storage 1. The inputs 41 of the basic building block and the outputs of the internal state storage 5 are linked with a group of comparising inputs of the maskable equality comparator 4. The group of the further comparising and masking inputs of the maskable equality comparator 4, further the control inputs of the next state storage 2, the internal state storage 5 and the J-K logic 3 form the control inputs 61 of the basic building block and they are connected to the control bus 6.

In the basic building block of the invention the J-K logic 3 is a combination network having one data input, two control inputs and one output. It is characterized by a Boolean function of three variables, especially by the function Q = J*D + K*D, it evaluates the contents of the next state storage 2. Here D is the signal of the data input, J and K mean the signals of the control inputs and the output is Q. The J-K logic 3 can be identified also as a part of the known J-K flip-flops.

The internal state storage 5 is typically a 2 to 10 bit register, and together with the present state storage 1 and the next state storage 2 are preferably realized in the form of gated transparent latches. The construction of the further blocks of the circuit is known for the artisan and the basic building block as proposed can be manufactured by the means of known methods of microelectronics, it constitutes a part of an integrated circuit of required

SUBSTITUTESHEET level of integration.

The way of operation of the basic building block of the invention built up preferably according to the example given above is extraordinarily simple. The basic building block is capable of carrying out three kinds of micro- commands, i.e. the microcommands of calculating state, of closing and of writing internal state. The microcommand of calculating state means that a so-called masked pattern consisting of a comparison value and a mask, further a J-K command is sent to the basic building block through the control bus 6. The basic building block, if its neighbour¬ hood state and internal state is equal with the masked pattern, executes the J-K command.

The microcommand of writing internal state renders it possible to fill into the internal state storage 5 of the basic building block the contents of the next state storage 2. If the number of bits of the next state storage 2 is lower than that of the internal state storage 5 the micro- command of writing internal state determines the bit(s) to be rewrited in the internal state storage 5.

During the execution of the closing microcommand the present state storage 1 receives the contents of the next state storage 2 and this means the end of the nano¬ processor's (basic building block's) operating step; this is executed when in the next state storage 2 of all basic building blocks constituting an array of a computer or other computing system the next state of the basic building block(s) had been calculated by the means of the micro- command of calculating state. During the operation the adjacent basic building blocks sense the present state of each other independently on the fact whether the basic building block has already taken up its next state. The present state storage 1 and next state storage 2 in the basic building block serve to this aim. The contents of the present state storage 1 are characteristic to the present state of the basic building block in each moment. The adjacent basic building blocks sense the state of the present state storage 1 because they are connected to the local data inputs 41 of the maskable equality comparators 4 of the adjacent basic building blocks. The value stored therein remains unchanged during evaluating the transition function. The next state of the basic building block is computed in the next state storage 2. During the closing step at the end of the nanoprocessor's operating step all basic building blocks constituting the processor array simultaneously take up their next state and allow the neighbours to sense it. This means, the value computed in the next state storage 2 is forwarded into the present state storage 1 in each of the basic building blocks forming a processor array.

As a consequence of operating according to the above example it is clearly shown that the array built up from the basic building blocks realized according to the invention operates in a parallel manner, even during serial evaluation of the transition function because all basic building blocks characterized by the.same neighbourhood state can operate in the same time. Hence, the speed of execution of the transition function in the basic building block remains independent on the number of the basic building blocks constituting the processor array.

An unexpected special advantage over the given above is and means a further improvement in the effectiveness that the masked comparison renders possible to give comparison don't care values when comparing the state of the adjacent basic building blocks.

In the solution according to the example given above all possible Boolean functions of the own state variable are built in, thereby the number of steps of evaluating the transition function is reduced to at least the half and this results in an about three-time increase of the speed, taking

SUBSTITUTESHEET into account the masked comparison also.^"

In the field of the invention it is possible to build in not only the Boolean functions of the own state but the functions of one or more neighbours, however, thereby the complexity of the basic building block quickly increases. In the example given above the increase of the speed by a factor of two is linked with a not remarkable increase of the complexity. If all the Boolean functions of the neighbours were built in this would result in an increase of the complexity in such extent which is less advantageous than the application of a large number of the basic building blocks. The increasing number of the basic building blocks is linked with a nearly linear increase of the speed. The solution shown in the drawings represents thereby an embodiment considered to be optimal.

The homogeneous construction of the basic building blocks called in the specification nanoprocessor realized according to the invention results in the advantage not expected but following from the combination that the full modularity is given which is especially important with regard to the manufacture of computers and the main advantage is that it is possible to connect with each other as many nanoprocessors as required. This circumstance makes the nanoprocessor implemented according to the invention form the basis for constructing systems differing from the known ones, of higher quality range, specially high reliability and of high error tolerance.

Claims

CLAIMS:

1. A basic building block for massively parallel com¬ puters, including a logic unit having control inputs (61) connectable to a control bus (6) and inputs (41) and outputs (11) connectable to processors in the neighbourhood, charac- terized in that the logic unit includes an internal state storage (5) connected by its output to a comparison input of a maskable equality comparator (4) linked with the inputs (41) of the logic unit, wherein the control inputs (61) of the logic unit connected to the control inputs of the internal state storage (5) and the remaining comparison and masking inputs of the maskable equality comparator (4) , further the output of the internal state storage (5) are coupled with an input of a J-K logic (3) connected to one of the control inputs (61) .

2. The basic building block according to claim 1, characterized in that in the logic unit a control input (21) of a next state storage (2) is connected with an output of the maskable equality comparator (4) , its data input (22) is linked with an input of the J-K logic (3) , the output of the next state storage (2) is coupled parallelly to an input of an present state storage (1) , to the input of the internal state storage (5) and to the input of the J-K logic (3) , wherein the output(s) of the present state storage (1) is (are) connected with the output(s) (11) of the logic unit.

3. The basic building block according to claim 1 or 2, characterized in that the logic unit has three, or four or six inputs (41) and outputs (11) .

SUBSTITUTESHEET