WO1991012576A1

WO1991012576A1 - Parallel string processor and method for a minicomputer

Info

Publication number: WO1991012576A1
Application number: PCT/US1991/000893
Authority: WO
Inventors: David H. Methvin; Chong Sam Un
Original assignee: Davin Computer Corporation
Priority date: 1990-02-12
Filing date: 1991-02-08
Publication date: 1991-08-22
Also published as: US5073864A

Abstract

A processor is disclosed for use in a computer system for comparing a number of bytes simultaneously in order to locate a particular character in a string of data. The processor includes a register (B) for holding the data bytes, a register (A) for storing the particular character, a comparison circuit (102, 109) for simultaneously comparing the bytes of the first register (B) with the bytes of the second register (A), and a circuit (115, 122) for generating indicator bits when a match has been found between the two registers. Microcode instructions cause the system to branch to a predetermined memory location when the control character has been located and to branch to a second predetermined memory location when no control character is found in the data string. A second portion of the processor finds the indicator bits generated from the circuit (115, 122) which have a predetermined characteristic and thus identifies the position of a particular byte in the data word that has the selected predetermined characteristic. In particular, four instructions are provided which find the first matching byte; the first non-matching byte; the first matching byte after the first non-matching byte; and the first non-matching byte after the first matching byte. A number of different operations can be performed based upon the output of the circuit (115, 122) to accomplish in one instruction operations that previously required a large number of instructions.

Description

PARALLEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER Notice Regarding Copyrighted Subject Matter

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

Background of the Invention

The present invention relates generally to computer systems for processing strings of data, and also to a parallel string processor for a minicomputer and a method of searching strings of bits and bytes for the presence of a desired keyword.

Prior art computers and microprocessors process data strings one byte at a time. One of the most frequently occurring processing tasks is to attempt to locate one or more control characters in a data string. Prior art systems compare the data one byte at a time to the control or reference characters which are loaded into a CPU (central processing unit) register. After a byte is compared, the data string is rotated one byte so that the next byte in the data string is compared, continuing until all bytes are compared.

The foregoing is a time-consuming procedure and utilizes a substantial amount of computer time as numerous repetitions of the comparison process are required to check each byte sequentially in order to determine whether it contains the reference character. For example, there may be only one "carriage return" (CR) character found per 80- character line, but all 80 characters must be compared one at a time. If a data string has 512 bytes, and each byte is separately compared to the control character, the comparison must be executed 512 times. Thus, a need exists for reducing the amount of time required to compare strings of data and find control characters embedded in the strings.

Eight bytes of data are simultaneously compared. Thus, the number of comparisons necessary is reduced by a factor of 8 relative to a single byte comparison, resulting in a substantial reduction of processing time. Since the comparison procedure is commonly executed numerous times in any given program, a significant saving in processing time may be achieved by this simultaneous comparison of a number of bytes.

In other computer applications it is desirable to have the capability to search long strings of bytes for the presence of a selected pattern of bytes. One such application that is relatively well known is used in the word processing context. This application allows one to search a portion of text for a particular word or phrase. For example, one may want to find each occurrence of the word "country" within a particular document so that the word "county" can be substituted therefor. Alternatively, one may want to find each occurrence of "couty" so that it can be replaced with the proper spelling "county." These are known as search and replace operations. Search and replace operations are also used in connection with automatic spelling check programs that are offered by many commercially available word processing programs.

In word processing programs and other programs in which words and letters are used, each letter of the alphabet as well as each symbol such as an asterisk or hyphen is represented as a unique string of eight 1 or 0 logic bits, also known as a byte. In order to determine whether two byte strings represent the same word, the corresponding bits in each byte are compared to determine whether they are the same. If all of the bits in the two byte strings are identical, the two byte strings represent the same word. A portion of text can be thought of and is represented as a long, continuous string of bytes, one byte for each letter appearing in the portion of text. To determine whether a particular word, or "keyword," appears in a portion of text, current string processors typically, starting at the beginning of the byte string that represents the portion of text, or the "character string," compare the first byte of the keyword with the first byte of the character string. If these two bytes match (the first letter of the keyword matches the first letter in the portion of text), then the processor compares the second byte in the keyword to the second byte in the character string. If these two bytes match, then the processor compares the next pair of bytes in the two strings, and so on. If all of the respective bytes in the two strings match, the processor has found an occurrence of the keyword in the portion of text.

However, the keyword does not usually appear as the first word in the portion of text being searched. Consequently, one of the bytes of the keyword will not match one of the bytes in the character string (the keyword is not the first word in the portion of text). In this case, the character string is shifted one byte relative to the keyword so that the first byte of the keyword is compared to the second byte of the character string. If these two bytes match, then the second byte of the keyword is compared to the third byte of the character string, and so on. If one of the pairs of bytes do not match, then the character string is again shifted one byte relative to the keyword so that the first byte of the keyword is now compared to the third byte of the character string. This general process repeats, usually until all occurrences of the keyword in the portion of text have been found.

As an example, let the keyword be the word "the" and the character string be "that time is the essence." Initially, as described above and set forth below, the byte representing the "t" in "the" will be compared to the byte representing the "t" in "that":

Data String: that time is the essence

Keyword: the

This comparison will yield a match, and so the byte representing the "h" in "the" will be compared with the byte representing the "h" in "that." These bytes will also match, and so the byte representing the "e" in "the" will be compared to the byte representing the "a" in "that." These bytes will not match, and so the character string will be shifted one byte with respect to the keyword so that the first byte of "the" will be compared with the second byte in the character string. The relative position of the keyword and the character string are set forth below, and the "3" above the letter "t" in the word "that" is the number of comparisons that were required to determine whether or not there was a match.

Comparisons: 3

Data String: that time is the essence

Keyword: the

Only one comparison will be needed at this point to determine that the keyword is not present at this portion of the character string, and the character string will be shifted again:

Comparisons: 31

Data String: that time is the essence

Keyword: the

This process will continue to repeat until the match is found, at which point the character string will have been shifted to the position set forth below:

Comparisons: 31121211111114

Data String: that time is the essence

Keyword: the Note that this particular example required 21 comparisons to find the keyword "the" in the character string "that time is the essence." In particular, four comparisons were required even where the keyword matched the same word in the character string (the blank space required one comparison).

In other computer applications it is desirable to test bit patterns for the presence of a particular bit string. Examples of such applications are encryption and decryption algorithms used to scramble and unscramble binary information to protect it from unauthorized reception. Such algorithms are often used in the intelligence field to protect highly classified information from being intercepted and used by foreign countries having adverse interests. These algorithms are also used by corporations to safeguard their valuable commercial information and trade secrets.

In general, these encryption and decryption algorithms may perform similar search and replace operations as described above in connection with word processing programs. In addition, it would be desirable to be able to perform operations on strings of binary information that are not an integral number of bytes long, for example, a string of five bits. Processors such as those described above in connection with word processing programs do not even have this capability since they shift strings of eight bits, or one byte, at a time. Even if such processors had the capability to shift strings of data one bit at a time, their use as described above on strings of bits would be even slower due to the large number of comparisons that would be necessary. As an example, assume that the bit string "11001110011011" is to be searched for the presence of the keyword "1101." Initially, as described above, the first bit of the keyword would be compared to the first bit in the bit string as set forth below:

Bit String: 11001110011011

Keyword: 1101 The processor would need to make four comparisons before it could determine that the four bits in the keyword do not match the first four bits in the bit string. Again, as described above, the processor would then shift the bit string relative to the keyword string as set forth below and compare the respective bits again:

Comparisons: 4

Bit String: 11001110011011

Keyword: 1101

Again, the "4" above the first "1" in the bit string means that four comparisons were required in order to determine that the keyword did not match. After the keyword was shifted as shown above, two comparisons would be required to test the next portion of the bit string. As shown below, 22 comparisons would be needed to find the portion of the bit string that matched the keyword.

Comparisons: 4211242114

Bit String: 11001110011011

Key Word: 1101

A greater number of comparisons are required overall in bit searching than are required in byte or character searching since it is more likely that a pair of bits each having one of two possible values will match than a pair of letters each having one of 26 possible values. Thus, a processor performing operations on bit strings in this manner would have an unduly large amount of computing overhead.

Summary of the Invention

The present invention comprises a portion of a computer system for comparing a number of bytes simultaneously. The parallel processor of the present invention includes a first register for receiving bytes of data, a second register for storing a number of copies of a byte representing a selectable control or reference character and a comparison circuit for simultaneously comparing the data in the two registers to determine whether any of the bytes in the first register are equal to the bytes representing the control character in the second register, and generating control bits which are in a first state if the corresponding byte in the first register is equal to the control character in the second register, and in a second state when the corresponding byte in the first register is not equal to the control character in said second register.

The parallel byte processor has the ability to branch to a predetermined memory location if any of the byte pairs being simultaneously compared are equal. If any byte of data in the first register is equal to the bytes comprising the control characters in the second register, the microcode instruction branches or proceeds to a predetermined memory location.

If no control character is located in the data in the first register, the instruction branches or proceeds to a second predetermined memory location. Thus, a number of bytes may be moved and checked for control characters with a single instruction, thereby substantially reducing the processing time. In an exemplary embodiment of the present invention, eight bytes of data are simultaneously compared.

Another aspect of the invention is directed towards a novel parallel bit and byte string processor for a minicomputer. In its byte mode, the processor stores a portion of a string of bytes that is to be tested for the presence of a desired keyword in a first register location and stores the keyword in a second register location. Instead of testing the portion of the byte string one byte at a time, the processor simultaneously tests each byte in the keyword with a respective byte in the byte string. Thus, only a single comparison is required to determine whether the keyword is present in any portion of the byte string. If the keyword is not present in the portion of the byte string tested, then the processor shifts the byte string with respect to the keyword and then makes a single comparison of the keyword with the new portion of the byte string. This single-compare-and-test process continues until either the keyword is found or the end of the byte string is reached. As a result of simultaneously testing each byte in the keyword with a respective byte in the byte string, the processing time is kept to an absolute minimum.

In its bit mode of operation, the processor stores a portion of a bit string that is to be tested for the presence of a desired string of bytes in a first register location and the desired keyword in a second register location. The processor simultaneously tests each bit in the keyword with a respective bit in the bit string. As a result of this simultaneous testing, only one comparison is needed to determine whether the keyword is present in the portion of the bit string being tested. If the keyword is not present, the bit string is shifted one bit relative to the keyword and a single comparison of the keyword with the new portion of the bit string is made. This process continues until the keyword is found or until the end of the bit string is reached. Because each bit in the keyword is simultaneously tested with a respective bit in the bit string, only a single comparison is required to determine whether the keyword matches a portion of the bit string, and as a result, processing time is minimized.

Another feature of the invention is the capability of the processor to automatically function either as a parallel bit processor or as a parallel byte processor. When the processor is given a first control signal, the processor functions as a parallel byte processor, and when the processor is given a second control signal, the processor functions as a parallel bit processor. As a result, two separate processors are not required, thus resulting in cost saving that a separate processor would otherwise entail.

Another aspect of the present invention is a set of novel instructions that are particularly useful for testing the outputs of byte comparisons. One such instruction finds the location of the first byte (i.e., most significant) in a first data word that is identical to the corresponding byte in a second data word. A similar instruction finds the location of the first byte in the first data word that does not match the corresponding byte in the second data word. A third instruction finds the first byte in the first data word that matches the corresponding byte in the second data word so long as the matching byte is less significant than a byte in the first data word that does not match the corresponding byte in the second data word. A fourth instruction finds the first byte in the first data word that does not match the corresponding byte in the second data word so long as the matching byte is less significant than a byte in the first data word that matches the correspondin byte in the second data word. The processor includes novel circuitry to implement these instructions.

In particularly preferred embodiments, the processor includes a replication Instruction and associated circuitry that duplicates a single Input byte into all the bytes of a multiple byte data word. The replication instruction is particularly useful for comparing an input data string toa predetermined control character or other delimiter. An improved replication circuit operates on data words in memory and replicates one or more bytes in selected positions in a memory word or two memory words.

A switch on first hit and a switch on first miss instruction provide the capability to branch to a selected location based upon the, location of the first hit or the location of the first miss.

A set of instructions are included that clear selected portions of a data word based upon the location of a first hit or the location of a first miss.

A pair of instructions are included to clear a hit register that determines the first hit or the first miss so that processing can occur on additional bytes in a data word associated with the data in the hit register.

These and other objects, features, and advantages of this invention will be apparent in view of the following detailed description of several preferred embodiments, which are explained with reference to the figures, a brief description of which is provided below.

Brief Description of the Drawings

Figures 1 and 2 are block diagrams of two registers of the parallel byte comparison processor;

Figure 3 is a circuit diagram of the comparison circuit of the parallel byte comparison processor;

Figure 4 is a representative instruction sequence of the parallel byte comparison processor;

Figure 5 is a schematic circuit diagram of a parallel string processor in accordance with the invention;

Figure 6 is a detailed circuit diagram of a portion of one embodiment of a shift register in accordance with the invention;

Figure 7 is a detailed circuit diagram of a portion of the parallel string processor of Figure 5;

Figure 8 is a detailed flowchart of the operation of the parallel processor of Figure 5 in its byte mode of operation;

Figure 9 is a detailed flowchart of the operation of the parallel processor of Figure 5 in its bit mode of operation;

Figure 10 is a block diagram illustrating the circuitry to implement instructions to find specific occurrences of hits and misses in the hit register;

Figure 11 is a block diagram illustrating the operation of circuitry to implement a replicate instruction to cause the data in one byte to be replicated in all the bytes of a data word;

Figure 12 is a logic diagram of the replication circuit of Figure 11 showing a particular implementation of the replication circuit;

Figure 13 is a block diagram of an rotate/replicate circuit of the present inven that implements the 1oad/replicate instruction;

Figure 14 illustrates the operation of the rotate/replicate circuit for a single byte;

Figure 15 illustrates the operation of the rotate/replicate circuit for a double byte;

Figure 16 illustrates the operation of the rotate/replicate circuit for a half-word;

Figure 17 illustrates the operation of the rotate/replicate circuit for a three-byte rotation;

Figure 18 illustrates the operation of the rotate/replicate circuit on eight bytes of data across a data word boundary;

Figure 19 illustrates a detailed block diagram of the rotate/replicate circuit showing the interconnections of the bits to the programmable logic devices;

Figure 20 illustrates a first register R1 having a plurality of control characters and a second register R2 having a replicated data byte to be compared to the control characters;

Figure 21 illustrates an exemplary instruction sequence showing the displacement and scaling functions of the Switch on First Hit instruction;

Figure 22 illustrates an exemplary switch on first hit or miss circuit in accordance with the present invention; Figure 23 illustrates a first register containing a portion of an input data stream and a second register containing replicated copies of a character representing a space;

Figure 24 illustrates the first register of Figure 23 showing the effect of the Clear Data From First Hit instruction on the data in the first register;

Figure 25 illustrates the first register of Figure 23 showing the effect of the Clear Data To First Hit instruction on the data in the first register;

Figure 26 illustrates the first register of Figure 23 showing the effect of the Clear Data First Hit instruction on the data in the first register;

Figure 27 illustrates a first register containing a portion of an input data stream and a second register containing replicated copies of a character representing a space;

Figure 28 illustrates the first register of Figure 27 showing the effect of the Clear Data From First Miss instruction on the data in the first register;

Figure 29 illustrates the first register of Figure 27 showing the effect of the Clear Data To First Miss instruction on the data in the first register;

Figure 30 illustrates the first register of Figure 27 showing the effect of the Clear Data First Miss instructio on the data in the first register;

Figures 31a and 31b respectively illustrate the hit register before and after the Clear First Hit instruction;

Figures 32a and 32b respectively illustrate the hit register before and after the Clear First Miss instruction; Figure 33 illustrates an exemplary circuit that implements the Clear Data instructions and Clear Hit Register instructions of the present invention; and

Figure 34 illustrates the data pattern within the pattern generator of Figure 33.

Detailed Description of Several Preferred Embodiments

Referring to Fig. 1, a selected control character, such as "EOS" (end of sector), is loaded into a Register A. Referring to Fig. 2, an 8-byte (64-bit) data string is loaded into a Register B and compared to the "EOS" reference characters in Register 2f in order to determine whether there are any "EOS" characters in any byte of the data string in the Register A. The results of the comparison, whether any particular byte of Register A matches the corresponding byte in Register B, is stored in a Processor Status Register 100 (also referred to as the "hit register").

It will be appreciated that with the present invention, any number of bytes may be simultaneously compared, the number depending on the particular computer system utilized. In the preferred embodiment discussed herein, the computer is a 64-bit machine; therefore, 8 bytes are simultaneously compared to determine whether they contain a controll character.

Each bit in the data string in the Register B is compared to the bits comprising the control characters in Register A. This is shown in more detail in Fig. 3, wherein each bit of each byte 0-7 in the Register B is compared with the corresponding bit of each corresponding control character byte 0-7 in the Register A, utilizing "exclusive- NOR" circuits 102-109, one "exclusive-NOR" circuit associated with each bit pair. It should be understood, however, that Fig. 3 is a functional diagram to illustrate the invention. In the actual embodiment, an arithmetic logic unit (ALU) is utilized to perform the exclusive-OR function as shown in Fig. 5 and discussed in further detail hereinafter. In Fig. 3, only the exclusive-NOR circuits 102a and 102h corresponding to byte 0, bit 0 (the least significant bit) and byte 0, bit 7 respectively, and 109a and 109h corresponding to byte 7, bits 0 and 7, respectively are shown. It should be understood, however, that there are 64 such exclusive-NOR circuits. In addition, only the portions of Registers A and B containing bytes 0 and 7, corresponding to the least significant bytes and most significant bytes, respectively, are shown in Fig. 3. The designations within Registers A and B denote the register, the byte number and the bit within the bytes. For example, "A67" refers to bit 7 of byte 6 of the Register A.

The components of the exclusive-NOR circuit 109 are also shown in Fig. 3 as comprising first and second AND gates 110 and 111, first and second inverters 112 and 113, and OR gate 114. The bit pairs, for example, A77 and B77, are input to the AND gate 110. The bits A77 and B77 are also inverted by inverters 112 and 113, respectively, and are input into the second AND gate 111 of the exclusive-NOR circuit. The output of the first AND gate 110 and the output of the second AND gate 111 are input to the OR gate 114. The output of each OR gate is provided as an input to one of eight 8-input NAND gates 115-122 (the NAND gates 116- 121 are not shown). There is one 8-input NAND gate for each byte being compared. The output of any of the 8-input NAND gates 204-210 will be low or logical "0" only when all eight bits being compared are equal and thus will indicate that the particular byte pair is equal to each other (e.g., when all the bits A00-A07 of the Register A are equal to the corresponding bits B00-B07 of the Register B, the output of the 8-input NAND gate 115 will be low).

The output of NAND gates 115-122 are stored in the Processor Status Register 100 or "hit" register (Fig. 2). An instruction (BAH) causes the system to branch or proceed to a predetermined memory location when any of the bits in the Processor Status Register 100 indicate that any of the eight bytes being compared are equal. Alternatively, if there are no bits in the Processor Status Register 100, indicating that no byte pairs match and no control character was found, the system proceeds to execute the instruction found in the next sequential memory location in the control memory of the processor. If a hit occurs, the location of the particular bytes which do match can be determined by looking at which bits of the Processor Status Register 100 indicate a match.

For example, if byte 2 of the Register A is equal to byte 2 of the Register B, bit 2 in the Processor Status Register 100 will be zero, indicating that the byte 2 pair matches.

Fig. 4 shows a representative instruction sequence. The left column corresponds to the line number in the control program of the processor. The instruction at line 80 causes the control character being compared to be loaded into the Register A. The instruction at line 82 causes the loading of Register B with the first eight bytes of data (data word 1, indicated as "DATAl" in Fig. 4). The instruction at line 84 performs the multibyte "exclusive- NOR" operation of the present invention on the data in the Register B and the Register A. The instruction at line 86 causes the system to branch to a memory location 400 if any of the bits in the Processor Status Register 100 (Fig. 2) are zero indicating that a match was found between the Registers A and B. At memory location 400, which is executed if a hit is found, is the beginning of a routine which examines the bits of the Processor Status Register 100 to determine the location of the characters within data word l which match the control character;. "EOS" for example.

Then at line 88, Register A is loaded with a second control character and at line 90 the exclusive-NOR operation is performed to determine whether the second control character is present in any of the eight bytes of data in DATAl. If the second control character is found in DATAl, then at line 92 the program branches to memory location 400. When there are no control characters found in the data, the instruction at line 94 is executed and the data in Register B is stored in a buffer. Thereafter, the system proceeds to execute the instruction at line 80 and the process described above repeats. Thus, eight bytes are checked for two different control characters with only two compare cycles in contrast to the 16 compare cycles required in prior art machines.

A "branch on no-hits" may be utilized as an alternative to the "branch on any hit" instruction, which branches to a memory location if none of the bytes in the data word contain the control character.

When the data is checked for more than one set of characters, the Register A may be reloaded with the characters for each compare sequence. However, to increase the execution speed, reloading the register may be avoided by various methods known to those skilled in the art. An n- to-1 multiplexer may be substituted for the Register A, where n is the number of character sets to be searched for in the data. For example, if the data is to be searched for two sets of characters, "EOS" and "CR," a 2-to-1 multiplexer may be utilized, with the registers containing "EOS" and "CR" serving as input to the multiplexer.

In the preferred embodiment, the architecture of the CPU permits the selection of the desired register for input to the exclusive-NOR circuit. Instructions cause the CPU to route the contents of the selected register to the exclusive-NOR circuit. Alternatively, tri-state devices may be utilized.

In the actual embodiment, an arithmetic logic unit (ALU) 140 is utilized to perform the exclusive-OR function. Referring to Fig. 5, the End of Sector (EOS) or othe control characters are loaded into the A register file. The data which is to be searched for the End of Sector flag is loaded in register B via the B bus 172. The EOS flag is input to the ALU 140 through the A latch 142 and the data to be compared to determine whether it contains "EOS" characters is input to the ALU 140 through B latch 144. The ALU 140 compares each bit of input from the A register to the corresponding bit of input from the B register. For each matching bit pair, the ALU 140 will generate a zero on the respective output line. The output of the ALU 140 is input to the zero detect circuit 150 (which comprises 8- input NOR gates) via the F bus 148. The zero detect circuit 150 determines whether all of the bits within a byte are zero. If all of the bits within a particular byte are zero, a one is generated by the zero detect circuit 150 indicating that a particular byte from the A register matches the byte from the B register. The foregoing embodiment utilizes inverse logic from the illustrative circuit shown in Fig. 3. In the circuit shown in Fig. 3, a zero is generated when the byte pairs match.

A parallel string processor in accordance with another aspect of the invention is shown in Fig. 5. The processor includes a dual register file 120 comprising an A register file and a B register file. Although only nine registers are shown in each register file, each register file 120 includes 1024 registers, and may include more if desired. In this embodiment, the processor of Fig. 5 is for a 64-bit minicomputer, and so each of the registers in the A and B register files is 64 bits, or eight bytes, wide. The A register file is shown to include an address register 122, a length register 124, a bit mask register 126, a byte mask register 128, and a test register 130. The address register 122 is used to store the address of a data string, either a bit string or a character string, that is to be searched by the processor for a particular keyword. The length register 124 is used to store the length of the portion of the data string that remains to be tested. The bit mask register 126 is used to store a desired pattern, of bits that is used to mask the keyword. For example, the bit mask register 126 might be used to ignore capital letters so that the processor would consider the letter "a" to be equivalent to the letter "A." The byte mask register 128 contains a desired pattern of bytes used to mask the keyword. For example, the byte mask register 128 might be used to ignore the second letter of a word so that the processor would equate the word "string" with "spring." The test register 130 contains the desired keyword after it has been masked with the desired byte mask.

The B register file contains a bit count register 132 and a byte count register 134 which, as is explained in more detail hereinafter, determine when the next portion of the data string being tested for the presence of the keyword needs to be fetched from memory. A keyword register 136 contains the binary data string corresponding to the desired keyword, and the end-of-string (END) flag register 138 contains a flag that indicates whether or not a data string has been completely searched for the presence of a desired keyword.

The A and B register files are connected to an arithmetic logic unit (ALU) 140 through an A latch 142 and a B latch 144, respectively. The ALU 140 is a conventional arithmetic logic unit, which in this embodiment may include SN54LS381A ('381), SN54LS382 ('382), or similar integrated circuit chips commercially available from Texas Instruments of Dallas, Texas. The arithmetic logic unit 140 performs various operations on the data supplied to its dual data inputs, depending upon the combination of binary signals supplied to its control inputs by an ALU function select circuit 146. For example, when the ALU 140 receives a particular combination of control inputs, the ALU 140 adds its two data inputs. In response to a different combination of its control inputs, the ALU 140 performs an exclusive-or operation on its data inputs.

The A and B register files are designed so that at any time, the binary information stored in each register is equal to the binary information stored in its adjacent register so that the A register file is a copy of the B register file, and vice-versa. This register organization speeds up the operation of the processor. In order to perform an operation on two operands, one operand must be transmitted to the A latch 142 and the other to the B latch 144. If there were only an A register file, the processor would require an extra cycle to perform any given ALU operation.

The output of the ALU 140 is connected via an 64-bit- wide F-bus 148 to a zero-detect circuit 150 which detects when all the outputs of the ALU 140 are zero. The ALU 140, ALU function select circuit 146, and zero detect circuit 150 are shown in detail in Fig. 7. The ALU function select circuit 146 is shown functionally (in dotted lines) for purposes of explaining the invention. In reality, the function select circuit 146 is implemented with programmable array logic integrated circuits commercially available from Monolithic Memories, Inc. of Santa Clara, California, that are programmed with many equations that do not facilitate explanation. These equations are, however, included in this specification as Appendix 1, and they completely describe the actual embodiment of the ALU function select circuit 146.

The ALU comprises 16 separate, 4-bit '381 integrated circuit chips 152. For purposes of clarity, the data inputs of the ALU chips 152 that are connected to the A and B latches 142, 144 have been omitted from Fig. 7, and only the outputs of the chips 152 are shown. Each pair of the chips 152 is connected to a respective multiplexer 154 which supplies the control inputs for the chips 152. Each of the multiplexers 154 either supplies a desired 3-bit FUNCTION signal or a 3-bit CLEAR signal to the control inputs of the pair of chips 152 to which it is connected, depending upon the value of its address signal sent from a register 156 which stores the 8 bits of the byte mask. As explained above, the byte mask causes the processor to ignore certain bytes in the data string being searched so that, for example, the processor would equate the keyword "string" with the word "spring" in the data string, in which case the second bit of the byte mask would be set to logic "1" so that the "p" in "spring" is ignored. Similarly, if it were desired that the fourth letter of a word were to be ignored, the fourth bit of the byte mask would be set to logic "1." The multiplexers 154 either supply a specified FUNCTION signal or a CLEAR signal to the chips 152, depending upon whether the value of the particular bit of the byte mask in the register 156 is logic "1" or "0." If the bit in the byte mask is logic "0," the desired 3-bit FUNCTION signal is transmitted, and if the bit in the byte mask is logic "1," the 3-bit CLEAR signal is sent, which causes the outputs of the ALU chips 152 to which it is connected to be forced to logic "0."

The zero detect circuit 150 comprises 16 NOR gates 158 connected to receive the outputs of the ALU chips 152. The outputs of the NOR gates 158 are connected to eight AND gates 160, which in turn are connected to a pair of NAND gates 162 which are connected to a NOR gate 164. If all outputs of the ALU chips 152 are logic "0," then it can be seen that the outputs of the NOR gates 158 will be forced to logic "1," which forces the outputs of the AND gates 160 to logic "1," the NAND gates 162 to logic "0," and the NOR gate 164 to logic "1." Thus, the output of the NOR gate 164 will be logic "1" only when all the outputs of the ALU chips 152 are logic "0." As set forth below, when the keyword matches a portion of the data string to which it is being compared using the exclusive-or function, all the ALU chip outputs will be logic "0," so that in essence a logic "1" output of the NOR gate signals a match. This logic "1" output is supplied to a flip-flop 166 which can then be checked to determine that there was a match. The particular logic gates used in the zero detect circuit 150 are not important to the invention since other circuits could be easily designed to detect that all outputs of the ALU chips were logic "0," such as, for example, a single 64-bit NOR gate.

Referring now to Fig. 5, the F-bus 148 is connected to an A-bus 168 via a buffer 170 and a B-bus 172 via another buffer 174. The zero-detect circuit 150 is coupled to the B-bus 172 through a buffer 176. A memory 178 is connected to the bus 180 that connects the output of the A latch 142 to the ALU 140 through a buffer 182 connected to an M-bus 184. Because this embodiment is for a 64-bit minicomputer, the A-bus 168, the B-bus 172, and the M-bus 184 are also 64 bits wide. A pair of serially connected 64-bit shift registers, comprising a J shift register 186 and a K shift register 188, are connected to the B-bus 172. A mask register 190 is connected to the J shift register 186 via a mask bus 192. As is explained in more detail below, these shift registers are used to store portions of the data string to be tested for the presence of a desired keyword.

A trio of control signals is supplied to each of the two shift registers 186, 188. A LOAD signal causes the register to which it is attached to be parallel-loaded with a portion of a data string. The data is loaded into the registers 186, 188 from the memory 178 through a data route consisting of the ALU 140, the Frbus 148, the buffer 174, and the B-bus 172. A second signal SI causes its respective shift register to be shifted left one bit, and a third signal S8 causes its respective shift register to be shifted left eight bits, or one byte.

Fig. 6 is a portion of a substantially functional equivalent of the J shift register 186 used for purposes of explaining the invention. The actual embodiment of the J and K shift registers 186, 188 comprises specially progreunmed conventional programmable array logic integrated circuits commercially available from Monolithic Memories, Inc. of Santa Clara, California, and the equations used to program these integrated circuits are included in this specification as Appendix 2 and completely describe the actual embodiment of the J and K shift registers 186, 188.

Referring now to Fig. 6, a portion of the J shift register 186 consisting of logic gates and flip-flops 196 is shown. Although only six flip-flops 196 are shown, the J shift register 186 is 64 bits wide and thus includes 64 serially connected flip-flops 196. In Fig. 6 the flip-flops 196 are numerically ordered, with the rightmost flip-flop being the Nth flip-flop, the flip-flop to the left of the Nth flip-flop being the (N+1)st flip-flop, etc. Each of the flip-flops 196 has a data input D connected to the output of a logic circuit 198 and a clock input C connected to receive a CLOCK signal that controls the speed of operation of the shift registers 186, 188.

The logic circuits 198 control the loading and shifting operations of the flip-flops 196. Each of the logic circuits 198 comprises a three-input OR gate 200 and three two-input AND gates 202. One of the AND gates 202a has a first input connected to one of the 64 lines of the B-bus 172 and has its second input connected to the LOAD signal. This AND gate 202a in each of the logic circuits 198 causes the flip-flop to which it is connected to be loaded with the binary value of the B-bus 172 when the LOAD signal is activated, which occurs when the LOAD signal is logic "1." In this state, the output of the AND gate 202a, which equals the binary value of the B-bus input, is supplied to its respective flip-flop 196 through its OR gate 200. The outputs of the other two AND gates 202b, 202c do not interfere with this loading process since the SI and S8 signals are forced to logic "0" when the LOAD signal is activated.

After a portion of a data string is loaded into the flip-flops 196 of the shift registers 186, 188, the portion is periodically shifted either one bit or eight bits at a time, depending on whether the processor is performing a bit-by-bit comparison or a byte-by-byte comparison. If bit comparisons are being performed, the S1 signal is activated to logic "1" while the LOAD and S8 signals remain at logic "0." Each AND gate 202c to which the S1 signal is supplied has its other input connected to the output of the first upstream flip-flop, "upstream" meaning the direction from which data is being shifted. In Fig. 6, data is being shifted from right to left, and thus with respect to any particular flip-flop or other circuit element, the first "upstream" flip-flop is the first flip-flop to the right of the circuit element and the first "downstream" flip-flop is the first flip-flop to the left of the circuit element. Thus, when the S1 signal is activated, the output of the AND gate 202c to which it is connected is equal to the output of the upstream flip-flop. Since the output of the AND gate 202c is passed through its respective OR gate 200 to the input of the downstream flip-flop, the activation of the S1 signal causes the shift registers 186, 188 to perform a one- bit logical left shift on the portion of the data string stored therein.

The activation of the S8 signal causes an eight-bit, or one-byte, logical left shift to be performed by the shift registers 186, 188. Each AND gate 202b to which the S8 signal is connected has its other input connected to the output of the eighth upstream flip-flop so that when the S8 signal is logic "1," the output of each of the flip-flops 196 is passed to the eighth respective downstream flip-flop so that the portion of the data string is shifted eight bits to the left.

Another portion of the J shift register 186 performs a bit mask operation so that any desired bits of the string being searched may be ignored. For example, as described above, it might be desirable to ignore capital letters so that the processor would consider the letter "a" to be equivalent to the letter "A." To this end, the output of each of the flip-flops 196 is supplied to one input of a two-input AND gate 204 having its other input connected to receive the output of a NAND gate 206. One input of the NAND gate 206 is connected to receive a respective bit of the bit mask from the mask register 190 connected to the J shift register 186 via the mask bus 192. The NAND gate 206 is also connected to receive a BIT MASK ENABLE signal that selectively activates or deactivates the bit mask operation. In particular, when the BIT MASK ENABLE signal is logic "0," the outputs of all of the NAND gates 206 are forced to logic "1" so that the outputs of the AND gates 204 equal the output of the flip-flops to which they are connected and are not affected by the outputs of the NAND gates 206. However, when the BIT MASK ENABLE signal is logic "1" and the corresponding mask input bit is also logic "1," the output of the NAND gate 106 is forced to logic "0," and as a result, the output of the AND gate 204 is also forced to logic "0." This operation thus causes logic "0"s to be placed in each bit of the data string which is to be ignored by the processor. As is described in more detail below, each of these logic "0"s causes a forced match when the masked portion of the data string is compared to the keyword string by the processor. Finally, the output of each of the AND gates 204 is connected to the B-bus 172 so that the masked or unmasked portion of the data string stored in the shift registers may be supplied to the ALU 140 for comparison to the keyword string.

The particular logic used for the masking functions is not important, and alternative logic could be used. For example, selected bits in a bit string could be masked off if the corresponding bits in the bit mask were logic "0" instead of logic "1" if the NAND gates 206 were replaced with OR gates, in which case the bit mask enable signal would be activated when logic "0" instead of logic "1."

The functional circuit diagram of the K shift register 188 is substantially identical to the diagram of the J shift register 186 shown in Fig. 6, except that the AND gates 204 and the NAND gates 206 used in connection with the bit mask and the BIT MASK ENABLE signal are not required since only the output of the J shift 186 register is sent to the ALU 140 for comparison to the keyword, as is explained in more detail below.

In its byte mode of operation, the processor compares a selected string of bytes to determine the presence of a selected keyword. Both the byte string and the keyword are selectable by the user of the processor. The basic process by which the processor tests for the presence of a selected keyword string within a selected data string includes initially loading the J and K shift registers 186, 188 with the first portion of the data string to be tested. Then, the entire contents of the J shift register 186 are simultaneously compared with the keyword stored in the test register 130. If there is a match, the presence of a match is indicated by the processor. Then, the contents of the J and K registers 186, 188 are shifted left one byte and the contents of the J register 186 are again compared with the contents of the test register 130. Any match is indicated, and the process is repeated. Periodically, the K register 188 will become empty since its contents are gradually shifted into the J register 186, and so the K register will be periodically reloaded with the next portion of the data string to be tested. In this manner, the entire keyword is simultaneously compared with a corresponding portion of the data string. This process reduces the number of comparisons required as shown by the exeunple shown below, in which the keyword is "the," the data string is "that time is the essence," and each number above the data string represents the number of comparisons that were required to determine whether or not the keyword matched that particular portion of the data string:

Comparisons: 11111111111111

Data String: that time is the essence

Keyword: the

Note that this particular exeunple required 14 comparisons to find the keyword "the" in the character string "that time is the essence" in contrast to the 21 comparisons that were required by a conventional data string processor as shown above. This reduction results from the entire keyword simultaneously being compared with a portion of the data string, instead of being compared one byte at a time.

The detailed operation of the byte mode of the processor is explained with reference Fig. 8 and Table 1. Fig. 8 is a flowchart of the microcode that controls the operation of the processor shown in Fig. 5, and Table 1 includes a software program that is substantially functionally equivalent to the microcode actually used. The operation is explained with reference to Table 1 and not the actual microcode used because the actual microcode would be incomprehensible since it is merely a collection of "1"s and

" 0"s.

DAVN COMPUTER CORP. 1987

At the start of the byte operation of the processor indicated by the start step 210 of Fig. 8, the binary representation of the keyword is stored in the keyword register 136 in the B register file and the binary representation of the data string is stored in the memory 178. Also, the desired bit mask is stored in the bit mas register 126 and in the mask register 190, the desired byte mask is stored in the byte mask register 128 and in the register 156, the address of the byte string in memory 178 to be searched is stored in the address register 122, and the length in bytes of the byte string being searched is stored in the length register 124.

The value of the end-of-string (END) flag indicates whether or not the data string has been completely searched for the presence of the keyword. At step 212 of Fig. 8, the value of the END flag is reset to indicate that the end of the string has not yet been reached. Then, at step 214, the keyword is masked with the bit mask to ensure that the processor ignores any bits in any desired byte as selected by the user. This step is carried out by instructions 2-5 of Table 1. Instructions 2 and 3 supply the bit mask to one data input of the ALU 140 and the keyword to the other data input. Instruction 4 causes the appropriate control signal to be supplied to the ALU so that its two data inputs are logically "anded" together, and the ALU output, which is the value of the masked keyword, is stored in the test register 130 in the A register file via a data path consisting of the F-bus 148, the F-A bus buffer 170, and the A-bus 168. Thus, any bits of the keyword which are to be ignored by the processor are masked to logic "0," and these masked zero bits will force a match with the corresponding bit position in the data string during subsequent comparisons as is explained in more detail below.

Next, at step 216, the J shift register 186 is loaded with the first word of the data string to be tested, "word" meaning a block of binary data eight bytes long to correspond to the eight-byte width of the J shift register 186. The step 216 is accomplished by instruction 6 in Table 1 which moves the contents of the memory at the address where the data string is stored to the J shift register 186 through a path including the memory buffer 182, the M-bus 184, the ALU 140, the F-bus 148, the F-to-B buffer 174, and the B-bus 172. Next, at step 218, the next word, or eight bytes, of the data string are loaded into the K shift register 188 from the memory 178 in a similar manner by instructions 7-11. Specifically, instructions 7-10 cause the address to be incremented by eight so that the incremented address will point to the next eight bytes of the data string in memory 178. Then instruction 11 causes the next eight bytes to be fetched from memory 178 and put into the K shift register 188 via the seune data path as described in connection, with the loading of the J shift register 186.

When the K shift register 188 has just been loaded, at step 220 and by instruction 12, the numeric value eight is stored in the byte count register 134 since there are now eight bytes of string data in the K register 188. Because the contents of the K register 188 are periodically shifted left into the J shift register 186, it is important to know how many bytes of the data string are left in the K register 188 so that the processor will know when to reload the K register with the next portion of the data string.

Next, at step 222, the masked keyword stored in the test register 130 is compared to the portion of the data string stored in the J register 186. This step is implemented by the instructions 13-16 of Table 1. Specifically, instruction 13 causes the masked keyword stored in the test register 130 to be sent to the A latch 142. Then, instruction 14 causes the contents of the J shift register 186 to be moved to the B latch 144 via the B- bus 172. If the BIT MASK ENABLE signal is logic "1," then the contents of the J register 186 are logically "anded" with the bit mask by the AND gates 204 prior to being sent to the B latch 144. At instruction 15, the binary value of the masked keyword is compeuced to the binary value of the masked portion of the data string by providing the ALU FUNCTION signal with the binary values that cause the ALU 140 to perform a bit-by-bit logical "exclusive-or" of its two data inputs. The logical exclusive-or operation, which is conventional and well known, is a sum modulo 2 operation. Thus, a bit-by-bit logical exclusive-or provides a logic "0" output if its two bit inputs are both logic "1" or logic "0," and hence match, and a logic "1" output if its two bit inputs are different. As a result, for each byte of the data string that matches the corresponding byte in the keyword, a logic "0" will be produced in the corresponding byte position.

After the keyword is compared with the portion of the data word in the J register 186, upon a match at step 224 the processor proceeds to the user's program so that the user program may perform its programmed function, for example, replace the keyword that was located with a different word, whereupon the user program returns control to the processor so that any other occurrences of the keyword can be found. The existence of a match is determined by the zero detect circuit at instruction 16. Instruction 16 causes the contents of the ALU 140 to be sent to the zero detect circuit 150. As mentioned above, for each byte position of the ALU 140 in which there was a match, the ALU output will be zero. Consequently, at instruction 17, the zero detect circuit 150 tests each byte of the ALU to determine whether all bytes are zero, in which case all unmasked bytes of the keyword match all unmasked bytes of the data string portion. When the masked bytes are compared by the ALU 140 during its exclusive-or operation, the ALU output corresponding to each masked byte is forced to logic "0," which is the seune logical output that the ALU provides in case of a match. Thus, each logic "1" bit in the byte mask forces a match in its corresponding byte position in the keyword. Upon a match, instruction 18 will ause a return to the user's program, and the user program will return control to the processor at instruction 19. If there is no match, instruction 17 will cause instructions 18 and 19 to be skipped. At step 226, the length of the data string will be decremented by one byte since one byte has just been tested and thus there is one less byte in the data string that needs to be tested. This step is implemented by instructions 20-23. Instruction 20 causes the number one to be moved to the B latch 144, and instruction 21 causes the current data string length to be sent to the A latch 142. Instruction 22 causes the ALU to subtract one from the current length, and the new l h is stored in the length register 124 by instruction 23.

Next, at step 228, the new data string length stored in the length register 124 is tested to determine whether all of the bytes in the delta string have already been compared to the keyword, which will be the case if the numeric value of the length is zero. This is accomplished at instruction 24 which sends the output of the ALU 140 to the zero detect circuit 150. If the value of length is zero, then step 230 is executed, causing the END flag to be set to logic "1" to indicate that the end of the string has been reached, and control is returned to the user's program. This is accomplished by instructions 26 and 27.

If the value of length is nonzero and the data string has not been completely tested, the program branches to step 232 at which the contents of the J and K registers 186, 188 are shifted left by one byte. This is accomplished b instruction 28, which causes a logic "1" S8 signal to be sent to the shift registers 186, 188 so that their contents are shifted left one byte as explained above. The contents of the byte count register 134 are then decremented by on at step 234 to indicate that there is one less byte in the shift register 188 since it has just shifted one of it bytes into the J shift register. This step is accomplished by instructions 29-31.

Next, at step 236, the numeric value of byte count is tested to determine if it is zero, in which case the next eight bytes of the data string need to be moved from the memory 178 into to K shift register 188, and so the program branches back to step 218 so that the K shift register 188 is reloaded. If the byte count is nonzero, the shift register 188 does not need to be reloaded, and the program branches to step 222 so that the current portion of the data string in the J register 186 may be compared to the masked keyword. Step 236 is executed by instructions 32-35. Instruction 32 causes the contents of the ALU 140 to be sent to the zero detect circuit 150. If the zero detect circuit 150 detects a zero, instruction 33 causes a branch to instruction 7. Instruction 34 saves the decremented value of the byte count if it is nonzero, and instruction 35 causes a branch back to instruction 13.

The bit mode of operation of the processor is generally similar to its byte mode of operation. In its bit mode of operation, the processor compares a selected string of bits to determine the presence of a selected keyword. Both the bit string and the keyword are selectable by the user of the processor. The basic process by which the processor tests for the presence of a selected keyword within a selected bit string includes initially loading the J and K shift registers 186, 188 with the first portion of the bit string to be tested. Then, the entire contents of the J shift register 186 are simultaneously compared with the keyword stored in the test register 130. If there is a match, the presence of a match is indicated by the processor. Then, the contents of the J and K registers 186, 188 are shifted left one bit and the contents of the J register 186 are again compared with the contents of the test register. Any match is indicated, and the process is repeated. Periodically, the K register 188 will become empty since its contents are gradually shifted into the J register 186, and so the K register 188 will be periodically reloaded with the next portion of the bit string to be tested. In this manner, the entire keyword is simultaneously compared with a corresponding portion of the bit string. This process reduces the number of comparisons required as shown by the example shown below, in which the keyword is "1101," the bit string is "11001110011011," and each number above the bit string represents the number of comparisons that were required to determine whether or not the keyword matched that particular portion of the bit string:

Comparisons: 1111111111

Bit String: 11001110011011

Keyword: 1101

Note that this particular example required only 10 comparisons to find the keyword "1101" in the bit string "11001110011011" in contrast to the 22 comparisons that were required by a conventional bit string processor as shown above. This reduction results from the entire keyword simultaneously being compared with a portion of the bit string, instead of being compared one bit at a time.

The detailed operation of the bit mode of the processor is very similar to the byte mode, and can be understood with reference to Fig. 9 euid Table 2 set forth below. Fig. 9, which is a flowchart of the microcode that controls the operation of the processor, is very similar to the flowchart of Fig. 8, except that in a number of instances different operations are executed since the processor is in its bit mode of operation and not its byte mode. Likewise, the software implementation set forth in Table 2 is very similar to that of Table 1, so that only the differences need be explained to provide a clear understanding of the detailed operation of the bit mode of operation.

In particular, at step 240 in Fig. 9 and instruction 12 in Table 2, the contents of the bit count register 132 are set to 64 since the K shift register 188 will be shifted one bit at a time and 64 bits are initially loaded into the K register 188. At step 242 and instruction 28, the contents of the J and K shift registers 186, 188 are shifted left one bit instead of byte. At step 244 and instructions 29-31, the contents of the bit count register 132 instead of the byte count register 34 are decremented by one. Finally, at step 246 and instructions 32-35, the conditional branch occurs when the value of the bit count register 132 has reached zero, and not the byte count register 134.

The two modes of operation just described are invoked by a user by including appropriate software instructions in the user's program. Specifically, the byte mode of operation is invoked by the instruction "SCANS" and the bit mode of operation is invoked by the instruction "BITSCAN."

Description of Branch Instructions that Utilize Parallel Byte Checking

The above-described, branch on any hit (BAH) instruction is particularly advantageous in determining when an input character string contains the byte or bytes in the keyword. Thus, by using the BAH instruction, the software can branch to a location to further process the input string. One of the first items of information that is desirable to determine related to the input string is the location of the first byte that matches the corresponding byte of the keyword. For exeunple, many programs parse input data by searching for certain delimiters (e.g., a space, a comma, a period, a semicolon, or the like). When a delimiter is found, the software will cause the input data up to the delimiter to be evaluated in accordance with a predetermine rule. Thereafter, the data following the delimiter may be evaluated according to a separate rule. Thus, it is important to know where the delimiter is located in the input string. The conventional manner of finding delimiters is to take the input string and search through it on a character-by-character basis (i.e., a byte-by-byte basis) until the delimiter is found. As set forth above, the parallel byte comparison operation of the present invention substantially reduces the amount of time required by identifying the multiple byte portion of the input string where the byte is located so that the byte-by-byte comparison need only be performed on that portion of the input string where the byte is located. Nevertheless, in a 64-bit computer having word lengths of eight bytes, each of the eight bytes would have to be compared to find the particular byte where the delimiter is located. A further improvement of the present invention comprises four instructions to greatly improve the efficiency of locating the precise byte where the delimiter is located or to find the first byte following the delimiter.

The first instruction to improve the efficiency of the byte location operations is a "find first hit" (FFH) instruction. The FFH instruction operates upon the hit register portion of the processor status register 100 of Figure 2 to identify the first byte in the input data string that is equal to the byte or bytes to which the input data string is being compared. For example, in the case where a single character (such as a control character or a delimiter) is reproduced in all eight bytes of a 64-bit word, and the input data string is being compared to the single character, the FFH instruction will generate an output code that identifies the location of the first byte that is equal to the single character. As a specific example, assume that the ASCII character code for a space (i.e., the hexadecimal value 20₁₆) is reproduced in all eight bytes of the register A of Figure 2 as follows:

REGISTER A: 2020202020202020 and the following eight-byte portion of an input string, corresponding to "time is ", is loaded into the register B of Figure 2:

REGISTER B: 74696D6520697320

With this input data portion, after performing the exclusive-OR instruction described eύsove, the eight-bit hit register portion of the processor status register 100 of Figure 2 will comprise the following bits:

Hit Register: 1 1 1 1 0 1 1 0

It should be recalled that in accordance with the convention chosen herein, a zero in the hit register portion of the processor status register 100 corresponds to a byte where the input data string matches the comparison byte and a one in the hit register portion of the processor status register 100 corresponds to a byte where the input data string does not match the comparison byte. Thus, there are two zeros in the hit register portion of the processor status register corresponding to the two spaces in the input data string.

Given the foregoing example, the FFH instruction causes a location value of "4" to be generated to indicate that byte 4 of the current portion of the input data string in the register B is the first byte that matches the corresponding byte of the register A. In the preferred embodiment of the present invention, the bytes are numbered from left to right rather than right to left. Thus, "byte 0" refers to the most significant (i.e., leftmost) byte and "byte 7" refers to the least significant (i.e., rightmost) byte in a 64-bit word. It should be noted that this convention is different from the labelling of the bits in which "bit 0" refers to the least significant bit and "bit 63" refers to the most significant bit. This convention also differs from the byte numbering convention illustrated in Figure 3 which refers to the byte number within the register. The choice of conventions relates to the particular application. In the description of the find instructions, the leftmost byte corresponds to the first data received in a string or a string portion and is thus identified as byte 0 since the following bytes are referenced to the first byte.

In the preferred embodiment of the present invention, the value of 4 is stored in a selected register where it is available for subsequent instructions to operate upon the value. For example, the preferred format of the FFH instruction is as follows:

FFH Rxx

where Rxx designates a particular register in the computer. As a specific example, the instruction

FFH R27

when operating on the string example and character example set forth above, will cause the value of 4 to be generated and stored in the register 27 of the computer, where the register 27 is the destination for a particular register in the A or B register file of Figure 5.

From the foregoing, it can be seen that when the leftmost (most significant) byte of data in the register B matches the corresponding byte in the register A, a location value of 0 is generated; when the next most significant byte matches a location value of 1 is generated; and so on. Thus, when the rightmost (least significant) bytes matches, a location value of 7 is generated. If none of the bytes compare, then a location value of 8 is generated to indicate that none of the bytes compared. Thus, a four-bit location value or code provides all the information necessary to determine whether there is a hit, and, if there is a hit, the location of the first hit.

The next novel instruction that is used in conjunction with the hit register portion of the processor status register 100 is a "find first miss" (FFM) instruction. The FFM instruction is similar to the FFH instruction; however, as its name implies, it identifies the location of the first byte in the input data string that is not equal to the byte or bytes to which the input data string is being compared. The FFM instruction has utility, for example, in finding the first non-blank character in an input line. As a specific example, assume once again that the register A of Figure 2 is loaded with eight bytes of data representing eight spaces, as follows:

REGISTER A: 2020202020202020

The following eight-byte portion of an input string, corresponding to " ABC ", is loaded into the register B of Figure 2:

REGISTER B: 2020202020414243

With this input data portion, the pertinent eight-bit hit register portion of the processor status register 100 of Figure 2 will comprise the following bits:

Hit Register: 0 0 0 0 0 1 1 1

where a zero again represents a hit and a one represents a miss. Thus, the location value generated by the FFM instruction will be a "5" to indicate that the first miss is in byte 5.

As with the FFH instruction, the FFM instruction includes a register identifier to designate the register where the location value identifying the byte location of the first miss is to be stored. For example, the instruction:

FFM R23

causes the location value 5 to be stored in the register 23 for the exeunple presented above. Again, a location value between 0 and 7 designates the location of the first miss. A location value of 8 indicates that there were no misses. The present invention also includes a "find first miss after first hit" (FFMAFH) instruction that is useful for finding the beginnings or words in a text streeun and other similar operations. For exeunple, using the space character as an example, it is often desirable to skip to the next space character to find the end of a word and then skip over the next space character or characters to find the beginning of the next word. The FFMAFH instruction performs this operation as a single instruction. This can be understood by referring again to the original example wherein the register A is loaded with eight space characters as follows:

REGISTER A: 2020202020202020

The register B is again loaded with the string portion corresponding to "time is ", as follows:

REGISTER B: 74696D6520697320

With this input data portion, the pertinent eight-bit hit register portion of the processor status register 100 of Figure 2 will again comprise the following bits:

Hit Register: 1 1 1 1 0 1 1 0

Unlike the FFH hit instruction which generated a location value of 4 corresponding to the zero which indicates the byte where the first space character is located, the FFMAFH instruction causes a location value of 5 to be generated which is the first miss (i.e., first non-blank character) after the first hit. Thus, with the location value generated by the FFMAFH instruction, a text processing program can immediately go to the beginning of the next word without having to methodically search each of the eight bytes in the string portion to find the first blank character and then find the first non-blank character that follows the first blank character. As with the previous instructions, the full FFMAFH instruction format specifies the register into which the generated value is to be stored as follows:

FFMAFH Rxx

where Rxx is one of the registers in the register file, as discussed above. A location value between 0 and 7 identifies the location of the first miss after the first hit. A location value of 8 indicates that there was no first miss after a first hit.

A similar instruction to the FFMAFH instruction is a "find first hit after first miss" (FFHAFM) instruction. Unlike the FFMAFH instruction, the FFHAFM instruction looks for the first miss in the input string portion and then finds the first hit thereafter. Using the space character as an example, a text processor can advantageously use this instruction to skip from the end of one word to the end of the next word. For exeunple, all eight bytes of the register A is again filled with data representing the blank character as follows:

REGISTER A: 2020202020202020

The register B is loaded with an eight-byte portion of an input data string having the characters " is the " as follows:

REGISTER B: 2069732074686520

With the foregoing data in the register A and the register B, the hit register portion of the processor status register 100 will comprise the following bits:

Hit Register: 0 1 1 0 1 1 1 0

The FFHAFM instruction will cause a value of 3 to be generated indicating the first hit (byte 3) after the first miss (byte 1) in the eight-byte portion of the data string. As before, the FFHAFM instruction has the format:

FFHAFM RXX

where Rxx designates a particular register into which the generated value will be loaded. A location value between 0 and 7 identifies the location of the first hit after the first miss. A location value of 8 indicates that there was no first hit after a first miss.

The foregoing find instructions also operate with string portions greater than a byte. For example, in some applications, it is desirable to determine whether a sixteen-bit portion of an input data string is equal to another sixteen-bit data string. In such applications, the find instructions operate on a sixteen-bit (i.e., double byte) basis. For example, assume that the register A is loaded with the following data:

REGISTER A: FE3CFE3CFE3CFE3C

Further assume that the register B is loaded with the following data:

REGISTER B: FE78BC3CFE3C8D56

The hit register portion of the processor status register 100 will comprise the following eight bits:

Hit Register: 0 1 1 0 0 0 1 1

Although there a four bytes with hits, only one sixteen-bit portion of the input data string matches the sixteen-bit pattern in the register A. Thus, the FFH instruction will cause a location value of 4 to be generated to indicate that the sixteen-bit portion that compared starts in byte 4 of the input data string. When the FFH instruction is operating on a double-byte basis, the single byte compares of byte 0 and 3 do not cause a location value to be output. For example, the two compares in a row on bytes 3 and 4 will not cause a location value to be generated because the two bytes are in separate sixteen-bit groups. Since the FFH instruction operates on two-byte boundaries, the four possible location value outputs are 0, 2, 4 and 6 when a hit occurs and a value of 8 when no hit occurs.

The find instructions also operate on a half-word (four-byte) basis by comparing 32 bits in the comparison register with 32 bits of the input data string. For example, assume that the register A is loaded with the following string:

REGISTER A: 1234567812345678

Further assume that the input data string is loaded into the register B as follows:

REGISTER B: 1234567A12345678

The hit register portion of the processor status register 100 will comprise the following bits:

Hit register: 0 0 0 1 0 0 0 0

The FFH instruction will generate a location value of 4 to indicate that the second 32-bit half-word matches the comparison string. The two possible location value outputs when a hit occurs are 0 and 4 which are the two half-word boundaries. As before, a location value output of 8 indicates that no hit occurred for the two half-words.

The FFH instruction also operates on a full word basis. When operating on a full word basis, the location value generated by the instruction will either be a 0 to indicate that the entire word matched beginning in byte 0 or an 8 to indicate that the word did not match.

The FFM instruction operates in a similar manner to the FFH instruction on multiple byte lengths.

The FFMAFH and FFHAFM instructions operate on the double-byte length in a manner similar to the operation on a single byte. However, it should be understood that the first miss after a first hit or the first hit after a first miss can only occur in bytes 2, 4 or 6. Thus, the only valid location values generated by these instructions when operating on double-byte lengths are 2, 4, 6 and 8. With respect to half-words, the only valid location value outputs are 4 and 8, since the first hit or miss after the first miss or hit respectively must necessarily occur in the second half-word beginning in byte 4 or not occur at all. With respect to full word operations, the FFMAFH and FFHAFM instructions always generate a location value of 8 since there can be no miss after a full word hit or a hit after a full word miss.

The foregoing find instructions are implemented as single cycle instructions in the present invention in accordance with the block diagram of Figure 10. For simplification only the pertinent portions of the overall processor are shown. In particular, the processor status register 100 is shown along with a portion of the M-bus 184. The present invention further includes an address buffer circuit 500 that receives the eight bits from the hit register portion of the processor status register 100 via an eight-bit bus 502. (Although described above only with respect to the hit register portion, it should be understood that the processor status register 100 includes other status bits such as a carry bit, an overflow bit, a zero bit and a sign bit, that are conventionally available from the arithmetic logic unit of a processor.) The address buffer 500 further receives four bits from an instruction register 504 (shown in phantom) that latches the operation code data from an instruction memory (not shown) and holds it throughout an instruction cycle. The four bits from the instruction register 504 are labelled as A, B, C and D and are provided as inputs to the address buffer on respective lines 510, 511, 512 and 513. The output of the address buffer 500 comprises twelve bits on an address bus 520 that is provided to the address inputs of a PROM (programmable read only memory) 522. In the preferred embodiment described herein, the PROM 522 is a 4096 word by 4-bit PROM. It can thus be seen that the address input to the PROM 522 comprises eight bits from the hit register portion of the processor status register 100 and four bits from the instruction register 504. Preferably, the least significant eight address bits applied to the PROM 522 comprise the hit register bits and the most significant four bits comprise the four bits from the instruction register 504. Also preferably, the eight bits from the hit register portion of the processor status register 100 are interchanged so that the least significant bit (bit 0) of the hit register is connected to address bit 7 of the PROM 522, bit 1 of the hit register is connected to address bit 6 of the PROM 522, and so on such that bit 7 of the hit register is connected to address bit 0 of the PROM 522. The interconnection of the hit register bits to the address bits of the PROM 522 is a matter of convenience in programming the PROM 522. It should be understood that the particular selection of address bits can be varied so long as the PROM 522 is programmed with the correct data for each address.

The PROM 522 provides four output data bits on a four- bit PROM output bus 530. The PROM output bus 522 is provided as an input to a set of tri-state gates 532. The tri-state gates 532 have outputs that are connected to the M-bus 184. The tri-state gates 532 are enabled via an enable line 534 during the execution of the selected find instruction so that the output bits from the PROM 522 are enabled onto the M-bus 184. The enable line 534 is connected to an output of an instruction decode circuit 536 (shown in phantom) which receives instruction data from the instruction register 504 euid provides a plurality of decoded instruction outputs, one of which is the output on the enable line 534. The enable output on the line 534 is activated when the operation code corresponding to the find instructions is decoded by the instruction decode circuit 536. The data on the M-bus 184 is transferred to a selected register via the buffer 170 and the A-bus 168 or via the buffer 174 and the B-bus 172 in a conventional manner in accordance with the destination register portion of the find instruction, as discussed above.

The four most significant address bits to the PROM 522 from the instruction register 502 are responsive to the particular find instruction and to the data length of the compares, as discussed above. Bits A and B, the two most significant pair of bits from the instruction register 502, define the particular find instruction as follows:

Bit A Bit B Instruction

0 0 FFH

0 1 FFM

1 0 FFMAFH

1 1 FFHAFM

The second pair of bits from the instruction register, bits C and D, define the groupings of the data strings for finding the hits or the misses as follows:

Bit C Bit D Group Length

0 0 One Byte

0 1 Two Bytes

1 0 Four Bytes (half word)

1 1 Eight Bytes (full word) Thus, the entire memory area of the PROM 522 can be considered as being divided into four major groups with the addresses 000-3FF (hexadecimal) defining the memory locations for the FFH instruction, the addresses 400-7FF defining the memory locations for the FFM instruction, the addresses 800-BFF defining the memory locations for the FFMAFH instruction, and the addresses COO-FFF defining the memory locations for the FFHAFM instruction. Within each group of memory locations, the bits C and D define the memory locations for the various byte groupings. For example, for the FFH instruction, the memory locations 000- OFF define the memory locations for the single byte FFH instruction, the memory locations 100-lFF define the memory locations for the two byte FFH instructions, the memory locations 200-2FF define the memory locations for the half word (four byte) FFH instructions, eund the memory locations 300-3FF define the memory locations for the full word instructions. Similar groupings are provided for each of the FFM, FFMAFH and FFHAFM instructions.

As can be seen from the foregoing, each of the four byte groupings for each of the four instructions comprises 256 memory locations. The 256 memory locations correspond to each of the 256 possible combinations of the eight bits from the hit register as provided by the eight least significant address bits to the PROM 522. Thus, the PROM 522 provides a unique four-bit output for each combination of data from the hit register for each byte grouping for each of the four instructions. The data programmed into the PROM 522 can be readily determined in accordance with the above-described rules for generating the location values for each instruction and each byte grouping. For convenience. Appendix 3 provides a data listing for the 4096 addresses of the PROM 522 progreunmed in accordance with the above- described rules. In order to more clearly understand the PROM progreunming and the data conventions, a portion of the PROM listing for the addresses 000-OOF for the single byte FFH instruction is shown below:

Hex Inst. Hit Reg. Output

Addr. Bits Bits Code

000 0000 00000000 0

001 0000 00000001 1

002 0000 00000010 0

003 0000 00000011 2

004 0000 00000100 0

005 0000 00000101 1

006 0000 00000110 0

007 0000 00000111 3

008 0000 00001000 0

009 0000 00001001 1 00A 0000 00001010 0

00B 0000 00001011 2

00C 0000 00001100 0

00D 0000 00001101 1

00E 0000 00001110 0

00F 0000 00001111 4

For compactness, only the hexadecimal codes for the addresses are shown in Appendix 3. However, the conversion from the hexadecimal codes to the individual bits is readily accomplished, as illustrated above.

Before discussing the PROM programming in detail, it should be again noted that the hit register bits have been reversed in the PROM addresses set forth above so that the least significant bit of the PROM address corresponds to the most significant bit of the hit register. Furthermore, it is again noted that a hit is represented in the foregoing hit register bits as a zero. Thus, address 000 above corresponds to all eight bytes of the two eight byte data strings being equal. On the other hand, address OOF corresponds to the least significant four bytes being equal (as represented by the zeros) and the four most significant bytes not being equal. Similarly, the address 001 corresponds to the most significant byte not being equal and the seven least significant bytes being equal. Thus, for example, it can be seen that the address 007 produces an location value output of "3" to indicate that byte 3 of the input string is the first byte to be equal to the corresponding byte in the comparison string.

A similar listing for the first sixteen addresses for the single byte FFM instruction is set forth below:

Hex Inst. Hit Reg. Output

Addr. Bits Bits Code

400 0100 00000000 8

401 0100 00000001 0

402 0100 00000010 1

403 0100 00000011 0

404 0100 00000100 2

405 0100 00000101 0

406 0100 00000110 1

407 0100 00000111 0 408 0100 00001000 3

409 0100 00001001 0

40A 0100 00001010 1

40B 0100 00001011 0

40C 0100 00001100 2

40D 0100 00001101 0

40E 0100 00001110 1

40F 0100 00001111 0

It should be noted that the location value output corresponding to the address 400 is an 8 to indicate that there were no misses. The location value outputs for the other addresses indicate the location of the first one counting from the right, thus corresponding to the first byte of the input string that is not equal to the corresponding byte of the comparison string.

As set forth above, the remaining programming of the PROM 522 can be determined in accordance with the above- described rules and can be verified in Appendix 3.

Since the PROM 522 is responsive to the change in the input addresses in accordance with the instruction in the instruction register 502 and in accordance with the hit register portion of the processor status register 100, the data output from the PRQM 522 can readily be provided in a single instruction cycle. Thus, it can be seen that a single find instruction quickly identifies a particular byte in an input string compared to the many instructions required in a conventional processor.

Although described above in connection with a 64-bit processor, it should be understood that the find instructions can be used with processors having more or fewer bits per word with suitable alterations in the circuitry to accommodate the different numbers of bits.

Description of Replicate Instruction

As set forth above, many of the operations performed with the above-described parallel byte processor utilize a repeated character in all eight bytes of a particula register. Although there are known apparatuses and methods for duplicating the data in all eight bytes, such as using shift and OR instructions, the present invention provides a novel replicate instruction that inserts the seune data in all eight bytes in a single instruction cycle.

The novel apparatus for replicating a single byte of data into all eight bytes of the 64-bit word is illustrated in Figure 11. The replication apparatus comprises a replication circuit 550 that has an input connected to receive eight bits (one byte) of data from the F-bus 148 and that generates 64 bits (eight bytes) of data as an output to the M-bus 184. Preferably, the eight bits of input data from the F-bus 148 comprise the eight least significant bits of the F-bus 148 and thus comprise the eight least significant bits of the selected source that is enabled onto the F-bus 148. For example, the data on the F-bus 148 can advantageously be the output of one of the registers in the A register file or the B register file gated through the ALU 140 of Figure 5, or alternatively, can be data from the M-bus 184. The 64 bits of output data generated by the replicate circuit 550 are gated onto the M-bus 184 in response to an active signal on an enable line 552, which is connected to an output of the instruction decode circuit 536 (shown in phantom). The instruction decode circuit 536 decodes the instruction data from the instruction register 504 (Figure 10) and enables the enable line 552 whenever the operation code for the replicate instruction appears in the instruction register 504. Preferεώly, as illustrated in Figure 12, the output circuits of the replicate circuit 550 are tri-state output circuits that enable data onto the M-bus 184 whenever the enable line 552 is active.

The operation of the replicate circuit is illustrated pictorially in Figure 11, wherein a first data word (i.e., eight bytes) on the F-bus 148 is illustrated as having the seven most significant bytes as X's, which designate don't cares in conventional terminology, and having a D in the least significant byte to illustrate the data to be replicated. The output data provided by the replicate circuit 550 onto the M-bus 184 is shown as an eight-byte output data word having a D in each of the eight bytes to indicate that the data byte D has been replicated in all eight bytes. Since the data has been gated onto the M-bus 184, the data can be transferred to a register in the A register file or the B register file in a conventional manner.

Figure 12 illustrates a preferred implementation of the replicate circuit 550. As illustrated, the replicate circuit 550 comprises an eight-bit data buffer 560 that receives the eight bits of data from the eight least significant bits (i.e., bits 0-7) of the F-bus 148 and provides eight buffered output bits. The buffered output bits are provided as inputs to eight sets of tri-state bus drivers 570-577. Each set of tri-state bus drivers 570-577 comprises eight bus driver gates. For example, the tri- state bus drivers 570-577 are advantageously SN74LS244 octal line drivers, available from Texas Instruments Incorporated, or an equivalent circuit. As illustrated, each octal line driver 570-577 receives all eight of the buffered output bits from the data buffer 560. Each octal line driver 570-577 provides one of the eight output bytes of the replicate circuit 550. Thus, the eight bits of each octal line driver 570-577 are connected to a respective eight-bit segment of the M-bus 184. For exeunple, the eight outputs of the octal line driver 570 are connected to bits 0-7 of the M-bus 184, the eight outputs of the octal line driver 571 are connected to bits 8-15 of the M-bus 184, and so on, such that the eight outputs of the octal line driver 577 are connected to bits 56-63 of the M-bus 184.

Each of the octal line drivers has a pair of enable inputs, which, when activated by a logic 0 signal, enable the data inputs onto the respective data outputs. The enable inputs of each octal line driver 570-577 are connected to a replicate enable line 580, which is connected to the output of the instruction decode circuit 536 (shown in phantom). Thus, when the instruction decode circuit 536 decodes the replicate instruction and activates the replicate enable line 580, the eight bits of data input to the data buffer 560 are replicated in the eight output bytes of the M-bus 184, as discussed above in connection with Figure 11. Since there is relatively little propagation delay through the data buffer 560 and the line drivers 570- 577, the replicate instruction is easily accomplished in a single processor instruction cycle.

Description of A Preferr^ti Embodiment of a Rotate/Replicate Circuit

The above-described replicate circuit operates on the least significant eight bits (i.e., the least significant byte) of data on the F bus to reproduce the byte in all eight byte locations of the target register. Although an extremely useful instruction, the limitation to the least significant byte of the F bus requires that a desired byte to be replicated be located in the least significant byte position of the source. In many cases, this may require that a data word be loaded from memory, rotated and placed on the F bus before the desired byte is in the least significant byte position. Alternatively, a separate data word for each byte pattern may be stored in memory with only the least significant byte of the data word comprising significant data. The improved rotate/replicate circuit described hereinafter allows a single 64-bit memory data word to store eight distinct bytes (e.g., eight control characters), and, in one instruction, a selected one of the bytes in the memory word is replicated and transferred to target register. In addition, the rotate/replicate circuit provides the option of working on a two-byte (double byte) basis, four-byte basis (half-word) and eight-byte basis (full word). In the present embodiment, the eight-byte operation rotates the bytes only; however, when the present invention is expanded to a 128-bit word or greater, the eight-byte operation will also provide the replicate function.

Figure 13 is a block diagram of an exemplary rotate/replicate circuit 600 as embodied in the processor of the present invention. As illustrated in Figure 13, the rotate/replicate circuit 600 is positioned to receive data from the memory 178 via the input buffer 182 and the M-bus 184. The rotate/replicate circuit 600 takes the 64 bits of input data on the M-bus 184 auid provides 64 bits of output data on the F-bus 148. The data is routed from the F-bus 148 to a selected destination register, represented by a register 604.

The format of an exemplary load replicate instruction that is advantageously used with the rotate/replicate circuit of Figure 13 has the following format:

LDR.X MEM Ri

where "LDR" specifies the load replicate instruction. The letter "x" following the period represents a selected lette in the instruction format that specifies the number of bytes to be replicated, as determined by a first three-bit control input 610 (labelled "REPL#") to the rotate/replicate circuit 600. In particular, if the letter is a B (i.e., LDR.B), a single byte will be replicated eight times. If the letter is a D (i.e., LDR.D), then two bytes will be replicated four times. If the letter is an H (i.e., LDR.H), then a half- word (four bytes) will be replicated two times. If the letter is a W, then a full word will be replicated once. The "MEM" portion of the instruction is the address of the data word containing the byte or bytes to be replicated, and also specifies the particular starting byte within that data word. Thus, "MEM" also determines the bytes by which to rotate the input data word to the right before replicating if the starting byte is not on a word boundary. The amount of rotation is determined by a second three-bit control input 612 (labelled as "ROTATE") to the rotate/replicate circuit 600. The "Ri" portion of the instruction format identifies the destination register of the replicated bytes.

As illustrated in Figure 14, the rotate/replicate circuit 600 can operate as a one-to-eight multiplexer which can select any one of the eight input bytes and replicate it in the eight output bytes. For example, byte 5 of an input data word from memory having the character "C" stored therein is replicated in the eight bytes of the output data word provided to the F-bus. It should be noted that the most significant byte is designated as byte 0 and the least significant byte is designated as byte 7 (i.e., bytes are numbered from left to right). On the other hand, the most significant bit of a data word is designated as bit 63 and the least significant bit is designated as bit 0 or 00 (i.e., the bits are numbered from right to left).

As illustrated in Figure 15, the rotate/replicate circuit 600 can operate as a one-to-four (or two-to-eight) multiplexer which can select any two of the eight input bytes (e.g, bytes 3 and 4 containing the characters "ED") and replicate the two bytes in the eight output bytes.

As illustrated in Figure 16, the rotate/replicate circuit 600 can operate as a one-to-two (four-to-eight) multiplexer which can select any four bytes (e.g., bytes 3, 4, 5 and 6 containing the characters "EDCB") and replicate the four bytes in the eight output bytes.

Finally, as illustrated by a three-byte rotation to the right in Figure 17, the rotate/replicate circuit 600 can operate as a rotation circuit by which it can rotate the eight input bytes by 1, 2, 3, 4, 5, 6 or 7 bytes. The number of bytes to replicate is specified by the first three-bit REPL# control input 610 into the rotate/replicate circuit 600. In the present embodiment only five of the code combinations are specified for no replication, single- byte replication, two-byte replication, four-byte replication and eight-byte replication (again more meaningful when the word length is increased). The location of the first byte position of the byte or bytes to replicate is specified by the second three-bit ROTATE control input 612 to the rotate/replicate circuit 600. For example, a ROTATE control input of 000 specifies a rotation of zero bytes so that the least significant byte (byte 7) is the least significant replicated byte; a ROTATE control input of 001 specifies a rotation of one byte to the right so that the next least significant byte (byte 6) is the leas significant byte of the replicated word, and so on, such that a ROTATE control input of 111 specifies a rotation of seven bytes to the right so that the most significant byte (byte 0) is in the least significant byte of the replicated word. If the first three-bit control input 610 specifies no replication, then the second three-bit control input 612 operates to specify the number of bytes to rotate.

It should be noted that the replicate instruction operates on byte boundaries irrespective of whether it is replicating a single byte, two bytes, four bytes or eight bytes. If the replicate instruction specifies that two or more bytes are replicated and that the first byte is located such that one or more of the additional bytes are located in a second data word in memory, the two data words are fetched in sequence from memory and formed into a single data word in the input buffer 182. This is illustrated, for example, in Figure 18 wherein a first data word 620, comprising bytes identified as G and H, and a second data word 622, comprising bytes identified as A, B, D, E, and F, are stored in the input buffer 182, as shown. Then, for exeunple if a four-byte replicate instruction specifies byte H of the first data word as the starting position, the rotate/replicate circuit will generate two four-byte data patterns of E, F, G, H and load the two patterns into the destination register 604 as the pattern E, F, G, H, E, F, G, H, as shown. A preferred embodiment of the rotate/replicate circuit 600 is illustrated in Figure 19. As illustrated, the rotate/replicate circuit 600 for the 64-bit embodiment of the present invention comprises eight progreummable logic devices (PLDs) 650, 651, 652, 653, 654, 655, 656, and 657. Each PLD 650-657 has eight inputs and eight outputs. Each input is connected to a selected bit of the M-bus 184, and each output is connected to a selected bit of the F-bus 148. The first PLD 650 controls the data applied to the most significant bits of each output byte (i.e., bit 63 in byte 0, bit 55 in byte 1, bit 47 in byte 2, bit 39 in byte 3, bit 31 in byte 4, bit 23 in byte 5, bit 15 in byte 6, and bit 07 in byte 7). Similarly, the second PLD 651 controls the next most significant bit in each output byte, and so on, such that the seventh PLD 657 controls the least significant bit of each byte (e.g., bit 56 in byte 0, bit 48 in byte 1, bit 40 in byte 2, bit 32 in byte 3, bit 24 in byte 4, bit 16 in byte 5, bit 08 in byte 6, and bit 00 in byte 7). The bits are controlled in these groupings so that each PLD can advantageously be constructed identically, thus reducing the number of different parts to design and manufacture for the rotate/replicate circuit 600. It should be understood from the foregoing description of the rotate replicate circuit that each output byte provided to the F-bus 148 can receive the data from any of the eight input bytes on the M- bus 184 depending upon which byte or bytes are selected to be replicated. Thus, each bit of each output byte must have a selectable path to the bit of corresponding significance in each input byte on the M-bus 184. For exeunple, the most significant bit 63 of byte 0 must have a selectable path to the most significant bit 55 of byte 1, the most significant bit 47 of byte 2, and so on. However, each bit within a particular output byte will have the same byte as its source so that the byte source selection for the bit of a particular byte in the first PLD 350 will be the same as the byte source selection for the bit of that particular byte in the second PLD 351 and so on. For example, if the source for bit 63 is the third byte of the M-bus 184, then the source for bits 62, 61, 60, 59, 58, 57 and 56 is also the third byte of the M-bus 184.

In Figure 19, only the connections to and from the most significant PLD 350 emd the least significant PD 357 are shown. The remaining interconnections can be determined from the bit numbering within the PLDs 351, 352, 353, 354, 355 and 356.

With the foregoing guidelines, the following equations for the least significant PLD 357 can be defined, wherein ROTATE is the value of the three-bit control input 612 that determines the number of bytes to rotate to the right, as discussed above. REPL indicates that there is to be replication and DLB defines a replication length of one byte, DLDB defines a replication length of two bytes, DLHW defines a replication length of four bytes and DLW defines a replication length of eight bytes (redundant for the presently defined 64-bit data word). REPL indicates that there is to be no replication (rotation only). DOUT(x) is the input data bit to the PLD 350 and DOUT(x) is the output data bit for the PLD 357.

The equation for generating output bit 00 from the PLD 357 is as follows:

DOUT(00) = (ROTATE EQ 0) x [(

x DIN(00))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(00)) +(REPL x DIHW x DIN(00)) +(REPL x DLW x DIN(00))] + (ROTATE EQ 1) x [(

x DIN(08))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(08)) +(REPL x DLHW x DIN(08) ) +(REPL x DLW x DIN(08))] + (ROTATE EQ 2) x [(

x DIN(16))

+(REPL x DLB x DIN(16))

+(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(16))

+(REPL x DLW x DIN(16))]

+ (ROTATE EQ 3) x [(

x DIN(24))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(24)) +(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 4) x [(

x DIN(32))

+(REPL x DLB x DIN(32))

+(REPL x DLDB x DIN(32))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(32))]

+ (ROTATE EQ 5) x [(

x DIN(40))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(40)) +(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(40))]

+ (ROTATE EQ 6) x [(R

x DIN(48))

+(REPL x DLB x DIN(48))

+(REPL x DLDB x DIN(48))

+(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(48))]

+ (ROTATE EQ 7) x [(

x DIN(56))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(56))] The equation for generating output bit 08 from the PLs as follows:

D0UT(08) = (ROTATE EQ 0) x [(

x DIN(08))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(08)) +(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(08))j

+ (ROTATE EQ 1) x [(

x DIN(16))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(16)) +(REPL x DLW x DIN(16))]

+ (ROTATE EQ 2) x [(R

x DIN(24))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 3) x [(

x DIN(32))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(32))

+(REPL x DLHW x DIN(32))

+(REPL x DLW x DIN(32))]

+ (ROTATE EQ 4) x [(

x DIN(40))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(40))

+(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(40))]

+ (ROTATE EQ 5) x [(

x DIN(48))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(48))

+(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(48))] + (ROTATE EQ 6) x [(

x DIN(56))

+(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(56))]

+ (ROTATE EQ 7) x [(

x DIN(OO))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(00)) +(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(00))]

The equation for generating output bit 16 from the PLD357 is as follows:

DOUT(16) = (ROTATE EQ 0) x [(

x DIN(16))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(00))

+(REPL x DLHW x DIN(16)) +(REPL x DLW x DIN(16))]

+ (ROTATE EQ 1) x [(

x DIN(24))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(08))

+(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 2) x [(

x DIN(32))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(32))]

+ (ROTATE EQ 3) x [( x DIN(40))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(40))] + (ROTATE EQ 4) x [(

x DIN(48))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(32)) +(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(48))] TATE EQ 5) x [(

x DIN(56))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(40)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(56))]

+ (ROTATE EQ 6) x [(

x DIN(00))

+(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(48)) +(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(00))]

+ (ROTATE EQ 7) x [

x DIN(08))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(08))]

The equation for generating output bit 24 from the PLD357 is as follows:

DOUT(24) = (ROTATE EQ 0) x [(

x DIN(24))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(08))

+(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 1) x [(

x DIN(32))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(32))] + (ROTATE EQ 2) x [(

x DIN(40))

+(REPL x DLB x DIN(16))

+(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(40))

+(REPL x DLW x DIN(40))]

+ (ROTATE EQ 3) x [

x DIN(48))

-(-(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(32)) +(REPL x DLHW X DIN(48)) +(REPL x DLW x DIN(48))]

+ (ROTATE EQ 4) x [(

x DIN(56))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(40)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(56))]

+ (ROTATE EQ 5) x [

x DIN(00))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(48)) +(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(00))]

+ (ROTATE EQ 6) x [(

x DIN(08))

+(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(08))]

+ (ROTATE EQ 7) x [(

x DIN(16))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(00)) +(REPL x DLHW x DIN(16)) (REPL x DLW x DIN(16))] The equation for generating output bit 32 from the PLD357 is as follows:

DOUT(32) - (ROTATE EQ 0) x [(

x DIN(32))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(00)) +(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(32))]

+ (ROTATE EQ 1) x [(

x DIN(40))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(08))

+(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(40))]

+ (ROTATE EQ 2) x [(

x DIN(48))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(16)) +(REPL x DLW x DIN(48))]

+ (ROTATE EQ 3) x [(

x DIN(56))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(56))]

+ (ROTATE EQ 4) x [(

x DIN(00))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(32))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(00))]

+ (ROTATE EQ 5) x [(

x DIN(08))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(40))

+(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(08))] + (ROTATE EQ 6) x [(

x DIN(16))

-(-(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(48)) -I-(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(16))]

+ (ROTATE EQ 7) x [(

x DIN(24))

+(REPL x DLB x DIN(56)) -(-(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(24))]

The equation for generating output bit 40 from the PLD357 is as follows:

DOUT(40) = (ROTATE EQ 0) x [(

x DIN(40))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(08))

+(REPL x DLHW x DIN(08))

+(REPL x DLW x DIN(40))3

+ (ROTATE EQ 1) x [(

x DIN(48))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(16)) +(REPL x DLW x DIN(48))]

+ (ROTATE EQ 2) x [(

x DIN(56))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(56))3

+ (ROTATE EQ 3) x [( x DIN(00))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(32))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(00))] + (ROTATE EQ 4) x [(

x DIN(08))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(40)) +(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(08))3

+ (ROTATE EQ 5) x [(

x DIN(16))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(48)) +(REPL x DLHW x DIN(48))

+(REPL x DLW x DIN(16))]

+ (ROTATE EQ 6) x [

( x DIN(24))

+(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 7) x [ (

x DIN(32) )

+(REPL x DLB x DIN(56))

+(REPL x DLDB x DIN(00))

+(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(32))]

The equation for generating output bit 48 from the PLD357 is as follows:

DOUT(48) = (ROTATE EQ 0) x [(

x DIN(48))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(00))

+(REPL x DLHW x DIN(16))

+(REPL x DLW x DIN(48))]

+ (ROTATE EQ 1) x [(

x DIN(56))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(08))

+(REPL x DLHW x DIN(24))

+(REPL x DLW x DIN(56))] + (ROTATE EQ 2) x [(

x DIN(00))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(16)) +(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(00))]

+ (ROTATE EQ 3) x [(

x DIN(08))

-(-(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(24)) +(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(08))]

+ (ROTATE EQ 4) x [(

x DIN(16))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(32)) +(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(16))]

+ (ROTATE EQ 5) x [(

x DIN(24))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(40)) +(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 6) x [(

x DIN(32))

+(REPL x DLB x DIN(48)) +(REPL x DLDB x DIN(48)) +(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(32))]

+ (ROTATE EQ 7) x [

( x DIN(40))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(56)) +(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(40))] The equation for generating output bit 56 from the PLD357 is as follows:

DOUT(56) - (ROTATE EQ 0) x [(

x DIN(56))

+(REPL x DLB x DIN(00)) +(REPL x DLDB x DIN(08)) +(REPL x DLHW x DIN(24)) +(REPL x DLW x DIN(56))]

+ (ROTATE EQ 1) x [(

x DIN(00))

+(REPL x DLB x DIN(08)) +(REPL x DLDB x DIN(16))

+(REPL x DLHW x DIN(32)) +(REPL x DLW x DIN(00))]

+ (ROTATE EQ 2) x [

x DIN(08))

+(REPL x DLB x DIN(16)) +(REPL x DLDB x DIN(24))

+(REPL x DLHW x DIN(40)) +(REPL x DLW x DIN(08))]

+ (ROTATE EQ 3) x [(

x DIN(16))

+(REPL x DLB x DIN(24)) +(REPL x DLDB x DIN(32))

+(REPL x DLHW x DIN(48)) +(REPL x DLW x DIN(16))]

+ (ROTATE EQ 4) x [(

x DIN(24))

+(REPL x DLB x DIN(32)) +(REPL x DLDB x DIN(40))

+(REPL x DLHW x DIN(56)) +(REPL x DLW x DIN(24))]

+ (ROTATE EQ 5) x [(

x DIN(32))

+(REPL x DLB x DIN(40)) +(REPL x DLDB x DIN(48))

+(REPL x DLHW x DIN(00)) +(REPL x DLW x DIN(32))3 + (ROTATE EQ 6) x [(

x DIN(40))

+(REPL x DLB x DIN(48))

+(REPL x DLDB x DIN(56))

+(REPL x DLHW x DIN(08)) +(REPL x DLW x DIN(40))]

+ (ROTATE EQ 7) x [(

x DIN(48))

+(REPL x DLB x DIN(56)) +(REPL x DLDB x DIN(00)) +(REPL x DIHW x DIN(16)) +(REPL x DLW x DIN(48))]

The equations for the other seven PLDs are identical to the foregoing equations. For example for the PLD 356, substitute 01 for each occurrence of 00, substitute 09 for each occurrence of 08, substitute 17 for each occurrence of 16, substitute 25 for each occurrence of 24, substitute 33 for each occurrence of 32, substitute 41 for each occurrence of 40, substitute 49 for each occurrence of 48, and substitute 57 for each occurrence of 56. Since the equations are identical, the PLDs can be constructed from identical circuits with the only difference being the data inputs and outputs connected to the respective PLDs.

Description of a Switch on First Hit and a Switch on First Miss Instruction

As discussed above the find first hit and miss instructions greatly improve the capabilities of the present invention in rapidly comparing an input data string to a predetermined byte, such as a control word. In the find first instructions, the result of the instruction is placed in a selected register. Thereafter, in subsequent instructions, the selected register can be used to direct an operation at the byte identified by the four-bit location value in the register. The instructions described hereinafter provide a single instruction in which the hit register is evaluated and a multi-way branch is performed based upon the result found in the hit register. By way of example, consider the two 64-bit words illustrated in Figure 20. A first 64-bit word 700 contains eight bytes which advantageously correspond to eight possible control characters that may be present in an input data stream (e.g., a carriage return, a line feed, etc.). The control characters are represented as C1, C2, C3, C4, C5, C6, C7 and C8. A second 64-bit word 704 contains eight bytes which are identical. For exeunple, the eight bytes may comprise eight copies of a character Dl in a data stream stored in memory or the like. The eight copies are advantageously produced using the load/replicate instruction and the rotate/replicate circuit 600 described above. In a typical prior art processor, it would be necessary to compare the data character with each of the eight control characters and branch if the data character compared. For example, an exemplary prior program segment would include the following instruction sequence:

CMPI 'C1' R1 Compare input data to C1

BRCH C_ONE Jump to instruction sequence based upon control character C1.

Otherwise fall through to next instruction

CMPI 'C2' R1 Compare input data to C2

BRCH C_TWO Jump to instruction sequence based upon control character C2.

Otherwise fall through to next instruction

CMPI 'C3' R1 Compare input data to C3

BRCH C_THR

CMPI 'C4' R1 Compare input data to C4

BRCH C_FOU

CMPI 'C5' R1 Compare input data to C3

BRCH C_FIV

CMPI 'C6' R1 Compare input data to C4 BRCH C_SIX

CMPI 'C7' R1 Compare input data to C3

BRCH C_SEV

CMPI 'C8' R1 Compare input data to C4

BRCH C_EIG

[No control character found, perform default routine]

It can be seen that up to sixteen instructions have to be performed to determine whether or not a control character is in the input data stream. The Switch on First Hit instruction of the present invention allows the same determination to be made in three instructions as follows:

LDR.B MEM R1 Load replicated byte into R1

CXOR R1 R2 Where R2 contains the eight control characters

SWFH.B S ±d Multi-way conditional branch on

first hit

[Default instructions to be performed if no hit is found]

As indicated above, the Switch on First Hit instruction has the form "SWFH.x S ±d", where "x" is the width of the comparison to be made (B designating a byte width comparison, D designating a double-byte (two-byte) comparison, H designating a half-word (four-byte) comparison, and W designating a full-word (eight-byte) comparison; S is a scale factor of 2, 4, 8, 16 or 32, for example; and d is a displacement in bytes. As discussed above with respect to the find first instructions, if a single byte is compared, one byte of one register must compare with a byte in the other register in the corresponding byte location. If a double byte is compared, two adjacent bytes in one register must compare with two adjacent bytes in the corresponding locations in the other register. If a half word is compared, four adjacent bytes in one register must compare with four adjacent bytes in the corresponding locations in the other register. If a full word is compared, all eight bytes must compare.

As illustrated in Figure 21, the displacement d determines the location of the beginning of a plurality of branch locations in the code segment containing the code to be executed or the address of the code to be executed if a hit occurs when the Switch on First Hit instruction is executed. A positive displacement d designates the number of bytes after the branch instruction and a negative displacement d indicates the number of bytes before the branch instruction. (It should be noted that the program counter will have advanced when the calculation is made. Thus, the displacement value will be based upon the first byte following the Switch on First Hit instruction.) The scale factor S determines where in the branch locations the next instruction will be taken if there is a successful comparison, and thus provides an index into a code table beginning at the displacement ±d. For example, if the scale factor S is 4, each possible branch location will be space apart by four bytes as illustrated in Figure 21. Thus, if for example, the C6 control character in byte 5 is successfully compared to the data character replicated in the register R2, the Switch on First Hit instruction will branch to the location d+5S (i.e., d+20). The instruction code at the location d+20 will contain instructions specific to the control character C6. For exeunple, if the control character C6 is a carriage return, the instruction sequence will execute instructions unique to the presence of a carriage return in the data stream. Generally, the instruction sequence in the code table will include a branch instruction to a longer code sequence elsewhere in the instructions stored in the memory of the processor.

The Switch on First Hit instruction is implemented by the Switch on First Hit or Miss circuit 720 illustrated in Figure 22. As illustrated, the circuit 720 receives the four-bit output of the First Hit PROM 522 described above in connection with Figure 10. When the Switch on First Hit instruction is decoded by the instruction decode circuit 536 (Figure 10), the instruction register 504 applies the seune address input lines to the PROM 522 as the corresponding Find First Hit instruction. The four output bits from the PROM 522 indicate which byte location has the first hit, or, if the most significant bit of the output is set, that there was no hit. The three least significant bits of the output of the PROM 522 are provided as inputs to a shifter 722 which shifts the bits left by 0, 1, 2, 3, 4 or 5 places to effect a multiplication of 0, 2, 4, 8, 16 or 32, respectively. The number of places shifted, and thus the magnitude of the multiplication is determined by the scale factor S provided a second input to the shifter 722. The shifted (i.e., multiplied) value is provided as an output from the shifter 722 and is provided as an input to an address adder 724. The address adder receives a second input from the program counter and a third input from the displacement value contained in the Switch on First Hit instruction. The three values are added together to provide an effective address output that is the sum of the program counter, the displacement and the scale factor times the byte location, as described above. The effective address output is the next address in memory from which the next instruction is retrieved when a direct addressing mode is used. If indirect addressing is used, the effective address defines a memory location where an address is stored. The stored address is the address of the next instruction.

The most significant output bit of the PROM 522 is shown as a control input to the adder 724 to disable the add function so that the output of the adder 724 is simply the current value of the program counter when no hit is found and the most significant bit is active. Thus, an unsuccessful Switch on First Hit instruction has the effect of an NOP (no operation) instruction. It should be understood that the Switch on First Miss instruction has a similar format:

SWFM.x S ±d

The Switch on First Miss instruction will cause a branch to the first miss, if any, found in the hit register 100 (Figure 10). It should be understood that when the Switch on First Miss instruction is executed, the instruction register 504 (Figure 10) applies an address to the PROM 522 to cause the PROM 522 to determine the first miss and provide the four output bits as described above with respect to the Find First Miss instruction.

Description of Clear Data and Clear Hit/Miss Instructions

The present invention includes eight other instructions that are advantageously used to process data in a character or integer data stream. One example of a frequently occurring operation in data processing is to parse the input data into text words. For exeunple, the text words are typically separated by spaces, periods, carriage returns, or other known delimiters. Thus, when a sequence of eight bytes is evaluated, it is desired to search for a delimiter, for example, a space and save the bytes prior to the first space as a text word, or as the end of a text word if a text word has crossed a data word boundary. The presence of a space in the data word can be determined by the Find First Hit instruction or the Switch on First Hit instruction as described above. For exeunple, as illustrated n Figure 23, a first register R1 750 contains a data string that includes the word "KEY", followed by two spaces (represented as "Sp"), and then followed by three characters that begin the next word. A second register R2 752 contains eight replicated bytes of the space character. Executing the compare exclusive-OR instruction (i.e., CXOR R1 R2) results in the hit register 100 having the bits corresponding to bytes 3 and 4 set. After determining that the first register R1 750 includes at least one space, it is desired to clear the register R1 beginning with the first space so that the register R1 includes only the first word. The present invention includes a Clear Data From First Hit instruction that accomplishes this goal. The Clear Data From First Hit has the format:

CLRDFFH Ri

The result of executing the Clear Data After First Hit on the register R1 is illustrated in Figure 24 wherein the dashes in the five least significant byte positions indicate zeros which represent no characters in the byte locations. It should be understood that the hit register 100 will continue to have the seune bit locations set until another compare exclusive-OR instruction is executed so that the Clear Data From First Hit instruction will operate based upon the previous compare exclusive-OR instruction.

Another useful instruction is a Clear Data To First Hit instruction which operates in a similar manner except that the data is cleared up to the location of the first hit. the Clear Data To First Hit instruction has the following format:

CLRDTFH Ri

Using the register R1 750 and the register R2 752 of Figure 23 as an example, the result of executing the Clear Data To First Hit instruction is illustrated in Figure 25.

A Clear Data First Hit instruction has the format:

CLRDFH Ri

The operation of this instruction is to clear the data byte causing the first hit without disturbing the other data bytes as illustrated in Figure 26 for the data in the register R1 750 and the register R2 752 in Figure 23. A Clear Data From First Miss instruction is included. The Clear Data From First Miss instruction has the format:

CLRDFFM Ri

The operation of this instruction is illustrated by first referring to Figure 27 wherein the register R1 750 comprises an input data word containing three spaces, followed by the text word "KEY", followed by three spaces, and the register R2 752 contains replicated spaces. The result of executing the CXOR R1 R2 instruction followed by the Clear Data From First Miss instruction is illustrated in Figure 28 wherein it can be seen that the data characters following the third space characters have been cleared.

A Clear Data To First Miss instruction has the format:

CLRDTFM Ri

The operation of this instruction on the data in the R1 register in Figure 27 following the compare exclusive-OR instruction is illustrated in Figure 29 wherein it can be seen that the first three space characters are cleared.

A Clear Data First Miss instruction has the format:

CLRDFM Ri

The operation of this instruction is to clear the byte that generated the first miss as illustrated by the clearing of the first non-space character in Figure 30

One pair of instructions provided by the present invention relate to the hit register itself. Often it is desired to determine whether there has been more than one hit. Although the clear data instructions described above can be executed followed by a compare exclusive-OR instruction and a branch on hit instruction, the pair of hit register instructions described below reduce the number of instructions required to accomplish this goal. The first instruction is a Clear First Hit instruction having the format:

CLRFH

Since the instruction operates on the hit register 100, it is not necessary to specify a register with the instruction. As illustrated in Figures 31a and 31b, the Clear First Hit instruction clears the first bit in the hit register without affecting any of the other bits in the hit register so that a Find First Hit instruction, or the like, will now find the next hit, if any, in the hit register. Note that a hit in the hit register 100 is represented by a zero and a miss in the hit register 100 is represented by a one.

Similarly, a Clear First Miss instruction has the format:

CLRFM

As illustrated in Figures 32a and 32b, the Clear First Miss instruction clears the first miss/ in the hit register 100 (i.e., makes the miss look like a hit) so that subsequent Find First Miss instructions, or the like, will find the next miss, if any.

An exemplary circuit 800 that implements the Clear Data From First Hit, Clear Data To First Hit, Clear Data From First Miss, Clear Data To First Miss, Clear First Hit and Clear First Miss instructions is illustrated in Figure 33. The circuit 800 receives data from the PROM 522 described above. When any of the just described eight instructions is executed, the appropriate decoded address signals are applied to the PROM 522 by the instruction register 504 (Figure 10) to cause the PROM 522 to provide the four output bits to indicate the first hit or first miss in accordance with the instruction being executed. The four output bits from the PROM 522 are provided as an input to a pattern generator 810 which generates an eight-bit mask output to a latch 814. The latch 814 provides a corresponding latched eight-bit mask output. Each bit of the mask output from the latch 814 is provided to a respective control input of one byte of the ALU 140. These control inputs are eneώled only when one of the eight clear instructions described above is being executed. Otherwise, the ALU 140 is controlled in a conventional manner. The mask output from the pattern generator 810 is responsive to three-bit control input that varies in accordance with e Clear instruction being executed.

For the Clear Data instructions, if an output bit from the latch 814 is set the output of the corresponding byte of the ALU 140 is cleared to zero irrespective of the data input to the A input of the ALU. The remaining bytes on the A input to the ALU are transferred through without change. When one of the Clear Data instructions is executed, the A input is the designated register (e.g., R1 in the examples presented above), an the output of the ALU 140 will be the same as the input with the selected byte cleared. The output of the ALU is routed back to the designated register via the F-bus 148.

When the Clear First Hit or the Clear First Miss instruction is selected, the output of the hit register 100 is routed through the ALU 140 with one bit of the hit register 100 being routed through a corresponding byte of the ALU 140. If the instruction is the Clear First Hit instruction, the output of the latch 814 is a logical 1 only for the bit to be cleared. This bit is OR'ed with the respective bit of the hit register to set the hit register bit to a one to clear the hit. If the instruction is the Clear First Miss instruction, the output of the latch 814 is a one for all the bits except the bit to be cleared. The output of the latch 814 is AND'ed with the hit register bits so that the selected bit is set to a zero (i.e., the miss is cleared) and the remaining bits remain as they originally were. Each byte of the output of the ALU 140 is examined as if it were a Find First instruction and a bit corresponding to each output byte is stored in the hit register 100. This has the desired effect of clearing a hit or a miss.

The pattern in the pattern generator 810 is illustrated in Figure 34. The leftmost column represents the number encoded by the four input bits from the PROM 522 and thus represent the position of the first hit or miss in accordance with the instruction being executed (an 8 again representing that a respective hit or miss was not found). The second column represents the pattern output for a Clear Data From First Hit or a Clear Data From First Miss instruction. The third column represents the pattern output for a Clear Data First Hit or a Clear Data First Miss instruction. The fourth column represents the pattern output for a Clear Data To First Hit or a Clear Data To First Miss instruction. The fifth column represents the pattern output for a Clear First Hit instruction. The sixth column represents the pattern output for a Clear First Miss instruction. The pattern generator can be implemented as a PROM or a programmable logic device (PLD).

Although the foregoing embodiments of the present invention have been described in connection with a 64-bit data width, it should be understood that the same advantages can be provided in machines having more or fewer bits per data word (e.g., 16-bit, 32-bit and 128-bit parallel processors). The differences between these embodiments include the data width of the buses, buffers, ALU, A and B latches, and registers. Otherwise, the operation of these additional embodiments is the seune.

Modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of the foregoing description. Accordingly, this description is to be construed as illustrative only, and is for the purposes of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure may be varied substantially without departing from the spirit of the invention, and the exclusive use of all modifications which come within the scope of the appended claims is reserved.

PARALLEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER

APPENDIX 1

DAVIN COMPUTER CORPORATION 1987

module _D8C7L8; flag '-r0';

title

'PAU6L8 PAL DESIGN SPECIFICATION

D8C7L8 U186 UN JAN 21, 1987

ALU FUNCTION SELECT BYTE 0,

DAVIN COMPUTER IRVINE, CALIFORNIA

-Translated by TOABEL- ' ;

D8C7L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L - 1,0;

GND,VCC

pin 10,20;

UALU0,UALU1,UALU2,WS0,WS1,DLB, !ICMPR, !UDIV,SHCY,UAS

pin 1,2, 3,4,5, 6,8*9,11, 7;

S0B1.S2B0

pin 12,19;

!ASUBB,ALUSUB,S2B1,S1B1,S1B0,S0B0

pin 13,14,15,16,17,18;

equations

!S0B0 = !UALU0 & !UDIV & !ICMPR

# !UALU0 & !UDIV & ICMPR & !WS0

# WS0 & !UDIV & ICMPR ;

!S1B0 - !UALU1 & !UDIV & !ICMPR

# !UALU1 & !UDIV & ICMPR & !WS1

# WS0 & !UDIV & ICMPR

# UDIV & !SHCY & !ICMPR ;

!S2B0 - !UALU2 & !UDIV & !ICMPR

# !UALU2 & !UDIV & ICMPR & !WS2

# WS2 & !UDIV & ICMPR

# UDIV & !ICMPR ;

ASUBB - !UALU2 & !UALU1 & UALU0 ;

"UDIV —> CONTROL FUNCTION SHT GROUP DIV

"ICMPR —> INSTRUCTION STATUS UPDATE CLASS 3 , 4 OR MATCH ONLY

!S0B1 = !UALU0 & !UDIV & !ICMPR

# !UALU0 & !UDIV & ICMPR & !WS0

# WS0 & !UDIV & ICMPR

# DLB & !UAS & !ICMPR ; !S1B1 - !UALU1 & !UDIV & !ICMPR

# !UALU1 & !WS1 & !UDIV & ICMPR

# WS1 & !UDIV & ICMPR

# UDIV & !SHCY & !ICMPR

# DLB & !UAS & !ICMPR ;

!S2B1 - !UALU2 & !UDIV & !ICMPR

# !UALU2 & !WS2 & !UDIV & ICMPR

# WS2 & !UDIV & ICMPR

# UDIV & !ICMPR

# DLB & !UAS ;

!ALUSUB - UALU2

# !UALU2 & !UALU1 & !UALU0

# !UALU2 & UALU1 & UALU0 :

"UDIV —> CONTROL FUNCTION SHT GROUP DIV "ICMPR —> INSTRUCTION STATUS UPDATE CLASS 3, 4 end_D8C7L8;

module _D13C3R4; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

D13C3R4 U29 UN MAY 23, 1987

Z, U BIT (PSR, USR)

DAVIN COMPUTER IRVINE, CALIFORNIA

-Translated by TOABEL- ';

D13C3R4 device 'P16R4';

"declarations

TRUE,FALSE = 1,0;

H,L- 1,0;

X,Z,C = .X.,.C.;

VCC

pin 20;

CIB, !FDPSR,F14, !ZL, !ZU, !UPDUSR, !UPDBZ, !ENUSET,UDATA3 pin 1,2,3,6,7,8,9,4,5;

!ZERO, !USRZI ,U,USRZ,ZBIT

pin 13,14,15,16,17;

!UPDCZ,!RSTD,F32

pin 12,18,19;

equations

!ZBIT := UPDBZ & !ZERO & !FDPSR

# FDPSR & !F14

# UPDCZ & ZERO & !ZBIT & !FDPSR

# UPDCZ & !ZERO & ZBIT & !FDPSR

# !UPDBZ & !FDPSR & !UPDCZ & !ZBIT

!USRZ := UPDUSR & !ZERO

# !UPDUSR & !USRZ ;

USRZI := UPDUSR & ZERO

# !UPDUSR & USRZI ;

!U := FDPSR & SF32 & !U

# ENUSET & !UDATA3

# RSTD

# !FDPSR & !RSTD & !ENUSET & !U ;

end _D13C3R4 ; module _D13B4L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

D13B4L8 U27,U53 UN FEB 27, 1988

N BIT (HALF WORD, WORD) MICRO N

DAVIN COMPUTER IRVINE, CALIFORNIA

-Translated by TOABEL-';

D13B4L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L- 1,0;

X,Z,C = .X.,.Z.,.C.;

GND,VCC

pin 10,20;

DLW,F63,AL63,BL63,COUT,DLHW,F31,AL31,BL31,CIN32

pin 1,2,3,4,5,6,7,8,9,11;

!UNA, !UNB

pin 12,19;

!ASUBB, !ZEROA, !ZEROB,N_C, !ZU, !ZL

pin 13,14,15,16,17,18;

equations

enable UNA - DLHW ;

UNA = !AL31 & BL31 & ASUBB

# !AL31 & !BL31 & !CIN32 & !ZL & ASUBB

# AL31 & BL31 & CIN32 & !ZL & ASUBB

# F31 & !ASUBB ;

"PIN 12

enable UNB = DLW ;

UNB - !AL63 & BL63 & ASUBB

# JAL63 & !BL63 & !COUT & !ZL & !ZU & ASUBB

# AL63 & BL63 & COUT & !ZL & !ZU & ASUBB

# F63 & !ASUBB ;

enable ZEROA - DLHW ;

ZEROA - DLHW & ZL ;

enable ZEROB - DLW ;

ZEROB - DLW & ZL & ZU ;

"PIN 19

" SAME EQ AS B, DB

end _D13B4L8;

PARALLEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER

APPENDIX 2

DAVIN COMPUTER CORPORATION 1987

module _JPAL; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

JPALR4 PAO AUG 07, 1986

SHIFTER J NUMBER 0 OF 31 (START WITH 0)

*** APPLY TO ALL SHIFTER J 16R4 ****

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

JPAL device 'P16R4';

"declarations

TRUE,FALSE - 1,0;

H,L - 1,0;

VCC

pin 20;

JCLKA,JSOA,JSIA,JS2A,EN_JOUTA,!MULDIVA,JOSL,SHJ02,SHK56 pin 1,2,3,4,5,6,7,8,9;

SHJ00,SHJ01,M0,M1

pin 14,15,16,17;

G,SHK57,B0,B1

pin 11,12,18,19;

JS = [JS2A , JS1A , JS0A] ;

JCK = JCLKA;

OUT = EN_JOUTA ;

MUL = MULDIVA ;

equations

enable B1 - EN_JOUTA ;

!B1 = !!S2A & JS0A & !SHJO1 & !MULDIVA

# JS1A & JS0A & !M1 & !MULDIVA

# JS1A & !JS0A & !SHJ01 & !MULDIVA

# !JS2A & JS1A & IJS0A & !SHJ00 & MULDIVA

# JS2A & JS1A & !JS0A & !SHJ02 & MULDIVA

# JS2A & JS1A & JS0A & !SHJ01 & !MULDIVA

# JS1A & JS1A & JS0A & !M1 & !MULDIVA ;

"OUT J,BIT SCAN

"BIT,BYT SCN /(MSK*SHJ01)

"SHL J, SHR J

"DIV

"MUL

"BYT SCAN

enable BO = EN_JOUTA ;

!BO = !JS2A & JS0A & !SHJ00 & !MULDIVA

# JS1A & JS0A & !M0 & !MULDIVA

# JS1A & !JS0A & !SHJ00 & !MULDIVA # !JS2A & JS1A & !JS0A & !JOSL & MULDIVA

# JS2A & JS1A & !JS0A & !SHJ01 & MULDIVA

# JS2A & JS1A & JS0A & !SHJ00 & !MULDIVA

# JS1A & JS1A & JS0A & !M0 & !MULDIVA ;

"OUT J,BIT,BYT SCAN

"BIT,BYT SCN /(MSK*SHJ00)

"SHL J, SHR J

"DIV

"MUL

"BYT SCAN

!M1 := JS2A & 1JS1A & JS0A & !B1

# !JS2A & !M1

# JS1A & !M1

# !JS0A & !M1 ;

"LD MASK

"(ALL OTHER

"CASE EQ

"TO /M1)

!MO := JS2A & !JS1A & JS0A & !B0

# !JS2A & !M0

# JS1A & !M0

# !JS0A & !M0 ;

"LD MASK

"(ALL OTHER

"CASE EQ

"TO /MO)

!SHJ01 := !JS2A & !JS1A & !SHJ01

# !JS2A & JS1A & !SHJ00

# JS2A & !JS1A & !JS0A & !B1

# JS2A & !JS1A & JSOA & !SHJ01

# JS2A & JS1A & !JS0A & !SHJ02

# JS2A & JS1A & JS0A & !SHK57 ;

"HOLD J, OUT J

"SHL J, BIT SCAN

"LOAD J

"LD MSK,

"SHR J

"BYT SCAN

!SHJ00 := !JS2A & !JS1A & !SHJ00

# !JS2A & JS1A & !J0SL

# JS2A & !JS1A & !JS0A & !B0

# JS2A & !JS1A & JS0A & !SHJ00

# JS2A & JS1A & !JS0A & !SHJ01

# JS2A & JS1A & JS0A & !SHK56 ;

"HOLD J, OUT J

"SHL J, BIT SCAN

"LOAD J

"LD MSK,

"SHR J

"BYT SCAN " JS = [JS2A , JS1A , JS0A] ; " JCK = JCLKA;

" OUT = EN_JOUTA ;

" MUL = MULDIVA ;

end _JPAL; module _KPAL; flag '-r0';

title

'PAL20R4 PAL DESIGN SPECIFICATION

KPALR4 PAO OCT 29, 1986

SHIFTER K NUMBER 15 OF 15 (START WITH 0) *** APPLY TO SHK 2 TO 15 ****

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

KPAL device 'P20R4' ;

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

vcc

pin 24;

KCLKB, !KSOB, !KSIB, !KS2B, !EN_KOUTB, !KCLRB

pin 1,2,3,4,5,6;

SHK59,K63SR,SHK55,SHK54,SHK53,G,SHK52

pin 7,8,9,10,11,13,14;

SHK60, SHK61,SHK62,SHK63

pin 17,18,19,20;

B60,B61,B62,B63

pin 15,16,21,22;

KC = KCLKB ;

KS = [KS2B , KS1B , KSO

0 = EN KOUTB ;

KL = KCLRB ;

K63 = SHK63

K62 = SHK62

K61 = SHK61

K60 = SHK60

K59 = SHK59

SR = K63SR

K55 = SHK55

K54 = SHK54

K53 = SHK53

K52 = SHK52

BIN = [B63,B62,B61,B60];

BOUT = [B63,B62,B61,B60];

quations

enable B63 = EN_KOUTB ;

!B63 = !SHK63 & !KCLRB

# KCLRB ;

"OUT K

enable B62 = EN_ KOUTB ; !B62 = !SHK62 & !KCLRB

# KCLRB ;

"OUT K

enable B61 = EN_KOUTB ;

!B61 = !SHK61 & !KCLRB

# KCLRB ;

"OUT K

enable B60 = EN_KOUTB ;

!B60 - !SHK60 & !KCLRB

# KCLRB ;

"OUT K

!SHK63 := !KSOB & !SHK63

# !KS2B & !KS1B & KSOB & !B63

# !KS2B & KS1B & KSOB & !SHK62

# KS2B & !KS1B & KSOB & !K63SR

# KS2B & KS1B & KSOB & !SHK55 ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN, SH K LEFT BYT

"K CLEAR

!SHK62 := !KSOB & !SHK62

# !KS2B & !KS1B & KSOB & !B62

# !KS2B & KS1B & KSOB & !SHK61

# KS2B & !!S1B & KSOB & !SHK63

# KS2B & KS1B & KSOB & !SHK54 ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN, SH K LEFT BYT

"K CLEAR

!SHK61 := !KSOB & !SHK61

# !KS2B & !KS1B & KSOB & !B61

# !KS2B & KS1B & KSOB & !SHK60

# KS2B & !KS1B & KSOB & !SHK62

# KS2B & KS1B & KSOB & !SHK53 ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN, SH K LEFT BYT

"K CLEAR

!SHK60 := !KSOB & !SHK60

# !KS2B & !KS1B & KSOB & !B60

# !KS2B & KS1B & KSOB & !SHK59

# KS2B & !KS1B & KSOB & !SHK61

# KS2B & KS1B & KSOB & !SHK52 ; "HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN, SH K LEFT BYT

"K CLEAR

KC = KCLKB ;

KS = [KS2B , KSIB , KSOB] ;

O = EN KOUTB ;

KL = KCLRB ;

K63 = SHK63;

K62 = SHK62;

K61 = SHK61;

K60 = SHK60;

K59 = SHK59;

SR = K63SR;

K55 = SHK55;

K54 = SHK54;

K53 = SHK53;

K52 = SHK52;

BIN = [B63,B62,B61,B60];

BOUT = [B63,B62,B61,B60]; testvectors

end KPAL; module _KPALS; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

KPALSR4 PAO OCT 29, 1986

SHIFTER K NUMBER 0 OF 15 (START WITH 0) >>>APPLY TO SHK 0 & 1 <<<

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

KPALS device 'P16R4';

"declarations

TRUE,FALSE = 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

VCC

pin 20;

KCLKA, !KS0A, !KS1A, !KS2A, !EN_KOUTA, !KCLRA,KOSL,SHK04

pin 1,2,3,4,5,6,7,8;

SHK00, SHK01, SHK02,SHK03

pin 14,15,16,17;

G,B0,B1,B2,B3

pin 11,12,13,18,19;

KCK = KCLKA ;

KS = [KS2A , KS1A , KS0A3 ;

OUT = EN_KOUTA ;

CLR = KCLRA ;

SKO = SHK00;

SKI = SHK01

SK2 = SHK02

SK3 = SHK03 equations

enable B3 = EN_KOUTA ;

!B3 = !SHK03 & !KCLRA

# KCLRA ;

"OUT K

enable B2 = EN_KOUTA ;

!B2 = !SHK02 & !KCLRA

# KCLRA ;

"OUT K

enable B1 = EN_KOUTA ;

JB1 = !SHK01 & !KCLRA

# KCLRA ;

"OUT K enable BO = EN_KOUTA ;

!BO = !SHK00 & !KCLRA

# KCLRA ;

"OUT K

!SHK03 :- !KS0A & !SHK03

# !KS2A & !KS1A & KS0A & !B3

# !KS2A & KS1A & KS0A & !SHK02

# KS2A & !KS1A & KS0A & !SHK04

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK02 := !KS0A & !SHK02

# !KS2A & !KS1A & KS0A & !B2

# !KS2A & KS1A & KS0A & !SHK01

# KS2A & !KS1A & KS0A & !SHK03

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK01 := !KS0A & !SHK01

# !KS2A & !KS1A & KS0A & !B1

# !KS2A & KS1A & KS0A & !SHK00

# KS2A & !KS1A & KS0A & !SHK02

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK00 := !KS0A & !SHK00

# !KS2A & !KS1A & KS0A & !B0

# !KS2A & KS1A & KS0A & !K0SL

# KS2A & !KS1A & KS0A & !SHK01

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR " KCK = KCLKA ;

" KS = [KS2A , KS1A , KSOA] ; " OUT = EN_ KOUTA ;

" CLR = KCLRA ;

" SKO = SHK00

" SKI = SHK01

" SK2 = SHK02

" SK3 = SHK03

test_vectors

end _KPALS;

module _SH12B5L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH12B5L8 PAO MAY 05, 1986

SHIFTER CARRY GENERATOR

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

SH12B5L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND,VCC

pin 10,20;

!SHRIGHTX, !SHLEFT,SD1, SD0, !SHWAITRQ, !SHF_OP, SHK00, !MUL, !LONG, SHJ00 pin 1,2,3,4,5,6,7,8,9,11;

!SHCYX

pin 12 ;

SHJ07 , SHJ15 , SHJ31 , SHJ63 , !UCY

pin 13,14,15,16,18;

SR = SHRIGHTX ;

SL = SHLEFT ;

J63 = SHJ63

J31 = SHJ31

J15 = SHJ15

J7 = SHJ07

J0 = SHJ00

K0 = SHK00

SD = [ SD1 , S00 ];

equations

SHCYX = SHLEFT & SD1 & SD0 & SHJ63 & SHWAITRQ

# SHLEFT & SD1 & !SD0 & SHJ31 & SHWAITRQ

# SHLEFT & !SD1 & SD0 & SHJ15 & SHWAITRQ

# SHLEFT & !SD1 & !SD0 & SHJ07 & SHWAITRQ

# SHRIGHTX & !LONG & !MUL & SHJOO & SHWAITRQ

# SHRIGHTX & !LONG & MUL & SHK00 & SHWAITRQ

# SHRIGHTX & LONG & SHK00 & SHWAITRQ;

"WORD & LONG LEFT

"HWORD LEFT

"DBYTE LEFT

"BYTE LEFT

"NOT LONG RIGHT NOT MUL

"NOT LONG RIGHT MUL

"LONG RIGHT

" ALL OF ABOVE ALSO QUALIFIED BY SHWAITRQ " SR = SHRIGHTX ;

" SL = SHLEFT ;

" J63 = SHJ63 ;

" J31 = SHJ31 ;

" J15 = SHJ15 ;

" J7 = SHJ07 ;

" J0 = SHJOO ;

" SD = [ SD1 , SD0 ]: " K0 = SHK00 ;

test_vectors

end _SH12B5L8;

module _SH12B7R4; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

SH12B7R4 PAO MAY 12, 1987

BEGIN OF SHIFTER OPERATION INDICATER

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH12B7R4 device 'P16R4';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

VCC

pin 20;

C2SHB, !SHRIGHTX,UGR2,UGR1,UGR0, !UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X pin 1,2,3,4,5,6,7,8,9;

!SHF_OP, !SHCYX, !SHCYXD,DIVTST

pin 17,16,15,14 ;

!G G, CTRCY, !JOSLB, !SHCY,C2SHBX

pin 11,12,13,18,19;

C2 = C2SHB ;

UGR = [UGR2 , UGR1 , UGR0 ];

equations

DIVTST := !GCTRCY & JOSLB

# GCTRCY & DIVTST ;

SHCYX := SHCY ;

SHCYXD := !UGR2 & UGR1 & UGR0 & SHCYX

# !( !UGR2 & UGR1 & UGR0 ) & SHCYXD ;

" WHEN IN SHIFTER GROUP UPDATE SHCYXD

" WHEN NOT IN SHIFTER GROUP HAVE SHCYXD THE SAME

SHF_OP := !UGR2 & UGR1 & UGR0 ;

C2 = C2SHB ;

UGR = [UGR2 , UGR1 , UGR0 ];

test_vectors

end_SH12B7R4;

module _SH11C7L8 ; flag ' -r0 ' ;

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11C7L8 PAO AUG 08, 1986

SHIFTER ENABLE, DIRECTION & DATA LENGTH CONTROL

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

SH11C7L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

UGR2 ,UGR1,UGR0,MEQ1,UDATA5,UDATA4,GCTRSGN,I5, I4,UDT0

pin 1,2,3,4,5,6,7,8,9,11;

!SHLEFT, ! SHRIGHTY

pin 12,19;

UDT1,UDT2 , SD0, SD1, !SHRIGHTX, !EN_SHIF

pin 13,14,15,16,17,18;

UGR = [UGR2 , UGR1 , UGR0 ];

SHR = [SHRIGHTX , SHRIGHTY ] ;

SHL = SHLEFT ;

GSIGN = GCTRSGN ;

UDT = [UDT2,UDT1,UDT0];

equations

"COMMENT: SD0, SD1 ARE DECODED FROM U-CODE TO INDICATE THE

" DATA LENGTH.

"

" SD1 SD0 LENGTH

" -------------------------- " 0 0 BYTE

" 0 1 DBYTE

" 1 0 HWORD

" 1 1 WORDe

EN_SHIF - !UGR2 & UGR1 & UGR0 & !MEQ1 ;

"EN SHJK

SHRIGHTX = !UGR2 & UGR1 & UGR0 & !MEQ1 & UDATA5 & !UDATA4

# SUGR2 & UGR1 & UGR0 & !MEQ1 & !UDATA5 & UDATA4 & !GCTRSGN ;

"EN SHJK

"DIR RIGHT

SHRIGHTY = !UGR2 & UGR1 & UGR0 & !MEQ1 & UDATA5 & !UDATA4

# !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDATA5 & UDATA4 & !GCTRRGN ; "EN SHJK

"DIR RIGHT

SHLEFT - !UGR2 & UGR1 & UGR0 & !MEQ1 & UDATA5 & UDATA4

# !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDATA5 & UDATA4 & GCTRSGN

"EN SHJK

"DIR LEFT

!SD0 - !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDT2 & UDT1 & !UDT0

# !UGR2 & UGR1 & UGR0 & !MEQ1 & UDT2 & I5 & I14

# !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDT2 & !UDT1 & !UDT0

# !UGR2 & UGR1 & UGR0 & !MEQ1 & UDT2 & !I5 & !I4 ;

"NOT HWORD

"& BYTE

!SD1 - !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDT2 & !UDT1 & UDT0

# !UGR2 & UGR1 & UGR0 & !MEQ1 & TJDT2 & 115 & 14

# !UGR2 & UGR1 & UGR0 & !MEQ1 & !UDT2 & !UDT1 & !UDT0

# !UGR2 & UGR1 & UGR0 & !MEQ1 & UDT2 & 115 & 114 ;

"NOT DBYTE

"& BYTE

UGR = [UGR2 , UGR1 , UGR0 ] ;

SHR = [SHRIGHTX , SHRIGHTY ] ;

SHL = SHLEFT ;

GSIGN = GCTRSGN ;

UDT = [UDT2,UDT1,UDT0];

test_vectors

end _SH12B5L8 ; module _SH12C1L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH12C1L8 PAO AUG 08, 1986

SHIFTER K FUNCTION CONTROL

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

SH12C1L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

!SHLEFT, !SHRIGHTX,ZFG, !GCTRCY

pin 1,2,3,4;

!UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X, !LD_SHK, !EN_SHIF

pin 5,6,7,8,9,11;

!KSIB, !KS1A

pin 12,19;

!KS2B, !KS2A, !KS0B, !KS0A

pin 15,16,17,18;

SL = SHLEFT ;

SR = SHRIGHTX

GC = GCTRCY ;

UDATA = [ UDATA3X UDATA2X , UDATA1X , UDATA0X ];

LDK = LD SHK;

ENSH = EN SHIF;

equations

"NOTE SHLEFT, SHRIGHTX ARE ALSO USED AS QUALIFY SIGNAL FOR SHIFTER FUNCTION KSOA = LD_SHK

# !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & EN_SHIF & !CGTRCY

# !UDATA3X & UDATA2X & !UDATA1X & EN_SHIF & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & EN_SHIF & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & SHLEFT & !GCTRCY

# UDATA2X & UDATA1X & !UDATA0X & SHLEFT & !ZFG & !GCTRCY ;

"LOAD K

"LOAG ROTATE LEFT,RIGHT

"LONG LSH,ASH,LEFT,RIGHT

"MUL,DIV

"SHK LEFT BYTE

"BIT,BYT SCAN

KS1A = !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHLEFT & !GCTRCY

# !UDATA3X & UDATA2X & !UDATA1X & SHLEFT & !GCTRCY # UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & SHLEFT & !GCTRCY

# UDATA2X & UDATA1X & !UDATA0X & SHLEFT & !ZFG & !GCTRCY ;

"LOAG ROTATE LEFT

"LONG LSH,ASH,LEFT

"DIV

"SHK LEFT BYTE

"BIT,BYT SCAN

KS2A - !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHRIGHTX & !GCTRCY

# !UDATA3X & UDATA2X & !UDATA1X & SHRIGHTX & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

& SHRIGHTX & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X £c SHLEFT & !GCTRCY

# UDATA3X & UDATA2X & UDATA1X & !UDATA0X

& SHLEFT & !ZFG & !GCTRCY ;

"LOAG ROTATE RIGHT

"LONG LSH,ASH,RIGHT

"MUL

"SHK LEFT BYTE

"BYT SCAN

KSOB = LD_SHK

# !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & EN_SHIF & !GCTRCY

# !UDATA3X & UDATA2X & !UDATA1X & EN_SHIF & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & EN_SHIF & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & SHLEFT & !GCTRCY

# UDATA2X & UDATA1X & !UDATA0X & SHLEFT & !ZFG & !GCTRCY;

"LOAD K

"LOAG ROTATE LEFT,RIGHT

"LONG LSH,ASH,LEFT,RIGHT

"MUL,DIV

"SHK LEFT BYTE

"BIT,BYT SCAN

KSIB = !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHLEFT & !GCTRCY

# !UDATA3X & UDATA2X & !UDATA1X & SHLEFT & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & SHLEFT & !GCTRCY

# UDATA2X & UDATA1X & !UDATA0X & SHLEFT & !ZFG & !GCTRCY ;

"LOAG ROTATE LEFT

"LONG LSH,ASH,LEFT

"DIV

"SHK LEFT BYTE

"BIT,BYT SCAN

KS2B - !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHRIGHTX & !GCTRCY

# !UDATA3X & UDATA2X & !UDATA1X & SHRIGHTX & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

& SHRIGHTX & !GCTRCY

# UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & SHLEFT & !GCTRCY

# UDATA3X & UDATA2X δ< UDATA1X & !UDATA0X

& SHLEFT & !ZFG & !GCTRCY ; "LOAG ROTATE RIGHT

"LONG LSH,ASH,RIGHT

"MUL

"SHK LEFT BYTE

"BYT SCAN " SL - SHLEFT ;

" SR - SHRIGHTX ;

" GC - GCTRCY ;

" UDATA - [ UDATA3X , UDATA2X , UDATA1X , UDATA0X ]; " LDK - LD_SHK;

" ENSH - EN SHIF;

test_vectors

(

end _SH12C1L8 ; module _SH11C5L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11C5L8 PAO MAY 07, 1987

SHIFTER K LINK CONTROL NUMBER 1 OF 2 (U50)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH11C5L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

!UCY, !SHLEFT, !SHCYX,UDATA6 , SHJ63, !SHRIGHTY

pin 1,2,3,4,5,6;

!UDATA3X, !UDATA2X, !UDATA1X, !UDATA0X

pin 7,8,9,11;

KOSL, !SHCYJ

pin 12,19;

!MULDIVD, !MULDIVC, !MULDIVB, !MULDIVA,SHK00, !SHF_OP

pin 13,14,15,16,17,18;

UDATA = [ UDATA3X , UDATA2X , UDATA1X , UDATAOX ] ;

SL = SHLEFT ;

SR = SHRIGHTY ;

MDABCD = [MULDIVA , MULDIVB , MULDIVC , MULDIVD] ;

OP = SHF_OP ;

KO = SHK00 ;

equations

!KOSL = SHLEFT & !UDATA6 & !SHJ63

& !UDATA3X & !UDATA2X & UDATA1X & UDATA0X

# SHLEFT & !UDATA3X & UDATA2X & !UDATA1X

# SHLEFT & UDATA2X & UDATA1X & !UDATA0X

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & !SHF_OP & !SHK00

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHF_OP & UCY

# !SHF_OP & SHLEFT & UDATA6 & !UCY

& !UDATA3X & !UDATA2X & UDATA1X & UDATA0X

# SHF_OP & SHLEFT & UDATA6 & !SHCYX

& !UDATA3X & !UDATA2X & UDATA1X & UDATA0X ;

"LONG ROL, SHJ63

"LONG LOG.ARTH SHL, 0 IN

"BIT,BYT SCAN, 0 IN

"DIV 1ST SHK00 "DIV REST CYC !UCY

"LONG ROL THRU CY FIRST CYCLE, KOSL = UCY

"LONG ROL THRU CY RESET OF CYCLE , KOSL = SHCYX

SHCYJ - SHFJDP & SHCYX

# !SHF_OP & UCY ;

"DIV

"MUL

MULDIVA = UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X & SHRIGHTY ;

"DIV

"MUL

MULDTVB = UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X & SHRIGHTY ;

"DIV

"MUL

MULDIVC = UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X & SHRIGHTY ;

"DIV

"MUL

MULDIVD = UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SHLEFT

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X & SHRIGHTY ;

"DIV

"MUL

" UDATA = [ UDATA3X UDATA2X , UDATA1X , UDATA0X ] ;

" SL =SHLEFT ;

" SR =SHRIGHTY ;

" MDABCD = [MULDIVA , MULDIVB , MULDIVC , MULDIVD];

" OP = SHFJDP ;

" KO = SHK00 ;

test_vectors

end _SH12B5L8;

module _SH11B3L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11B3L8 PAO MAY 06, 1987

SHIFTER J LINK CONTROL (Η63)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH11B3L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

!SHRIGHTY,SD0,SD1.UDATA6, !UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X, SHJOO, ! SHCYX pin 1,2,3,4,5,6,7,8,9,11;

J15SR.J31SR

pin 12,19;

!SHCYJ , SHJ31, SHJ15 , !UCY, SHJ32 , SHJ16

pin 13,14,15,16,17,18;

SRY = SHRIGHTY ;

SD = [ SD1 , SD0];

UDATA = [ UDATA3X , UDATA2X , UDATA1X , UDATA0X ] ;

J0 = SHJ00

J15 = SHJ15

J16 = SHJ16

J31 = SHJ31

J32 = SHJ32 equations

!J15SR = SHRIGHTY & !SD1 & SD0 & !UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & SD0 & 1SHJ15 & !UDATA3X & !UDATA2X & !UDATA1X & UDATA0X

# SHRIGHTY & !SD1 & SD0 & !UDATA6 & !SHJOO & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & SD0 & UDATA6 & 1SHCYJ & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & SD0 & UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

# SHRIGHTY & 1SHJ16 & SD1 ;

"LOG SHR DBYTE, 0 IN

"ASH SHR DBYTE,MSB SELF

"ROR DBYTE, SHJOO

"RRC DBYTE, SHCYJ

"MUL DBYTE,0 IN

"DIR RIGHT W,HW , SHJ16 !J31SR - SHRIGHTY & SD1 & !SD0 & !UDATA3X & !UDATA2X & !UDATA1X & !UDATA # SHRIGHTY & SD1 & !SD0 & 1SHJ31 & !UDATA3X & !UDATA2X & !UDATAl & UDATA0X

# SHRIGHTY & SD1 & !SD0 & !UDATA6 & !SHJOO & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & SD1 & !SD0 & UDATA6 & !SHCYJ & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & SD1 & !SD0 & UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

# SHRIGHTY & !SHJ32 & SD1 & SD0 ;

"LOG SHR HWORD, 0 IN

"ASH SHR HWORD,MSB SELF

"ROR HWORD,SHJ00

"RRC HWORD,SHCYJ

"MUL HWORD,0 IN

"DIR RIGHT W.SHJ32

" SRY - SHRIGHTY ;

" SD - [ SD1 , SD0] ;

" UDATA - [ UDATA3X , UDATA2X , UDATA1X , UDATA0X ] ;

" J0 = SHJ00

" J15 = SHJ15

" J16 = SHJ16

" J31 = SHJ31

" J32 = SHJ32

test_vectors

end _SH12B5L8;

module _SH11B1L8; flag ' -r0' ;

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11B1L8 PAO MAY 06, 1987

SHIFTER J LINK CONTROL (U62)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH11B1L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

!SHRIGHTY,SD0,SD1,UDATA6, !UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X.SHJ00, !SHCY pin 1,2,3,4,5,6,7,8,9,11;

J63SR.J7SR

pin 12,19;

SHJ63 , SHJ08 , SHK00 , !UCY,SHJ07, 3 SHCYJ

pin 13,14,15,16,17,18;

SRY = SHRIGHTY ;

SD = [ SD1 , SD03 ;

UDATA = [ UDATA3X , UDATA2X , UDATA1X , UDATA0X j ;

J0 = SHJ00

J7 = SHJ07

J8 = SHJ08

J63 = SHJ63

K0 = SHK00

equations

!J7SR = SHRIGHTY & !SD1 & !SD0 & !UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & !SD0 & !SHJ07 & !UDATA3X & !UDATA2X & !UDATA1X & UDATA0X

# SHRIGHTY & !SD1 & !SD0 & !UDATA6 & !SHJOO & !UDATA3X δ: !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & !SD0 & UDATA6 & !SHCYJ & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & !SD1 & !SD0 δe UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

# SHRIGHTY & !SHJ08 & SD1

# SHRIGHTY & !SHJ08 & SD0 ;

"LOG SHR BYTE, 0 IN

"ASH SHR BYTE,MSB SELF

"ROR BYTE, SHJOO

"RRC BYTE, SHCYJ

"MUL BYTE.O IN

"DIR RIGHT W,HW , SHJ08

"DIR RIGHT W.DB , SHJ08 !J63SR - SHRIGHTY & SD1 & SD0 & !UDATA3X & !UDATA1X & !UDATA0X

# SHRIGHTY & SD1 & SD0 & !SHJ63 & !UDATA3X & !UDATA1X

& UDATA0X

# SHRIGHTY & SD1 & SD0 & !UDATA6 & !SHJ00 & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X

# SHRIGHTY & SD1 & SD0 & !UDATA6 & !SHK00 & !UDATA3X & !UDATA2X & UDATA1X & UDATA0X

# SHRIGHTY & SD1 & SD0 & UDATA6 & !SHCYJ & !UDATA3X & !UDATA2X

& UDATA1X

# SHRIGHTY & SD1 & SD0 & UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X ;

"(LONG) LOGIC SHR WORD, 0 IN

"(LONG) ASH SHR WORD,MSB SELF

"ROR WORD,SHJ00

"LONG ROR WORD,SHJ00

"RRC.LRRC WORD,SHCYJ

"MUL WORD.O IN

SRY - SHRIGHTY ;

SD - [ SD1 , SD0] ;

UDATA - [ UDATA3X , UDATA2X , UDATA1X , UDATA0X ] ;

J0 - SHJ00

J7 - SHJ07

J8 - SHJ08

J63 - SHJ63

K0 - SHK00

testvectors

end _SH12B5L8;

module _SH12C3L8 ; flag ' -r0 ' ;

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH12C3L8 PAO OCT 28, 1986

SHIFTER FUNCTION I/O CONTROL (U8)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH12C3L8 device 'P16L8';

"declarations

TRUE , FALSE - 1 , 0 ;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20 ;

!SHLEFT, 1 SHCY, !SHCYX, !GCTRCY,ZFG

pin 1,2,3,4,5;

!UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X.C2SHB

pin 6,7,8,9,11;

!SHWAITRQ, 1ENA_JOUT

pin 12,19;

UGR2 ,UGR1,UGR0,MEQ1

pin 13,14,17,18;

SL = SHLEFT ;

GC = GCTRCY ;

UDATA = [UDATA3X , UDATA2X , UDATA1X , UDATA0X 3 ;

C2 = C2SHB ;

UGR = [UGR2 , UGR1 , UGR03 ;

equations

"NOTE SHLEFT ARE USED AS ENABLE SIGNAL FOR SHIFTER FUNCTIONS

ENA_JOUT - UDATA2X & UDATA1X & !UDATA0X

& SHLEFT & !ZFG & !GCTRCY & C2SHB

# !MEQ1 & !UGR2 & UGR1 & UGR0

& UDATA3X & !UDATA2X & !UDATA1X & !GCTRCY & C2SHB ;

"C2SHB*(BIT,BYT SCAN)

"C2SHB*(MUL,DIV)

SHWAITRQ = !MEQ1 & !UGR2 & UGR1 & UGR0 & !UDATA3X & !UDATA2X & !GCTRCY

# !MEQ1 & !UGR2 & UGR1 & UGR0 & !UDATA3X & !UDATA1X & !GCTRCY

# !MEQ1 & !UGR2 & UGR1 & UGR0 & !UDATA2X & !UDATA1X & !GCTRCY

# !MEQ1 & !UGR2 & UGR1 & UGR0

& UDATA3X & UDATA2X & !UDATA1X & !UDATA0X & !GCTRCY

# !MEQl & !UGR2 & UGR1 & UGR0

& UDATA2X & UDATA1X & !UDATA0X & !GCTRCY & !ZFG

# !MEQl & !UGR2 & UGR1 & UGR0

& !UDATA3X & UDATA2X & UDATA1X & UDATA0X & C!TGRCY & !SHCYX; "LOGSHF.ARSHF,ROT

"LONG LOGSHF,ARSHF,ROT

"MUL,DIV

"SHK LEFT BYTE

"BIT BYT SCAN

"LOC LEAD

"1 BIT " SL = SHLEFT ;

" GC = GCTRCY ;

" UDATA = [UDATA3X , UDATA2X , UDATA1X , UDATA0X ] ; " C2 = C2SHB ;

" UGR = [UGR2 , UGR1 , UGR0] ;

test_vectors

end _SH12B5L8 ; module _SH9B1R4; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

SH9B1R4 PAO MAY 07, 1987

SHIFTER K NUMBER 0 OF 15 (START WITH 0) >>> APPLY TO SHK 0 & 1 <<<

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

SH9B1R4 device 'P16R4';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

VCC

pin 20;

KCLKA, !KSOA, !KS1A, !KS2A, 1EN_KOUTA, !KCLRA,KOSL,SHK04, !MULDIV pin 1,2,3,4,5,6,7,8,9 ;

SHK00 ,SHK01,SHK02,SHK03

pin 14,15,16,17;

G,B0,B1,B2,B3

pin 11,12,13,18,19;

KC = KCLKA ;

KS = [KS2A , KS1A , KSOA] ;

OUT = EN KOUTA ;

CLR = KCLRA ;

SKO = SHK00

SKI = SHK01

SK2 = SHK02

SK3 = SHK03

SK4 = SHK04

MD = MULDIV ;

equations

enable B3 = EN_KOUTA ;

JB3 = !SHK03 & !KCLRA

# KCLRA ;

"OUT K

enable B2 = EN_KOUTA ;

!B2 = !SHK02 & !KCLRA

# KCLRA ;

"OUT K

enable Bl = EN_KOUTA ;

!B1 = !SHK01 & !KCLRA

# KCLRA ;

"OUT K enable BO - EN_KOUTA ;

IBO - I SHKOO & !KCLRA

# KCLRA ;

"OUT K

!SHK03 :- !KSOA & !SHK03

# 1KS2A & !KS1A & KS0A & !B3

# !KS2A & KS1A & KS0A & !SHK02

# KS2A & !KS1A & KS0A & !SHK04

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK02 := !KSOA & !SHK02

# !KS2A & !KS1A & KS0A & !B2

# 1KS2A & KS1A & KS0A & !SHK01

# KS2A & !KS1A & KS0A & !SHK03

# KS2A & KS1A & KS0A ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK01 := !KSOA & !SHK01

# !KS2A & !KS1A & KSOA & !B1

# !KS2A & KS1A & KSOA & !MULDIV & !SHK00

# !KS2A & KS1A & KSOA & MULDIV & !KOSL

# KS2A & !KS1A & KSOA & !SHK02

# KS2A & KS1A & KSOA ;

"HOLD K,RESERVED

"LOAD K

"SH K LEFT NORMAL CASE

"SH K LEFT DIVID CASE

"SH K RIGHT

"BYT SCAN 0 IN

"K CLEAR

!SHK00 :- !KSOA & !SHK00

# !KS2A & !KS1A & KSOA & !BO

# 1KS2A & KS1A & KSOA & !MULDIV & !KOSL

# !KS2A 6= KS1A & KSOA & MULDIV

# KS2A & !KS1A & KSOA & !SHK01

# KS2A & KS1A & KSOA ;

"HOLD K.RESERVED

"LOAD K

"SH K LEFT NORMAL CASE FROM KOSL

"SH K LEFT DIVID CASE 0 IN

"SH K RIGHT "BYT SCAN O IN

"K CLEAR

KC = KCLKA ;

KS = [KS2A , KS1A KSOA]

OUT = EN KOUTA ;

CLR = KCLRA ;

SKO = SHK00;

SKI = SHK01;

SK2 = SHK02;

SK3 = SHK03;

SK4 = SHK04;

MD = MULDIV ;

test_vectors

end _SH9B1R4; module _SH12C7L8 ; flag ' -r0' ;

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH12C7L8 PAO MAY 13, 1987

SHIFTER FUNCTION CONTROL

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH12C7L8 device 'P16L8';

"declarations

TRUE, FALSE - 1,0 ;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10, 20;

!SHLEFT, !SHRIGHTX, !SHCY, !GCTRCY.ZFG

pin 1.2.3,4,5;

!UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X.C2SHB, !SHCYX, !SHCYXD, !SHCYDLP

pin 6,7,8,9,11,13,14,15 ;

!SHJS1B.!SHJS2A

pin 12,19;

!SHJS1A, !SHJSOA

pin 17,18;

SL - SHLEFT ;

SR - SHRIGHTX ;

GC - GCTRCY ;

UDATA - [UDATA3X , UDATA2X , UDATA1X , UDATA0X] ;

C2 - C2SHB ;

equations

"NOTE SHLEFT,SHRIGHTX ARE USED AS QUALIFY SIGNAL FOR SHIFTER FUNCTION

SHJSOA = UDATA2X & UDATA1X & !UDATA0X & SHLEFT & C!TGRCY & !ZFG ;

"BIT,BYT SCAN

"ALL SHIFT RIGHT RELATED CASE ARE IN SH12B7R4.ABL

SHJS1A - !UDATA3X & !UDATA1X & SHLEFT & !GCTRCY

# !UDATA3X & !UDATA2X & SHLEFT δ: !GCTRCY

# !UDATA3X & UDATA2X & UDATA1X & UDATA0X

& SHLEFT !&G CTRCY & !SHCY

# UDATA3X & !UDATA2X & !UDATA1X & UDATA0X

& SHLEFT!&G CTRCY & C2SHB

# UDATA2X & UDATA1X & !UDATA0X & SHLEFT & !GCTRCY & !ZFG ;

"LOG SHL, ARTH SHL,ROL

"(LONG & NO LONG)

"LOC LEAD 1 BIT "DIV (2ND HALF CYC WILL

"LOAD J FROM ALU)

"BIT,BYT SCAN

SHJS2A - !UDATA3X & !UDATA1X & SHRIGHTX & !GCTRCY

# !UDATA3X & !UDATA2X & SHRIGHTX & C!GTRCY

# UDATA3X & !UDAIA2X & !UDATA1X & !UDATA0X

& SHRIGHTX !&G CTRCY & C2SHB

# UDATA3X & !UDAIA2X & !UDATA1X & !UDATA0X

& SHRIGHTX & IGCTRCY & 1C2SHB

# UDATA3X & UDATA2X & UDATA1X & !UDATA0X

& SHLEFT & !GCTRCY & !ZFG

# UDATA3X & !UDAIA2X & !UDATA1X & UDATA0X

& SHLEFT & !GCTRCY & !C2SHB ;

"LOG SHR,ARTH SHR,ROR

"(LONG & NO LONG)

"MUL & 1ST HALF CYC

"MUL & 2ND HALF CYC WILL BE LOAD J

"LOAD J FROM ALU

"BYT SCAN

"DIVID 2ND CYC WILL BE LOAD J

SHJS1B = !UDATA3X & !UDATA1X & SHRIGHTX & !GCTRCY

# !UDATA3X & !UDATA2X & SHRIGHTX & !GCTRCY

# UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X

& SHRIGHTX & !GCTRCY & C2SHB ;

"LOG SHR,ARTH SHR,ROR

"(LONG & NO LONG)

"MUL(2ND HALF CYC WILL

" LOAD DATA FROM ALU)

SHCYDLP = UDATA3X & !UDATA2X & !UDATA1X

& SHCY

# I ( UDATA3X & !UDATA2X & !UDATA1X )

& SHCYXD ;

"FOR MUL & DIV CASE CY TO DLOOP WILL BE NO DELAY

"ALL THE OTHER CASE CY TO DLOOP WILL BE DELAY BY 2 u-CYC " SL = SHLEFT :

" SR = SHRIGHTX ;

" GC = GCTRCY ;

" UDATA = [UDATA3X , UDATA2X , UDATA1X , UDATA0X] ;

" C2 = C2SHB ;

" CARY = [ SHCY , SHCYX];

testvectors

module _SH11C3L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11C3L8 PAO AUG 08, 1986

SHIFTER K LINK CONTROL NUMBER 2 OF 2 (U19)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH11C3L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

!SHRIGHTY, 1LONG, SHJ00, SD1,SD0 ,SHK08,SHK16 ,SHK32 , !MUL

pin 1,2,3,4,5,7,8,9,11;

K31SR.K15SR

pin 12,19;

K63SR,K7SR

pin 16,17;

SD = [ SD1 , SD0 ];

SR = SHRIGHTY;

JO = SHJOO;

K8 = SHK08;

K16 = SHK16;

K32 = SHK32;

equations

"***** NOTE: SHRIGHTY IS AN ENABLE SIGNAL FOR SHIFTER FUNCTION ALSO !K7SR = SHRIGHTY & LONG & !SHK08

# SHRIGHTY & MUL & SD0 & !SHK08

# SHRIGHTY 6. MUL & SD1 & !SHK08

# SHRIGHTY & MUL & !SD1 & !SD0 & !SHJ00 ;

"LONG RIGHT, SHK08

"DBYTE,WORD MUL, SHK32

"HWORD,WORD MUL, SHK32

"BYTE MUL, SHJOO

!K15SR = SHRIGHTY & LONG & !SHK16

# SHRIGHTY & MUL & SD1 & !SHK16

# SHRIGHTY & MUL & !SD1 & SD0 & !SHJ00 ;

"LONG RIGHT, SHK16

"HWORD,WORD MUL, SHK16

"DBYTE MUL, SHJ00 !K31SR - SHRIGHTY & LONG & !SHK32

# SHRIGHTY & MUL & SD1 & SD0 & 1SHK32

# SHRIGHTY & MUL & SD1 & !SD0 & !SHJ00

"LONG RIGHT, SHK32

"WORD MUL, SHK32

"HWORD MUL, SHJ00

!K63SR = SHRIGHTY & LONG & !SHJ00

# SHRIGHTY & MUL & SD1 & SD0 & !SHJ00 ;

"LONG RIGHT, SHJ00

"WORD MUL, SHJ00 " SD = [ SD1 , SD0 ];

" SR = SHRIGHTY;

" J0 = SHJ00

" K8 = SHK08

" K16 = SHK16

" K32 = SHK32

testvectors

(

end _SH12B5L8 ;

module SH11B5L8 ; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11B5L8 PAO AUG 07, 1986

SHIFTER J LINK CONTROL NUMBER 1 OF 2

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH11B5L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

SHJ07,SD0,SD1, !SHLEFT, !UDATA0X, !UDATA1X, !UDATA2X, !UDATA3X, !UCY,SHK63 pin 1,2,3,4,5,6,7,8,9,11;

JJOSLA,!JOSLAX

pin 12,19;

SHJ63 ,SHJ31 , SHJ15.UDATA6 , ! SHCY, !SHF_OP

pin 13,14,15,16,17,18;

SL = SHLEFT;

SD = [SD1 , SD0J;

UDATA = [UDATA3X , UDATA2X „ UDATA1X , UDATA0X] ;

J7 = SHJ07

J15 = SHJ15

J31 = SHJ31

J63 = SHJ63

K63 = SHK63

OP = SHF_OP ;

equations

enable JOSLAX = UDATA6 ;

JOSLAX = !SHF_OP & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X & UCY

& SHLEFT

# SHF_OP & !UDATA3X & !UDATA2X & UDATA1X & !UDATA0X & SHCY & SHLEFT

# SHLEFT & !UDATA3X & UDATA2X & !UDATA1X & SHK63

# SHLEFT & !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHK63 ;

"RLC FIRST CYCLE, JOSL - UCY

"RLC REST CYCLE, JOSL - SHCY

"LONG LEFT SHIFT, SHK63

"LONG LEFT ROTATE, SHK63 enable JOSLA = !UDATA6 ; JOSLA - SHLEFT & SD1 & SD0 & SHJ63 & !UDATA3X & !UDATA2X

& UDATA1X & !UDATA0X

# SHLEFT & SD1 & !S0D& SHJ31 & !UDATA3X & !UDATA2X

& UDATA1X & !UDATA0X

# SHLEFT & !SD1 & SD0 & SHJ15 & !UDATA3X & !UDATA2X

& UDATA1X & !UDATA0X

# SHLEFT & !SD1 & !SD0 & SHJ07 & !UDATA3X & !UDATA2X

& UDATA1X & !UDATA0X

# SHLEFT & !UDATA3X & UDATA2X & !UDATA1X & SHK63

# SHLEFT & !UDATA3X & !UDATA2X & UDATA1X & UDATA0X & SHK63

"WORD ROL, SHJ63

"HWORD ROL, SHJ31

"DBYTE ROL, SHJ15

"BYTE ROL, SHJ07

"LONG LEFT SHIFT, SHK63

"LONG LEFT ROTATE, SHK63 " SL = SHLEFT

" SD = [SD1 , SD0]

" UDATA = [UDATA3X , UDATA2X , UDATA1X , UDATA0X]

" J7 = SHJ07

" J15 = SHJ15

" J31 = SHJ31

" J63 = SHJ63

" K63 = SHK63

" OP = SHF OP

test_vectors

( !O

module _SH11B7L8; flag '-r0';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH11B7L8 PAO DEC 19, 1986

MULTIPLY, DIVISION, & BIT SCAN LINK CONTROL FOR JOSL (U17)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SHUB7L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND,VCC

pin 10,20;

!UDATA3X, !UDATA2X, !UDATA1X, !UDATA0X, SD1,SD0,SHK07,SHK15,SHK31,SHK63 pin 1,2,3,4,5,6,7,8,9,11;

1ARSH,!JOSLB

pin 12,19;

!SHLEFT, !SHF_OP, !MUL, !LONG

pin 13,14,17,18;

UDATA = [UDATA3X,UDATA2X,UDATA1X,UDATA0X] ;

SD = [SD1, SD0];

K7 = SHK07;

K15 = SHK15;

K31 = SHK31;

K63 = SHK63;

SL = SHLEFT;

equations

" COMMENT: 1 BIT SCAN WILL BE IN WORD ONLY

JOSLB = SHLEFT & !UDATA3X & UDATA2X & UDATA1X & !UDATA0X

& SD1 & SD0 & SHK63

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SD1 & SD0 & SHK63

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & SD1 & !SD0 & SHK31

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & !SD1 & SD0 & SHK15

# SHLEFT & UDATA3X & !UDATA2X & !UDATA1X & UDATA0X & !SD1 & !SD0 & SHK07 ;

"BIT SCAN, SHK63

"WORD DIV

"HWORD DIV

"DBYTE DIV

"BYTE DIV

ARSH = !UDATA3X & !UDATA1X & UDATA0X ; "ARITH SH.LONG ARITH SH

LONG = !UDATA3X & !UDATA2X & UDATA1X & UDATA0X # !UDATA3X & UDATA2X & !UDATA1X ;

"LONG ROTATE

"LONG LOGIC AND

"ARITHMETIC SHIFT

MUL = UDATA3X & !UDATA2X & !UDATA1X & !UDATA0X ;

"MULTIPLY

UDATA = [UDATA3X.UDATA2X,UDATA1X,UDATA0X] ; "

" SD = [SD1,SD0];

" K7 = SHK07;

" K15 = SHK15;

" K31 = SHK31;

" K63 = SHK63;

" SL = SHLEFT;

test vectors

en _SH ; module _SH12B3R4; flag '-r0';

title

'PAL16R4 PAL DESIGN SPECIFICATION

SH12B3R4 PAO DEC 23, 1986

OVERFLOW FLAG GENERATOR (U41)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL- ' ;

SH12B3R4 device 'P16R4';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

C2, !SHLEFT,SD1,SD0, !ARSH,SHJ63,SHJ31,SHJ15,SHJ07,G

pin 1,2,3,4,5,6,7,8,9,11;

!SHAROV,Q1, !SHWAITRQD,Q0

pin 17,15,16,14;

!OVFL2, !OVFLl, !SHWAITRQ, !SHCYX

pin 12,13,18,19;

SL = SHLEFT ;

J63 = SHJ63 ;

J31 = SHJ31 ;

J15 = SHJ15 ;

J7 = SHJ07 ;

SD = [SD1 , SD0 ];

SHRV = SHAROV ;

SHCX = SHCYX ;

SW = SHWAITRQ ;

SWD = SHWAITRQD ;

V1 = OVFLl ;

V2 = OVFL2 ;

SV = SHAROV ;

" States

S0 = ^b11;

S1 = ^b10;

S2 = ^b00;

equations

OVFL2 = ARSH & SHLEFT & SHWAITRQD & SD1 & SD0 & SHJ63 & !SHCYX

# ARSH & SHLEFT & SHWAITRQD & SD1 & SD0 & 1SHJ63 & SHCYX

# ARSH & SHLEFT & SHWAITRQD & SD1 & !SD0 & SHJ31 & !SHCYX

# ARSH & SHLEFT & SHWAITRQD & SD1 & !SD0 & !SHJ31 & SHCYX ;

OVFL1 = ARSH & SHLEFT & SHWAITRQD & !SD1 & SD0 & SHJ15 & !SHCYX

# ARSH & SHLEFT & SHWAITRQD & !SD1 & SD0 & !SHJ15 & SHCYX

# ARSH & SHLEFT & SHWAITRQD & !SD1 & !SD0 & SHJ07 & !SHCYX

# ARSH & SHLEFT & SHWAITRQD & !SD1 & !SD0 & 1SHJ07 & SHCYX "ASHL WORD,LONG WORD

"ASHL HWORD

"ASHL DBYTE

"ASHL BYTE

SHWAITRQD := SHWAITRQ ;

SHAROV := !Q0

# 1SHWAITRQD & Ql & QO & SHAROV

# SHWAITRQD & Ql & QO & ( OVFL2 # OVFLl ) ;

state_diagram [Q1,Q0]

State S0: IF SHLEFT & ARSH & SHWAITRQD & (OVFL1 # OVFL2) THEN S1

ELSE S0 ;

State S1: IF SHWAITRQD THEN S1

ELSE S2 ;

State S2: GOTO S0 ;

" SL = SHLEFT

" J63 = SHJ63

" J31 = SHJ31

" J15 = SHJ15

" J7 = SHJ07

" SD = [SD1 , SD0 ];

" SHRV = SHAROV ;

" SHCX = SHCYX ;

" SW = SHWAITRQ ;

" SWD = SHWAITRQD ;

" V1 = OVFL1 ;

" V2 = OVFL2 ;

" SV - SHAROV ;

test_vectors

test_vectors

end _SH12B3R4;

module _SH12C5L8; flag '-rO';

title

'PAL16L8 PAL DESIGN SPECIFICATION

SH12C5L8 PAO JAN 13, 1987

SHIFTER IN/OUT CONTROL (U9)

DAVIN COMPUTER IRVINE CALIFORNIA

-Translated by TOABEL-';

SH12C5L8 device 'P16L8';

"declarations

TRUE,FALSE - 1,0;

H,L = 1,0;

X,Z,C = .X.,.Z.,.C.;

GND.VCC

pin 10,20;

UFD0 ,UFD1,UFD2 ,UFD3 ,UBS0,UBS1,UBS2 ,UBS3 ,C2SHB

pin 1,2,3,4,5,6,7,8,11;

!EN_KOUTA, !ENB_JOUT

pin 12,19;

!KCLRA, 1KCLRB, !LD_SHK, 1EN_KOUTB, 1 SHJS2B, !SHJSOB

pin 13,14,15,16,17,18;

UFD = [UFD3 , UFD2 , UFD1 , UFD0] ;

UBS = [UBS3 , UBS2 , UBS1 , UBS0];

C2 = C2SHB;

KC = [KCLRA^', KCLRB];

equations

SHJSOB = !UBS3 & UBS2 & !UBS1 & UBS0 & C2SHB

# UFD3 & UFD2 & UFD1 & !UFD0 & !C2SHB

"OUT J FIRST HALF

"ALU FD E,(LD MASK) SECOND HALF

SHJS2B = ( UFD = ^h5 ) & !C2SHB

# ( UFD = ^h8 ) & !C2SHB

# ( UFD = ^hC ) & !C2SHB

# ( UFD = ^hD ) &!C2SHB

# ( UFD = ^hE ) &!C2SHB

# ( UFD = ^hF ) & !C2SHB

"ALU FD5,8,C,D,E,F (LD J) LOAD J 2ND HALF

ENB_JOUT - !UBS3 & UBS2~& !UBS1 & UBSO & C2SHB ;

"ALU B BUS SOURCE AT

"1ST HALF CYC

EN_KOUTA - !UBS3 & UBS2 & UBS1 & !UBS0 & C2SHB

# UBS3 & !UBS2 & !UBS1 & UBS0 & C2SHB ; "ALU B BUS SOURCE

"ALU B BUS 0 SOURCE

ENJCOUTB - !UBS3 & UBS2 & UBS1 & !UBS0 & C2SHB

# UBS3 & !UBS2 & !UBS1 & UBS0 & C2SHB ;

"ALU B BUS SOURCE

"ALU B BUS 0 SOURCE

LD_SHK - !UFD3 & UFD2 & UFDl & !UFD0 & !C2SHB

# UFD3 & !UFD2 & !UFD1 & UFD0 & !C2SHB

"LOAD K 2ND HALF AND ALU FD6.9

KCLRA - UBS3 & !UBS2 & !UBS1 & UBS0; "ALU B BUS 0 SOURCE

KCLRB - UBS3 & !UBS2 & JUBS1 & UBS0; "ALU B BUS 0 SOURCE " UFD = [UFD3 , UFD2 , UFD1 , UFD0];

" UBS = [UBS3 , UBS2 , UBS1 , UBS0];

" C2 = C2SHB;

" KC = [KCLRA , KCLRB];

end _SH12C5L8;

PARALLEL STRING PROCESSOR AND METHOD FOR A MINICOMPUTER

APPENDIX 3

DAVIN COMPUTER CORPORATION 1987

Claims

WHAT IS CLAIMED IS:

1. A string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word having data of unknown content in said bytes and that finds the location of a byte in said first multiple-byte data word having a selected content characteristic, characterized by:

a first circuit (100, 102, 109, 115, 122) that provides an output signal for each byte of said first multiple-byte data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;

a second circuit (500, 522, 532, 536) that receives the output signals from said first circuit (100, 102, 109, 115, 122) said second circuit (500, 522, 532, 536) providing a digital output value that identifies the location of an output signal from said first circuit (100, 102, 109, 115, 122) that has a selected one of said first and second logic levels and that corresponds to a byte in said first multiple-byte data word having a selected positional characteristic with respect to other bytes in said first multiple-byte data word; and

a third circuit (720; 800) that receives said digital output value provided by said second circuit (500, 522, 532, 536) and performs a selected function based upon said byte in said first multiple-byte data word having said positional characteristic.

2. The string processor as defined in Claim 1, wherein said third circuit (720) performs a multi-way conditional branch upon identifying the most significant byte of said first multiple-byte data word having said selected content characteristic.

3. The string processor as defined in Claim 1, wherein said third circuit (720) performs a multi-way conditional branch upon identifying the most significant byte of said first multiple-byte data word not having said selected content characteristic.

4. The string processor as defined in Claim 1, wherein said third circuit (800) clears the byte positions in said first multiple-byte data word from the location of the most significant byte of said first multiple-byte data word having said selected content characteristic to the least significant byte of said first multiple-byte data word.

5. The string processor as defined in Claim 1, wherein said third circuit (800) clears the byte positions of said first multiple-byte data word from the most significant byte of said first multiple-byte data word up to the location of the most significant byte of said first multiple-byte data word having said selected content characteristic.

6. The string processor as defined in Claim 1, wherein said third circuit (800) clears the most significant byte of said f-irst multiple-byte data word having said selected content characteristic.

7. The string processor as defined in Claim 1, wherein said third circuit (800) clears the byte positions of said first multiple-byte data word from the location of the most significant byte of said first multiple-byte data word not having said selected content characteristic to the least significant byte of said first multiple-byte data word.

8. The string processor as defined in Claim 1, wherein said third circuit (800) clears the byte positions of said first multiple-byte data word from the most significant byte of said first multiple-byte data word up to the location of the most significant byte of said first multiple-byte data word not having said selected content characteristic.

9. The string processor as defined in Claim 1, wherein said third circuit (800) clears the most significant byte of said first multiple-byte data word not having said selected content characteristic.

10. The string processor as defined in Claim 1, wherein said third circuit (800) clears the output bit from said first circuit corresponding to the location of the most significant byte of said first multiple-byte data word having said selected Content characteristic.

11. The string processor as defined in Claim 1, wherein said third circuit (800) clears the output bit from said first circuit corresponding to the location of the most significant byte of said first multiple-byte data word not having said selected content characteristic.

12. A circuit (600) that receives an input data word comprising a plurality of bytes and that provides at least one selected byte of said input data word in an output data word, said at least one selected byte being selectably rotated by one or more byte positions, and said at least one selected byte being replicated to fill said output data word with copies of said at least one selected byte.

13. A circuit (600) as defined in Claim 12, wherein said at least one selected byte of said input data word comprises one byte and said output data word comprises eight bytes, said one byte replicated to fill said output data word with eight copies of said one byte.

14. A circuit (600) as defined in Claim 12, wherein said at least one selected byte of said input data word comprises two bytes and said output data word comprises eight bytes, said two bytes replicated to fill said output data word with four copies of said two bytes.

15. A circuit (600) as defined in Claim 12, wherein said at least one selected byte of said input data word comprises four bytes and said output data word comprises eight bytes, said four bytes replicated to fill said output data word with two copies of said four bytes.

16. A circuit (600) as defined in Claim 12, wherein said at least one selected byte of said input data word comprises eight bytes and said output data word comprises eight bytes, said eight bytes replicated to fill said output data word with one copy of said eight bytes, said eight bytes in said output data word occupying different byte positions than in said input data word.

17. A circuit (600) as defined in Claim 12, wherein said circuit comprises a multiplexer (650-657) for each bit of said output data word, said multiplexer (650-657) for an output bit in a particular bit position in a byte receiving one bit from the corresponding bit position in each byte in said input data word, said multiplexer (650-657) controlled so that said bit of said output data word comprises said corresponding bit from said at least one selected byte.