WO1991014015A1

WO1991014015A1 - Method and materials for forming multi-layer circuits by an additive process

Info

Publication number: WO1991014015A1
Application number: PCT/US1991/000875
Authority: WO
Inventors: Keith O. Wilbourn; Thomas A. Armer; Jeffrey S. Braden; Kin-Shiung Chang; Michael A. Raftery
Original assignee: Olin Corporation
Priority date: 1990-03-05
Filing date: 1991-02-11
Publication date: 1991-09-19
Also published as: AU7317191A

Abstract

A screenable dielectric (16) and a method for the manufacture of multi-layer circuits (10) by an additive process is provided. A plurality of conductive layers are separated by the screenable dielectric (16). During screen printing, vias (46) are formed in the dielectric (16) such that a selective portion of underlying circuit traces (14b) remains conductive. The screenable dielectric (16) has a high thixotropic index so that it readily flows through the screen and then rapidly increases in viscosity to minimize feature collapse. The conductive portions (14b) are electrically interconnected by a conductive paste (48) which may be deposited by screen printing or by direct writing.

Description

METHOD AND MATERIALS FOR FORMING MULTI-LAYER CIRCUITS BY AN ADDITIVE PROCESS

This invention relates to printed circuits having a plurality of interconnected conductive layers separated by a dielectric. More particularly, the invention relates to a process for forming flexible circuits having a high density of signal plane circuit traces selectively electrically interconnected to ground and/or power planes.

Electronic circuits contain a plurality of conductive circuit traces supported by a dielectric substrate. A printed circuit board or other rigid type of circuit assembly usually has a glass-filled epoxy substrate on the order of about .25mm (10 mils) thick. Flexible circuits are generally supported by a thin, on the order of about .051mm (2 mils) thick, polyimide substrate. Both types of circuitry may be formed by the same general procedure. Conventional circuit assembly processes employ photolithography. A layer of a conductive metal, such as copper foil, is bonded to the dielectric substrate by lamination. The conductive layer is then patterned into circuit traces. Patterning is usually a subtractive process entailing resist patterning followed by etching. The conductive surface of the laminate is coated with a photoresist. The photoresist is then exposed by a radiation appropriate to the resist type. Exposure takes place through a photomask so that the resist is developed in the desired circuit design. After resist patterning, a suitable solvent removes the unexposed resist. A suitable acid etch then removes the conductive layers from the exposed regions. After etching, the remaining resist is removed resulting in a desired pattern of circuit traces.

While patterning has been described in terms of a negative photoresist, a positive photoresist may also be employed.

This process is known as subtractive. The circuit traces are formed by removing metal from the circuit board. While dissolved metal may be recovered by an electrolytic process, recovery is time consuming and expensive. The solvents used to remove resist and the dissolved resists are based on organic chemicals which may pose a hazard both to the environment and to people exposed to them.

It is frequently desired to form printed circuits having a plurality of conductive layers separated by a dielectric disposed between the layers. Electrical interconnection between conductive layers is by small holes, called vias, formed within the dielectric layer. Many processes have been detailed to make the vias conductive. One such process known as the BLACKHOLE™ deposition process (BLACKHOLE™ is a trademark of Olin Corporation, Stamford, Connecticut, USA) is disclosed in U.S. Patent No. 4,684,560 by Minten et al. A dispersion of carbon black is deposited on the dielectric walls of the via. The carbon black makes the walls conductive and facilitates either electrolytic or electroless deposition of copper to form a conductive via.

The vias are conventionally formed by a subtractive process similar to that used to pattern the circuit traces. A layer of a photosensitive dielectric is deposited over the circuit traces. A mask containing the desired pattern of vias is placed over the resist. The resist is exposed and only the sites of the vias remain soluble. After dissolution, a second conductive layer is laminated to the resist. The second conductive _4 _

Other additive type processes exploit polymers which cross link when irradiated by X-rays. U.S. Patent No. 4,732,843 by Budde et al discloses linear fluorooligomers which have at least two reactive groups per molecule and have been reacted with a radiation sensitive substance. These processes also include subtractive steps.

Accordingly, it is an object of the present invention to provide a screenable dielectric having improved flow and thermal characteristics. It is another object of the invention to provide a process to manufacture multi-metal layer circuits by an additive process. It is a feature of the invention that dielectric layers and conductive layers are applied by screen printing or by the direct writing. It is another feature of the invention that the vias are formed directly in the dielectric layer as applied. It is an advantage of the additive process that precise alignment is obtained. Yet another advantage of the invention is the flow characteristics of the dielectric are carefully controlled minimizing via collapse. It is a further advantage that no subtractive removal of material is required. It is an advantage of the invention that the amount of material dissolved which must be reclaimed or disposed is minimized. It is a further advantage that the requirement for organic solvents is minimized reducing the environmental hazard.

In accordance with the invention, there is provided a screenable dielectric and an additive process to electrically interconnect selected traces of a circuit containing a plurality of traces. The dielectric has a composition by weight of from about 35 to about 60% thermosetting polyimide, from about 35 to about 60% of a solvent, an effective amount of a flow enhancer and an effective amount of a viscosity increasing agent. The plurality of traces are selectively insulated by coating -3-

layer is then coated with another layer of resist and formed into a desired pattern of circuit traces by photolithography. The process may be repeated as many times as necessary. One problem with forming vias using a conventional resist is the flow characteristics of most resists is not ideal. The polymer flows after screening reducing the inside diameter of the via. During a post screening cure, the resist frequently gives off water further collapsing the via. The collapse may be sufficiently severe to prevent the deposition of a conductive metal within the via leading to failure of the interconnect.

The photolithographic process is subtractive. Metal loss and disposal of solvents is also problem. The multitude of photolithographic steps makes alignment between the plurality of layers difficult. Alignment is not as severe a problem with rigid boards. Individual traces may have a width of up to about .38mm (15 mils). However, on flexible circuits with circuit trace widths down to about .051mm (2 mils), mask alignment is difficult.

Several additive processes to manufacture multi-layer circuit boards are known. U.S. Patent No. 3,904,783 to Nara discloses printing a circuit pattern on an insulating substrate with a synthetic resin ink containing 1 to 10 percent by weight of a fine metal powder by silk screening. Conductivity is improved by electroless plating on the screened metal powder.

Another method disclosed in the Nara patent uses an organometallic. Certain metal salts of organic acids liberate metal ions when irradiated with ultra-violet rays. The metal salt is applied to the substrate as a solution. Irradiation through a mask containing the desired circuit pattern forms conductive lines of the metallic salt. The salt is chemically converted to base metal and plated to form circuit patterns. The unexposed organometallic is removed by dissolution. with the dielectric. A portion of those traces which are to be electrically interconnected is left conductive. Each conductive portion is then electrically connected either to another conductive portion or to a ground or power plane.

The above stated objects, features and advantages will become more apparent from the specification and figures which follow.

Figures 1A-1C illustrate in cross-sectional representation a sequence of steps to electrically interconnect circuit traces by an additive process in accordance with a first embodiment of the invention.

Figures 2A-2C illustrate in cross-sectional representation a sequence of steps to electrically interconnect signal plane circuit traces to ground and power planes in accordance with an embodiment of the invention.

Figure 3 illustrates in top planar view a signal plane containing circuit traces and plurality of annuli as known in the prior art.

Figure 4 illustrates in top planar view the additive process of the invention as applied to the signal plane of the prior art.

Figure 5 illustrates in top planar view an improved annulus in accordance with an embodiment of the invention.

Figures 6A-6C illustrate in cross-sectional representation an additive process - to electrically interconnect select traces by direct writing in accordance with an embodiment of the invention.

Figure 7 illustrates in top planar view the interconnection of selected traces by direct writing in accordance with the invention. -6-

Figure 1 illustrates in cross-sectional representation a method of forming a multi-metal layer printed circuit in accordance with the invention. The process employs a conventional printed circuit 10 as known from the art. The printed circuit 10 comprises a dielectric substrate 12, which may be a rigid board such as FR-4 (a flame retardant, glass-filled epoxy) or a flexible dielectric such as polyimide. A plurality of conductive circuit traces 14 which may have been patterned by subtractive photolithography are supported by the substrate 12.

In accordance with the invention, a screenable dielectric 16 is selectively applied over the circuit traces 14 and dielectric substrate 12 as illustrated in Figure IB. Certain circuit traces 14' are coated with the screenable dielectric 16 and insulated. Portions of certain circuit traces 14'' are not coated and remain conductive.

The screenable dielectric is chemically non-reactive to both the conductive circuit traces 14 and the substrate 12. The conductive circuit traces 14 are usually copper or a copper based alloy. The screenable dielectric should be resistant to copper catalyzed degradation. The screenable dielectric should further be environmentally stable and non-hydroscopic so the circuit does not break down upon exposure to sunlight or moisture. Other requirements of the screenable dielectric include a coefficient of thermal expansion close to that of the dielectric substrate 12. This requirement is most stringent in the case of a flexible dielectric substrate 12. A severe coefficient of thermal expansion mismatch may lead to flexure of the circuit during heating and cooling. A rigid substrate may not flex. However, the mismatch may generate stresses at the interface of the screenable dielectric and the substrate and cause delamination of the circuit traces 14. The screenable dielectric should also exhibit high temperature stability. During wire bonding or tape automated bonding to a semiconductor device, the temperature of the circuit traces is elevated to about 150°C. The circuit may be subjected to harsh operating environments, such as under the hood of an automobile or outer space.

Photolithography is not employed in the process of the invention. The screenable dielectric need not be photosensitive. This is an advantage since many photo active polymers contain methacrylate linkages. These linkages are unstable at temperatures above about 180°C. Other photo active compounds also have limited thermal stability. While any thermosetting polymer meeting the thermal stability, chemical resistivity and dielectric properties stated above is suitable, a thermosetting polyimide is preferred. The screenable dielectrics of the invention comprise a mixture of a thermosetting polyimide, a solvent, a flow enhancer and a viscosity enhancer. In the preferred embodiments, a co-solvent is included. The thermosetting polyimide is preferably a preimidized polyimide. These compounds are preferred over polyamic acids since they do not eliminate water during curing. It has been found the elimination of water causes the polyamic acid to shrink leading to via collapse.

A most preferred preimidized polyimide is polyisoimide. A thermosetting polyisoimide is preferred due to its thermal stability, chemical non-reactivity and good adhesion to other polyimides and metals. For flexible circuits, the coefficient of thermal expansion matches that of the polyimide substrate 12 preventing thermally induced flexure. A thermosetting polyimide is manufactured by National Starch & Chemical Corporation (Bridgewater, New Jersey, USA) under the trademark "THERMID™" . The second component of the screenable dielectric is a solvent capable of dissolving the polyimide for screen printing. A most preferred solvent is butyrolactone for screen printing. A flow enhancer is added in a quantity effective to enhance the flow of the screenable dielectric through the screen and to minimize the formation of bubbles in the deposited dielectric. One preferred flow enhancer is siloxane (R^Si-O-Si^R) . An effective amount of flow enhancer will permit bubbles formed in the screened dielectric to escape without increasing significantly the flow. Too much flow enhancer will lead to a loss of feature integrity. Too little will result in entrapped pockets of gas in the cured dielectric. The fourth component of the the screenable dielectric is a viscosity enhancer. By properly balancing the selection and composition of flow enhancer and viscosity enhancer, the unique properties of the screenable dielectric are achieved. The viscosity enhancer increases the thixotropic index of the screenable dielectric. When subjected to a shear stress, such as during screening, the dielectric flows readily. Unlike conventional filled dielectrics, little clogging of the screens is detected. Once the shear stress is removed, the viscosity increases rapidly so that the dielectric does not flow much after deposition. An effective amount of viscosity enhancer allows the dielectric to flow through the screen and then minimize flow on the substrate. Too much viscosity enhancer will result in a dielectric which can not pass through the screen. Too little will result in a loss of feature integrity on the screen.

One evaluation of the viscosity index of a screened substance is to compare feature dimensions on the screen to feature dimensions of the substance on a substrate. While conventional photoresists and inks have a feature reduction approaching 100% on small dimension vias, the dielectric of the invention exhibited only about a 35% feature reduction. One suitable viscosity enhancer is a fumed silica. The particles are quite small, preferably less than about 5 microns in diameter. Preferably a hydrophobic fumed silica is selected to minimize water retention in the dielectric. Over time, the polymer and solvent begin to separate. To keep the polymer in solution, a co-solvent is preferred. The co-solvent is any solvent which dissolves the polymer more readily than the solvent. Suitable co-solvents when the solvent is butyrolactone include dimethylsulfoxide (DMSO) and tetragly e.

The ratio of components is selected to produce a viscous liquid having a high thixotropic index. The liquid is screen printable using conventional screen printing equipment. The post screening viscosity increases rapidly to a value sufficiently high to minimize bleed out when deposited on circuit 10. For room temperature screening, the viscosity of the screenable dielectric is from about 10,000 to about 100,000 centipoise. More preferably, the viscosity of the screenable dielectric is from about 30,000 to 50,000 centipoise.

In its broadest embodiment, the screenable dielectric has a composition by weight of: from about 35 to about 60% thermosetting polyimide from about 35 to about 60% solvent an effective amount of flow enhancer an effective amount of viscosity enhancer.

In a more preferred embodiment, the composition of the screenable dielectric is: from about 40 to about 50% thermosetting polyimide from about 40 to about 50% solvent an effective amount up about to 1% flow enhancer from about 3 to about 5% viscosity enhancer from about 1 to about 3% co-solvent

A most preferred screenable dielectric has the composition by weight: from about 40 to about 50% polyisoimide from about 40 to about 50% butyrolactone an effective amount up about to 1% siloxane from about 3 to about 5% hydrophobic fumed silica from about 1 to about 3% dimethylsulfoxide

An advantage of the screenable dielectric is the flow rate is highly controlled due to a tightly balanced mixture of flow enhancers and viscosity increasers. Without the tightly balanced thixotropic index of the invention, features less than about .25mm (10 mils) with .25mm (10 mil) spacings are not obtainable by screening. With the balanced dielectric, features as small as .076mm (3 mils) have been printed by screening and by direct writing. The dielectric should also be amenable to application by stenciling (contact printing) .

Vias 18 are formed over those traces 14' ' to be electrically interconnected to either other circuit traces or to a ground or power plane. The circuit traces 14 in a flexible circuit are on the order of about .051mm (2 mils) wide with .051mm (2 mil) spacing. Vias on the order of .051mm to .076mm (2 to 3 mils) in diameter are required. At these dimensions, vias formed from conventional dielectrics are prone to collapse after screening and are not suitable. The features are readily obtained with the thermosetting screenable dielectric of the invention. After screening, the dielectric is cured by heating to a temperature of from about 230°C to about 350°C and more preferably in the range of from about 280°C to about 300°C. The cure time varies dependent upon the cure time. At 230°C, approximately four hours are required. At 320°C, the cure time is about 30 minutes. During the cure, the dimensions of the vias formed in the dielectric of the invention change by less than about 3 percent. After curing, the thermoset fluorinated polyimide is stable to intermittent temperatures of over 300°C and continuous operation at temperatures over 200°C.

The multi-layer circuit is completed by electrically interconnecting conductive portions of the circuit traces 14'' with a conductive paste 20 as illustrated in Fig 1-C. The conductive paste is applied over the entire surface 22 of the screenable dielectric 16. Screen printing or other techniques which are capable of applying a layer of paste having a uniform thickness may be used. A sufficient amount of paste is used so vias 18 are filled. The conductive paste makes contact with the conductive circuit traces 14''.

The conductive paste 20 may be any commercially available paste. One preferred paste comprises a fluorinated polyimide in a butyrolactone vehicle. A fine metal powder is dispersed through the paste to provide electrical conductivity. A preferred metal is silver. The paste is mixed so that after curing it has a composition of about 80 percent by weight silver and 20 percent by weight polyimide. This conductive paste is marketed under the trademark 99R0884 by Olin Hunt Conductive Materials (Ontario, CA., USA). The paste may be electroplated after curing to form a surface 24 which is solderable to another component, such as a heat sink or leadframe. The deposition of a metal overlayer 24 also improves conductivity. All fine features are formed in the thermosetting dielectric. High resolution is not required from the conductive pastes.

If desired, surface 24 of the conductive paste may be coated a barrier layer 26. The barrier layer 26 may be a polymer or an oxidation resistant metal. The layer prevents moisture, air and ionic contamination from contacting the conductive layer 20. The contaminants may react with the conductive layer and affect electrical properties. A most preferred barrier layer is a polyimide.

Figure 2 illustrates in cross sectional representation, an additive process to manufacture a multi-layer circuit in accordance with a second embodiment of the invention.

Figure 2A shows a conventional circuit following deposition of screenable dielectric 16. As Figure in IB, the circuit includes a dielectric substrate 12, insulated circuit traces 14' and conductive circuit traces 14'' and 14'''. A first class of circuit traces 14' is insulated by the screenable dielectric and forms the signal plane for the assembled circuit. These circuit traces transmit electrical signals between an electronic device and external circuitry. A second class of conductive circuit traces 14'' forms ground circuits. These circuit traces provide the electronic device with a ground. A third class of conductive circuit traces 14''' provides a source of power to the electronic device. Power and ground planes which are to be electrically interconnected to the conductive leads 14'', 14''' are formed from the conductive paste. Fine features are not required and any conductive paste may be used. A silver filled fluorinated polyimide as described above is one preferred paste. Figure 2B shows in cross sectional representation the circuit of Figure 2A with the addition of a first conductive portion constituting a ground plane 28 and a second conductive portion constituting a power plane 30. Since, in accordance with the invention, the vias 18 were formed in the thermosetting screenable dielectric 16, very fine features are obtained. The gap 32 which separates the ground and power planes does not require precise placement. The 10 mil resolution obtainable with a filled conductive ink is satisfactory for locating gap 32.

The gap 32 is preferably filled with a dielectric material 34 such as a polymer as illustrated in Figure 2C. The gap 32, if left unfilled may trap moisture or other contaminants and form an electrical short circuit between ground plane 28 and signal plane 30. One preferred dielectric for coating 34 is a polyimide. The process of the invention is particularly suited for manufacturing circuits for a pin grid array type electronic package. In a pin grid array circuit, a generally rectangular array of terminal pins is electrically interconnected to an electronic device by conductive circuit traces. The terminal pins are then inserted into external circuitry such as a printed circuit board. Figure 3 illustrates a conventional circuit 10 for a pin grid array circuit. A molded plastic pin grid array type package incorporating a circuit 10 is illustrated in United States Patent No. 4,816,426 to Bridges et al.

The circuit 10 is supported by a dielectric substrate 12. A first end 35 of circuit traces 14 terminates at a generally rectangular aperture 36. The electronic device (not shown) is centered within the rectangular aperture 36 and electrically interconnected to the first ends 35 of circuit traces 14 by wire bonds, tape automotive bonding means or other forms of electrical interconnection. The opposing end 37 of circuit traces 14 terminates at a conductive annulus 38. The conductive annulus 38 is formed by photolithographic techniques when the circuit traces 14 are formed. The conductive annulus is formed from the conductive metal layer which forms the circuit traces.

A circular aperture 40 is circumscribed by the conductive annulus 38. The head of a terminal pin (not shown) passes through each circular aperture 40 and is electrically interconnected to annulus 38. Electrical interconnection may be by mechanical contact, soldering, or other techniques such as brazing or riveting. Soldering is preferred for low cost reliable electrical interconnections. A low melting temperature solder such as a lead-tin alloy is mixed in powder form with an appropriate vehicle such as terpineol to form a solder paste. The paste is applied to each conductive annulus by a process such as screen printing. Any suitable solder may be employed. The melting temperature of the solder should be below the temperature at which thermal degradation of the dielectric substrate is encountered. Generally the solder will be selected to melt at a temperature below about 300°C. Lead-tin alloys such as 60% tin / 40% lead are exemplary. Subsequent to application of the solder paste, the terminal pins are inserted through circular apertures 40 and supported by a fixture. The assembly is passed through a furnace in an appropriate atmosphere. The solder melts and bonds the terminal pins to the circuit 10.

Figure 4 illustrates in top planar view a portion of the circuit 10 illustrating a problem with conventional annuli. When the screenable dielectric 16 is selectively applied over the circuit traces 14 (shown in phantom when coated with the screenable dielectric and as solid lines when visible through vias 18) surface tension causes the dielectric to creep along circuit traces 14 and impinge the annuli 38. The screenable dielectric interferes with soldering. The solder does not adhere to the screenable dielectric. A gap in the solder forms and the integrity of the solder joint is impacted. In accordance with an embodiment of the invention illustrated in Fig. 5, a teardrop shaped annulus 38' is formed during photolithography. The teardrop 42 is aligned so the circuit trace 14 is expanded prior to reaching the annulus 38'. The expanded metal reduces the distance the screenable dielectric 16 creeps along the circuit trace. No dielectric reaches the annulus 38'. High quality solder bonds between terminal pins and the conductive annuli 38' are formed. In certain applications, the resolution of the screenable conductive paste is inadequate even in combination with high resolution features formed within the screenable dielectric. Figure 6 illustrates in top planar view such a circuit. It is desired to interconnect circuit traces labeled 14^a and also the traces labeled 14 . The circuits 14^a and 14 are to remain electrically isolated. The circuits are spaced close together. The separation between vias 44 exposing the circuit traces 14 and vias 46 exposing the circuit traces 14 is less than about .15mm (6 mils). The applicants have solved this problem with the discovery direct writing may be employed. A direct writing process makes the vias 44, 46 electrically conductive. The process can also be used to interconnect the vias by conductive lines 48. The process of forming the conductive vias and conductive lines by direct writing is illustrated in cross sectional representation in Figure 7.

As with previous embodiments of the invention, a circuit 10 comprising a dielectric substrate 12 and conductive circuit traces 14 is coated with a screenable dielectric 16. Vias 46 are formed in the screenable dielectric 16 to form conductive portions of the circuit traces 14 at appropriate locations. The vias 46 are made electrically conductive and interconnected by conductive lines 48. Conductive lines are formed by a process such as additive direct writing. In additive direct writing, a fluid material is extruded from a pen tip onto a substrate resulting in an image. The features are produced directly from computer generated data without the need for hard tooling. For soluble systems containing no particulates, .031mm (1.2 mil) lines having .006mm (0.25 mil) spacings have been achieved. Using a precision X-Y table, resolution up to .003mm (.1 mil) is repeatability obtained. A direct writing system is available from Micropen, Inc. (Pittsford, New York, USA).

Filled inks clog the pen and reduce line resolution. An unfilled conductive material is favored. One such material is an organometallic gel. Organometallics are organic salts comprised of an organic acid and a metal ion. One group of organometallics employ glutamic acid. Silver glutamate, copper glutamate and palladium glutamate were formed.

For the process of the invention, copper, gold and silver salts are preferred for highest conductivity. One particularly favored organometallic salt is gold mercaptide. The salts decompose in the presence of heat or other energy source. One commercial source of organometallic gels is Engelhard Corporation (Newark, New Jersey, USA) .

Organometallics have been used to write circuit lines on ceramic substrates. The process has not been used with polymer substrates since the prior art screenable dielectrics thermally degrade at about 300°C. The screenable polyimide of the invention is thermally stable at the elevated temperatures required to decompose the organometallics. Applicants flexible circuits are capable of withstanding the decomposition temperature and organometallics may be used. Thin conductive lines 48 on the order of about 1000 angstroms can be formed by this process. The base of vias 46 is also made conductive by direct writing. The lines are quite thin and electrical conductivity is low. A conductive layer 50 as illustrated in Figure 7C, is preferably deposited on conductive line 48. The conductive layer 50 may be copper, gold or other highly conductive metal. It is deposited by electrolytic or electroless means or by any other process applicable to the techniques of the invention. By controlling the thickness of the conductive layer 50, the electrical properties of the circuit may be tailored to meet the needs of the electronic device. As with circuits described above, a barrier layer 26 is preferably employed to minimize surface contamination.

Direct writing is capable of producing lines having a width below about .051mm (2 mils). Spreading of the lines is minimal so electrical short circuits between adjoining lines are not likely. The resolution with direct writing is about +/- .006mm (0.25 mils) with a pitch of .013mm (0.5 mils). Extraordinarily small vias 46 may be formed in the screenable dielectric layer 16. These vias are then filled with a precise amount of material.

While the methods of the invention have been described in combination with a conventional circuit formed by photolithography, the process is applicable to entirely additive processes. With reference back to Figure 3, the circuit traces 14 and conductive annuli 38 may be formed by direct writing. .051mm (2 mil) circuit traces may be written using an organometallic ink. The traces are then plated with copper or other conductive metal to a thickness which gives a desired conductivity. While the multi-layer circuits of the invention have been described in terms of two conductive layers, it should be apparent to those skilled in the art that a second layer of screenable dielectric may be deposited on the conductive paste. The second layer of screenable dielectric may also contain vias which are filled with a second layer of conductive paste. This process may be repeated multiple times to form multi-layer circuitry. Direct writing techniques with improved resolution is particularly suitable for a plurality of conductive layers.

The circuits formed by the process of the invention are not limited to pin grid array circuits, any multilayer circuitry requiring a high density of interconnects may be formed. Among other applications of the circuits are multi-chip modules and hybrid packages.

It is apparent that there has been provided in accordance with the invention, a process for manufacturing multi-layer circuits by an additive technique which fully satisfies the objects, means and advantages set forth herein above. While the invention has been described in combination with the embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the appended claims.

Claims

IN THE CLAIMS

1. A thermosetting dielectric 16 suitable for screen printing, characterized by said thermosetting dielectric 16 consisting essentially of: from about 35 to about 60 weight percent a thermosetting polyimide; from about 35 to about 60% a solvent; an effective amount of a flow enhancer; an effective amount of a viscosity enhancer; and an effective amount of a co-solvent.

2. The thermosetting dielectric 16 of claim 1 characterized in that said thermosetting dielectric 16 consists essentially of: from about 40 to about 50 weight percent a thermosetting polyimide; from about 40 to about 50% of a solvent; an effective amount up to about 1% a flow enhancer; from about 3 to about 5% of a viscosity enhancer; and from about 1 to about 3% a co-solvent.

3. The thermosetting dielectric 16 of claim 2 characterized in that said thermosetting dielectric is a preimidized polyimide.

4. The thermosetting dielectric 16 of claim 2 characterized in that said co-solvent is selected from the group consisting of dimethylsulfoxide and tetraglyme and mixtures thereof.

5. The thermosetting dielectric of claim 3 characterized in that said thermosetting dielectric 16 consists essentially of: from about 40 to about 50 weight percent polyisoimide; from about 40 to about 50% butyrolactone; an effective amount up to 1% siloxane; and from about 3 to about 5% fumed silica; and from about 1 to about 3% dimethylsulfoxide.

6. The thermosetting dielectric 16 of claim 5 characterized in that said fumed silica has a mean particle diameter of less than about 5 microns.

7. The thermosetting dielectric 16 of claim 6 characterized in that said fumed silica is hydrophobic.

8. An additive process to electrically interconnect selected traces 14', 14", 14^a, 14 on a printed circuit 10 containing a plurality of traces, 14, 14', 14", 14a', 14b characterized by the steps of: partially insulating said selected traces 14',

14", 14^a, 14^b such that a portion 18, 44, 46 of each selected trace 14', 14", 14 , 14 remains conductive; and electrically interconnecting each one of said portions 18, 44, 46 either to at least one other said portion 44, 46 or to a ground 28 or a power 30 plane.

9. The additive process of claim 8 characterized in that said step of selectively insulating said plurality of traces 14', 14", 14a. 14b comprises selectively depositing a dielectric 16 by screen printing.

10. The additive process of claim 9 characterized in that said screenable dielectric 16 the composition: from about 35 to about 60 weight percent a thermosetting polyimide; from about 35 to about 60% a solvent; an effective amount of a flow enhancer; an effective amount of a viscosity enhancer; and an effective amount of a co-solvent.

11. The process of claim 10 characterized in that said screenable dielectric 16 has the composition: from about 40 to about 50 weight percent polyisoimide; from about 40 to about 50% butyrolactone; an effective amount up to 1% siloxane; from about 3 to about 5% fumed silica; and from about 1 to about 3% dimethylsulfoxide.

12. The process of claim 10 characterized in that said step of electrically interconnecting each conductive portion 14', 14", 14a, 14b comprises depositing a conductive paste 20 over said screenable dielectric 16 by screen printing.

13. The process of claim 12 characterized in that said conductive paste 20 is selected to be a silver filled fluorinated polyimide.

14. The process of claim 13 characterized in that said conductive paste 20 is composed of 80% silver and 20% polyimide after curing.

15. The process of claim 12 characterized in that said conductive paste 20 forms a single layer interconnecting each conductive portion 18 of said exposed selected circuit traces 14', 14".

16. The process of claim 12 characterized in that said conductive paste 20 is formed into at least first 28 and second 30 conductive portions such that some circuit traces 14' are electrically interconnected to said first conductive portion 28 and others 14" are electrically interconnected to said second portion 30.

17. The process of claim 12 characterized in that a barrier layer 26 is deposited over said conductive paste 20.

18. The process of claim 17 characterized in that said barrier layer 26 is a polyimide.

19. The process of claim 10 characterized in that the step of electrically interconnecting each said portion 44, 46 comprises direct writing a conductive material 48.

20. The process of claim 19 characterized in that said conductive material 48 contains no undissolved fillers.

21. The process of claim 20 characterized in that said conductive material 48 is an organometallic containing a metallic component selected from the group consisting of copper, gold and silver.

22. The process of claim 21 characterized in that said organometallic 48 is selected to be gold mercaptide.

23. An additive process for forming a circuit 10 for a pin grid array type package, characterized by the steps of: forming a plurality of circuit traces 14, 14a, 14b on a dielectric substrate 12, each said trace 14 having a first end 35 terminating at an aperture 36 in said dielectric substrate 12 and an opposing end 37 terminating at a conductive annulus 38; selectively insulating said traces 14, 14^a, 14 such that a portion of each selected trace 14^a, 14 and said conductive annulus 38 remain conductive; and electrically interconnecting each said portion

14' 14^J

24. The process of claim 23 characterized in that said step of selective insulation comprises depositing a dielectric 16 by screen printing and said step of electrical interconnection comprises depositing a conductive paste 20 over said screenable dielectric 16.

25. The process of claim 24 characterized in that said annuli 38'are formed in a teardrop shape 42 aligned such that the portion 37 of said trace 14 terminating at an annulus 38' is expanded.

26. The process of claim 25 characterized in that said screenable dielectric 16 has the composition: from about 35 to about 60 weight percent a thermosetting polyimide; from about 35 to about 60% a solvent; an effective amount of a flow enhancer; an effective amount of a viscosity enhancer; and an effective amount of a co-solvent.

27. The process of claim 26 characterized in that said screenable dielectric 16 has the composition: from about 40 to about 50 weight percent polyisoimide; from about 40 to about 50% butyrolactone; an effective amount up to 1% siloxane; from about 3 to about 5% fumed silica; and from about 1 to about 3% dimethylsulfoxide.

28. An additive process for the manufacture of a multi-layer flexible circuit 10, characterized by the steps of: providing a flexible dielectric substrate 12; forming a plurality of circuit traces 14, 14',

14" of said substrate 12 by an additive process; selectively insulating said traces 14, 14', 14" such that a portion of each selected trace 14', 14" remains conductive; and electrically interconnecting each said portion.

29. The process of claim 28 characterized in that said additive process comprises direct writing.

30. The process of claim 29 characterized in that said direct writing step employs an unfilled conductive material 48.

31. The process of claim 30 characterized in that said unfilled conductive material 48 comprises an organometallic capable of decomposition to a metal subsequent to said writing step.

32. The process of claim 31 characterized in that said direct written metal 48 is overplated with a conductive material 50 to a thickness effective to improve conductivity, said metal 50 selected from the group consisting of copper, silver and gold.

33. The process of claim 32 characterized in that said overplate 50 is copper.

34. A multilayer circuit 10 manufactured according to the process of claim 10.

35. A multilayer circuit 10 manufactured according to the process of claim 21.

36. A multilayer circuit 10 manufactured according e process of claim 25.

37. A multilayer circuit 10 manufactured according e process of claim 29.