WO1991015905A1 - Flexible-multiplexing process and device - Google Patents
Flexible-multiplexing process and device Download PDFInfo
- Publication number
- WO1991015905A1 WO1991015905A1 PCT/DE1991/000178 DE9100178W WO9115905A1 WO 1991015905 A1 WO1991015905 A1 WO 1991015905A1 DE 9100178 W DE9100178 W DE 9100178W WO 9115905 A1 WO9115905 A1 WO 9115905A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- identifier
- multiplex
- voice
- signals
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1623—Plesiochronous digital hierarchy [PDH]
- H04J3/1641—Hierarchical systems
Definitions
- the invention relates to a method and an arrangement for flexible multiplexing.
- a flexible multiplexer enables free bundling and distribution of time periods of digital multiplex signals. It can establish connections between subscriber-side connection units and can bundle and separate multiplex signals between subscriber-side and line-side connection units and channel distribution between line-side connection units.
- Such a multiplex device is from the publication "PDMX programmable digital multiplexer for the 2 Mbit / s network level", published by Siemens AG, Transmission Systems Division, PO Box 700073, order no. A .2020-S154-A1-2-29 known.
- 64 kbit / s signals or signals with a multiple bit rate can be subjected to a time segment assignment. In the latter case, several bytes per frame must be routed over the switching matrix. If these would arrive in two different frames at a first output of the switching network, then a time compensation can be achieved according to the application note "Memory Time Switch Large", PEB 2047, Siemens AG, 12/89, in that the at least one, bytes that actually get into the first frame are instead fed back from a second output of the switching matrix via a loop to a further input. This causes a delay of this byte in the switching matrix by one frame duration, and finally all the bytes at the first output of the switching matrix arrive in the same subsequent frame. However, this causes a reduction in the number of effectively usable ones
- a flexible multiplexer is designed for a certain number of line units with a certain number of channel units contained in them.
- a connection unit can contain a different number of channel units, so that the multiplexer also has a more or less large number of connection units.
- the coupling network must always be designed so that it can serve the maximum number of channel units.
- the object of the invention is to ensure the byte integrity for the former case without substantial modification of a basic device and to increase the number of connection units for the second case if necessary.
- This method accordingly makes it possible to accommodate extension switching matrixes separately from the main switching matrixes and to use them as required.
- channels can be switched through without and with a delay.
- the former is sought in particular for signals which have only one byte per frame and are to be switched through with the shortest possible transit time.
- the latter can be used to ensure byte integrity in the case of n x 64 kbit / s signals. In this case the number of connection units is small and the unused additional connection options or the available additional crosspoints can be used for loop switching.
- the basic device is a frame that is filled with connection units connected to the main switching matrix.
- the expansion switching networks are also included in this, while the additional connection units are inserted into a second frame for reasons of space, from which they are connected to the expansion switching networks.
- Loops are only attached to the extension coupling fields so that the capacity of the main coupling fields, that is to say the number of coupling points available for direct switching through, is retained. If coupling points for loops had to be provided in the main switching matrixes, only a smaller number of connection units could be served and the first frame would remain partially empty.
- FIG. 1 shows a block diagram of a flexible multiplexer according to an older proposal, shows a subscriber-side connection unit according to this older proposal, shows a line-side connection unit according to this older proposal, shows a block diagram of a flexible multiplexer according to the invention, shows a block diagram of a main and extension switching matrix and shows this main and extension switching matrix with commercially available integrated circuits.
- Figure 1 shows the block diagram of the flexible multiplexer according to the older proposal.
- This contains subscriber-side connection units T 7a, 8a, 9, 10 and 11, line-side connection units L 12, 13 and 14, a control device 15, a voice / data main switching matrix 16a, an identifier main switching matrix 17a, voice / data Buses 18a and 19a, license plate buses 20a and 21a, voice / data multiplex signal lines 22a, 22d, 23a and 23d, label multiplex signal lines 24a, 24d, 25a and 25d and a control bus 26 which connects to all subscriber-side connection units 7a, 8a , 9, 10 and 11 and all main switching networks 16a and 17a is connected.
- the designation S / D means that either voice or data signals can be transmitted in one time period.
- the designation Kz stands for license plate signals.
- FIG. 2 shows the subscriber-side connection unit T with eight channel units K, time / space couplers 27 and 28 and space / time couplers 29 and 30.
- the channel units K and the time / space couplers 27 and 28 on the one hand and the space / time Couplers 29 and 30, on the other hand, are connected to one another by interconnecting connections identified by the same three-digit numbers.
- the time / space couplers 27 and 28 and space / time couplers 29 and 30 are set via the control bus 26.
- Input signals with a bit rate of nx 64 kbit / s are converted into n bytes per frame.
- FIG. 3 shows a line-side connection unit L with a frame multiplexer 31 and a frame demultiplexer 32.
- M denotes multiplex signals. These can be 2048 kbit / s signals, for example, in the 16 th frame of which 4-bit identifier words are transmitted for two channels. The latter are converted into bytelange tag words.
- the subscriber-side connection units T are connected in groups.
- the subscriber-side connection units 7a and 8a and other subscriber-side connection units T form a group, each of which is connected via four multiplex signal lines 22a to 25a to the buses 18a to 21a which emanate from the main switching matrixes 16a and 17a in a star shape.
- the line-side connection units L are also connected to these; the line-side connection unit 12, for example, via the multiplex signal lines 22d to 25d.
- the main switching matrixes 16a and 17a and the buses 18a to 21a are components of a controller CTR.
- FIG. 4 shows a flexible multiplexer according to the invention. In a frame I, this contains the controller CTR known from FIG.
- the switching network extension SNE contains a voice / data extension switching matrix 16b and a flag extension switching matrix 17b in optionally different sizes.
- the buses 18a to 21a which are already known from FIG. 1, are continued asymmetrically via the switching interface 45-48 to the extension switching fields 16b and 17b.
- buses 18b to 21b are brought to these expansion switching fields via symmetrical frame interfaces 35 to 38, from which multiplex signal lines 22b to 25b and 22c to 25c to the subscriber-side connection units 7b and 8b and 7c and 8c are implemented.
- Bus loops 33 and 34 are also connected for delay.
- FIG. 5 shows a block diagram of a voice / data main switching matrix 16a with a voice / data expansion switching matrix 16b. This block diagram applies correspondingly to an identifier main switching matrix 17a with an identifier extension switching matrix 17b.
- Their reference numbers are in parentheses.
- Periods in the voice / data multiplex input signals S / D-EMI or in the flag multiplex input signals Kz-EM1 can either via the voice / data main switching matrix 16a or the flag main switching matrix 17a in voice / data multiplex output signals S / D- AMI or flag multiplex output signals Kz-AM1 or via the voice / data expansion switching matrix 16b or the flag extension switching matrix 17b in voice / data multiplex output signals S / D-AM2 or S / D-AM3 or flag multiplex output signals Kz-AM2 or Kz-AM3 are routed.
- Voice / data multiplex input signals S / D-EM2 or flag multiplex input signals Kz-EM2 can be via the voice / data expansion switching matrix 16b or the flag extension switching matrix 17b either in voice / data multiplex output signals S / D-AMI or Tag multiplex output signals Kz-AM1 or voice / data multiplex output signals S / D-AM2 or S / D-AM3 or tag multiplex output signals Kz-AM2 or Kz-AM3 can be rearranged.
- Time segments of the multiplex output signals S / D-AM3 and Kz-AM3 can be delayed by one frame duration as multiplex input signals S / D-EM3 or Kz-EM3 via the bus loops 33 and 34, which can be formed from one or more lines .
- a multiple loop can also be formed along the dashed arrow.
- Figure 6 shows the implementation of the block diagram of Figure 5 with integrated circuits PEB 2047 under the reference numerals 16a, 39, 40 and 41 for voice / data and 17a, 42, 43 and 44 for identification.
- the numbers with an asterisk indicate how many S / D or Kz multiplex signal lines each run in parallel, and the numbers 512 and 1024 - assigned values in brackets - indicate the possible number of channels on the buses 18a to 21a and 18b to 21b 64 kbit / s signals.
- the buses 18a to 21a of the controller CTR are connected to the switching network extension SNE via the asymmetrical switching network interfaces 45 to 48.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3504185A JPH088553B2 (en) | 1990-04-06 | 1991-02-28 | Method and apparatus for a flexible multiplexer |
BR919106317A BR9106317A (en) | 1990-04-06 | 1991-02-28 | PROCESS AND ARRANGEMENT FOR FLEXIBLE MULTIPLEXING |
NO923872A NO923872D0 (en) | 1990-04-06 | 1992-10-05 | PROCEDURE AND DEVICE FOR FLEXIBLE MULTIPLE Plexing |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4011264.0 | 1990-04-06 | ||
DE19904011264 DE4011264A1 (en) | 1990-04-06 | 1990-04-06 | Flexible multiplexing procedure for programmable digital multiplexer |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991015905A1 true WO1991015905A1 (en) | 1991-10-17 |
Family
ID=6403959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1991/000178 WO1991015905A1 (en) | 1990-04-06 | 1991-02-28 | Flexible-multiplexing process and device |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0523059A1 (en) |
JP (1) | JPH088553B2 (en) |
AU (1) | AU637460B2 (en) |
BR (1) | BR9106317A (en) |
CA (1) | CA2079793A1 (en) |
DE (1) | DE4011264A1 (en) |
WO (1) | WO1991015905A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19748956B4 (en) * | 1997-10-29 | 2005-09-22 | Detewe Deutsche Telephonwerke Aktiengesellschaft & Co. Kg | Circuit arrangement for non-blocking coupling fields |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4524442A (en) * | 1983-06-22 | 1985-06-18 | Gte Automatic Electric Inc. | Modularly expandable space stage for a T-S-T digital switching system |
US4725835A (en) * | 1985-09-13 | 1988-02-16 | T-Bar Incorporated | Time multiplexed bus matrix switching system |
-
1990
- 1990-04-06 DE DE19904011264 patent/DE4011264A1/en not_active Withdrawn
-
1991
- 1991-02-28 JP JP3504185A patent/JPH088553B2/en not_active Expired - Lifetime
- 1991-02-28 EP EP19910904061 patent/EP0523059A1/en not_active Withdrawn
- 1991-02-28 CA CA 2079793 patent/CA2079793A1/en not_active Abandoned
- 1991-02-28 WO PCT/DE1991/000178 patent/WO1991015905A1/en not_active Application Discontinuation
- 1991-02-28 BR BR919106317A patent/BR9106317A/en unknown
- 1991-02-28 AU AU72474/91A patent/AU637460B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4524442A (en) * | 1983-06-22 | 1985-06-18 | Gte Automatic Electric Inc. | Modularly expandable space stage for a T-S-T digital switching system |
US4725835A (en) * | 1985-09-13 | 1988-02-16 | T-Bar Incorporated | Time multiplexed bus matrix switching system |
Non-Patent Citations (1)
Title |
---|
Proceedings IEEE Military Communications Conference 5-9 Oktober 1986, Monterey, CA Conference Record, Band 1 von 3 IEEE (US) J.A. Vigil: "A new integrated multiplex, patch, and test (IMPATTM) system", Seiten 341-345 * |
Also Published As
Publication number | Publication date |
---|---|
JPH05502354A (en) | 1993-04-22 |
AU637460B2 (en) | 1993-05-27 |
AU7247491A (en) | 1991-10-30 |
EP0523059A1 (en) | 1993-01-20 |
CA2079793A1 (en) | 1991-10-07 |
BR9106317A (en) | 1993-04-20 |
JPH088553B2 (en) | 1996-01-29 |
DE4011264A1 (en) | 1991-10-10 |
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