WO1992008231A1

WO1992008231A1 - Rom patch device

Info

Publication number: WO1992008231A1
Application number: PCT/US1991/008098
Authority: WO
Inventors: Yao T. Yen
Original assignee: Transcomputer, Inc.
Priority date: 1990-11-02
Filing date: 1991-11-01
Publication date: 1992-05-14

Abstract

A device for enhancing the program code of a first ROM inlcudes an original ROM (10) connected to address and data busses (12 and 14, respectively) in parallel with a patch ROM (22). The original ROM (10) contains a given set of code or data, while the patch ROM (22) contains replacement code or data, such as enhancements to the code. A select ROM (20) has inputs connected to the address bus (12) and outputs (18 and 19) connected to the chip select input pins of the original and patch ROMs (10 and 22, respectively). When the ROMs are addressed, the select ROM selects either the original ROM (10) or the patch ROM (22), depending upon the address. The select ROM (20) controls the data bus by enabling the appropriate chip select pins of the original and patch ROMs (10 and 22, respectively).

Description

ROM PATCH DEVICE BACKGROUND Field of the Invention

The present invention relates to an apparatus for use in conjunction with an existing ROM which contains original information stored as binary bits. The information provided by the apparatus is different from the original information even though the original information stored in the ROM is not altered.

Discussion of the Prior Art

The information stored as binary bits in a read¬ only-memory (ROM) cannot be selectively changed. In order to change ROM code, a new program mask must be made. Similarly, with programmable-read-only- memories (PROM) and electrically-programmable-read¬ only-memories (EPROM) a device must be entirely reprogrammed. The same is true of EAROMs and certain classes of EEPROMs. In other words, if one wanted to duplicate the information stored in a ROM except for changing a few locations, the entire code must copied into the data space of a blank device. (With certain classes of EEPROMs, the device can be byte erased and reprogrammed.) Because PROMs and EPROMs are merely subclasses of ROMs, insofar as this invention are concerned, we will only refer to ROMs. It will be understood that a reference to a ROM also refers to PROMs, EPROMs, EAROMs and EEPROMs.

More importantly, ROMs or systems containing ROMs are sold where the ROM (or PROM or EPROM) contains the vendor's copyrighted software or data. A common example of such a system is a personal computer (PC) containing a basic input/output system (BIOS) ROM which contains program code that handles microprocessor-to-peripheral communications for the PC. A user or a value added reseller (VAR) could develop a BIOS program which merely enhanced the performance of one or several of the BIOS routines by programming a new ROM, PROM or EPROM to contain most of the original copyrighted program code with the enhancements developed by the user However, this is copyright infringement.

Thus, the end user is limited to the BIOS code provided by the PC vendor or to developing an entirely new code in a so called clean room. A device is needed to allow a user to develop and implement enhancements to software or data stored in a ROM, PROM or EPROM without infringing a copyright in the original data or software.

SUMMARY OF THE INVENTION A device for enhancing the program code of a first ROM is presented. An original ROM is connected to address and data busses in parallel with a patch ROM. The original ROM contains a given set of code or data, while the patch ROM contains replacement code or data, such as enhancements to the code. A select ROM has inputs connected to the address bus and outputs connected to the chip select input pins of the original and patch ROMs. When the ROMs are addressed, the select ROM selects either the original ROM or the patch ROM, depending upon the address.

The select ROM controls the data bus by enabling the appropriate chip select pins of the original and patch ROMs.

In the preferred embodiment, the patch and select ROM's are contained in a single module, which plugs into the socket provided for the original ROM. The original ROM is then plugged into the module to complete the interconnections among the ROMs.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a ROM and socket module according to the prior art.

Figure 2 is a block diagram of a Rom patch device according to the present invention.

Figure 3 is a side elevation view of the prior art.

Figure 4 is a side elevation view of a ROM patch module according to the present invention.

Figure 5 is a bottom view of the ROM patch module of Figure 4.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to Figure 1, a ROM 10, as is well known, contains program code stored to be retrievable by a series of binary address locations. A typical ROM 10, such as an Intel 2764 EPROM, has an address bus 12 for selecting an appropriate memory location, a data bus for providing the information stored in the selected memory location and a chip select pin 16 to activate the ROM so that the information stored in the selected memory location becomes available external to the ROM. In the absence of the appropriate logic signal on the chip select line 16, the lines of the data bus remain floating.

A typical function of a ROM 10 in a PC is to control the Basic Input/Output System (BIOS) , so that the ROM 10 contains instructions to enable the microprocessor to communicate with peripheral equipment such as printers, displays, memory controllers and the like. When the ROM 10 is enabled, program instructions beginning at the address on the address bus 12 are presented on the data bus 14.

In Figure 2, the ROM patch device of the present invention enables the user to enhance or alter the instructions provided by an original ROM without altering the instructions which are stored in the original ROM 10, and thus, without infringing the copyright on the BIOS code. As in Figure 1, the address bus 12 is tied to the input and the data bus 14 is tied to the output of the ROM 10. The select

ROM 20 and the patch ROM 22 are connected in parallel to the ROM 10 with respect to the address bus 12; i.e., the address bus 12 is coupled to the input of both the select ROM 20 and the patch ROM 22. However, only the output of the patch ROM 22 is coupled in parallel to the original ROM 10 with respect to the data bus 14.

ROM 20 and ROM 22 may be user programmable EPROMs. In this case, the contents of the ROM 20 and the ROM 22 contained in device 54 may be initially blank. A user may plug device 54 into a commercially available PROM programming equipment, and program each of ROM 20 and ROM 22 sequentially. In this useful application, the chip selects 18 and 19 are brought to the external pins Jl and J2, as shown in Figure 2. The external pins Jl and J2 may be connected by an external cable to the PROM programming equipment. By controlling the signals applied to the external pins Jl and J2, the address bus 12 and the data bus 14 available at the socket pins 60, the contents of the ROMs 20 and 22 can be programmed to suit a particular user application.

Commercially available ROMs have eight lines in the data bus to provide a byte of binary data for each location addressed. Only two of the output lines of the of the select ROM 20 are used for the present invention: a first output line is coupled as the chip select 18 of the original ROM 10 and a second output line is coupled as the chip select 19 of the patch ROM 22. Further, the chip select 16 for selecting the original ROM 10 before the ROM patch device is used, is now coupled to enable the select ROM 20. Thus, whenever a host system would have accessed data or code from the original ROM 10, it will now access data or code from either the original ROM 10 or the patch ROM 22 under control of the select ROM 20.

Preferably, every address location having a corresponding valid address in the original ROM 10 has information stored in the select ROM 20. In each case, the data site that supplies a binary bit as the chip select 18 to the original ROM 10 will contain the opposite binary condition as the data site that supplies a binary bit as the chip select 19 to the patch ROM 22 so that only one or the other of the original ROM 10 or the patch ROM 22 can drive the data bus 14. In other words, the select ROM is coded so that either the original ROM or the patch ROM are enabled but not both.

The ROM 22 contains alternative or substitute instructions that are programmed by the user. For example. Table I contains a series of sample instructions for the original ROM 10, the select ROM 20 and the patch ROM 22.

Address Original ROM

1 instruction A

2 instruction B 3 instruction C

4 instruction D

5 instruction E

6 instruction F

7 instruction G 8 instruction H

9 instruction I

10 instruction J

11 instruction K

12 instruction L 13 instruction M

14 instruction N

15 instruction O

The original ROM 10 contains fifteen original instructions A - O. The user wants to modify the software by substituting the alternate instruction F and alternate instruction J for the original instructions F and J stored in address 6 and 10, respectively. The select ROM has eight outputs because that is the type of device commercially available. The first output is used to drive the original ROM's chip select and the second output is used to drive the patch ROM's chip select. In each address, the condition of the first and second outputs for the select ROM are opposite. In each case, except for addresses 6 and 10, the first output is a binary "1" and the second output is a binary "0" to select the original ROM. For addresses 6 and 10, the binary conditions are reversed to select the patch ROM. The remaining six outputs do not matter to this invention and are indicated by an "x" for a "don't care" condition.

Ordinarily, when the original ROM 10 contains a BIOS program it is packaged in a dual-in-line (DIP) package and mounted in a socket 50 on a PC mother board 52 as shown in Figure 3 rather than being soldered. In the preferred embodiment of the present invention shown in Figure 4, the original ROM 10 is removed from the socket 50 and is inserted into a socket 58 on a ROM patch device 54. The ROM patch device 54 includes a printed circuit board 56 on which the select ROM 20 and the patch ROM 22 are mounted. Preferably, the select ROM 20 and the patch ROM 22 are packaged in leadless chip carrier (LCC) packages. Thus, they are sufficiently small to fit within the boundaries of the pins 60 on the printed circuit board 56 as shown in Figure 5.

The printed circuit board 56 includes the appropriate interconnection traces to electrically couple the socket 58 for the original ROM 10, the select ROM 20 and the patch ROM 22 to one another and to the appropriate pins 60. The ROM patch device 54 is inserted into the socket 50 on the PC mother board 52 by the pins 62. Thus, the ROM patch device 54 does not require any additional space on the mother board 52. In such a design, ROM patch device 54 has length and width substantially identical to ROM 10, but the height is slightly increased. Ordinarily, this will not be a problem.

It should be understood that the invention is not intended to be limited by the specifics of the above-described embodiment, but rather defined by the accompanying claims. For example, in the event that LCC packaged ROMs are not available, the physical configuration of the module would necessarily be changed. Further, three or more outputs of the select ROM could be used to select from among information stored in three or more ROMs.

Claims

C L A I M SWhat is claimed is:

1. A memory device comprising: first and second memory chips coupled in parallel to an address bus and a data bus and each having a chip select input pin, wherein the second memory chip contains data at one or more specified locations for replacing the data stored at corresponding locations of the first memory chip; and a selector chip having address input pins coupled to the address bus and having data output pins coupled to the chip select input pins of the first and second memory chips, wherein the selector chip contains data that when output selects the second memory chip when one of the specified locations is addressed and selects the first memory chip when any other location is addressed.

2. A device for patching data contained in a first memory chip containing first address pins, first data pins, and a first chip select pin, said device comprising: a plurality of signal pins coupled to receive an address and a chip select from an external device and to transmit data to the external device; a plurality of first sockets for receiving and contacting the pins of the first memory chip, including address, data and chip select sockets corresponding to the first address, first data, and first chip select pins, respectively, of the first memory chip so that the address and data first sockets are coupled to the address and data signal pins, respectively; a plurality of second sockets for receiving and contacting pins of a patch memory chip having second address pins, second data pins and a second chip select pin, the plurality of second sockets including address, data and chip select sockets corresponding to the second address, second data, and second chip select pins, respectively, of the patch memory chip so that the address and data second sockets are coupled to the address and data signal pins, respectively; and a plurality of third sockets for receiving and contacting pins of a select memory chip having third address pins, third data pins and a third chip select pm, the plurality of third sockets including address, data and chip select sockets corresponding to the third address, third data, and third chip select pins, respectively, of the select memory chip so that the address and chip select third sockets are coupled to the address and chip select signal pins, respectively and one of the data third sockets is coupled to each of the second and third chip select sockets.

3. The device of Claim 2, wherein the plurality of first, second and third sockets are combined on a single modular package.

4. A device for enhancing a program code stored in a first ROM, wherein the first ROM has a first input coupled to an address bus, a first output coupled to a data bus, and a first select pin for enabling the first ROM, whereby presentation of a valid address on the address bus to the first input combined with enabling of the first ROM by activating the first select pin causes data stored at the valid address in the ROM to be presented on the data bus, the device comprising: a) a second ROM having a second input coupled to the address bus, a second output coupled to the data bus, and a second select pin for enabling the second ROM, whereby presentation of a valid address on the address bus to the second input combined with enabling of the second ROM by activating the second select pin causes data stored at the valid address in the second ROM to be presented on the data bus; and b) a third ROM having a third input coupled to the address bus, and a first and a second output pin, wherein the first output pin is coupled to the first select pin, and the second output pin is coupled to the second select pin, and whereby the third ROM is programmed to activate only one of the first ROM or the second ROM.

5. The device of Claim 4, wherein the modular package is inserted into a socket on a printed circuit board, and wherein the first ROM is coupled to the modular package.