WO1992021088A1 - Novel electrical bus structure - Google Patents

Novel electrical bus structure Download PDF

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Publication number
WO1992021088A1
WO1992021088A1 PCT/US1992/003977 US9203977W WO9221088A1 WO 1992021088 A1 WO1992021088 A1 WO 1992021088A1 US 9203977 W US9203977 W US 9203977W WO 9221088 A1 WO9221088 A1 WO 9221088A1
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WO
WIPO (PCT)
Prior art keywords
data
bus
bus structure
source device
data source
Prior art date
Application number
PCT/US1992/003977
Other languages
French (fr)
Inventor
James Earl Mcgarvey
Original Assignee
Eastman Kodak Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Company filed Critical Eastman Kodak Company
Publication of WO1992021088A1 publication Critical patent/WO1992021088A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This invention relates to an electrical bus structure.
  • An electrical bus structure is a known and important entity that can function, for example, in a modular image processing system, as an interface between, on the one hand, a data source device including e.g., memory devices, encryption devices or transmission devices, and on the other hand, a data destination device, including e.g., memory devices, compression devices or displays.
  • a data source device including e.g., memory devices, encryption devices or transmission devices
  • a data destination device including e.g., memory devices, compression devices or displays.
  • Fig. 1 shows a typical electrical bus structure 10.
  • the bus structure 10 can function as an interface between a data source device 12 and a data destination device 14.
  • the bus structure 10 further includes a controller 16 i.e., a conventional central processing unit (CPU) , and address bus lines 18, data bus lines 20, and control bus lines 22.
  • the bus structure further includes sundry interconnect lines between the three sets of bus lines 18, 20, 22, and the controller 16 and source and destination devices 12, 14, respectively.
  • the Fig. 1 bus structure 10 can transfer a datum from the data source device 12, to the data destination device 14, by way of a two-step process.
  • the controller 16 can generate an address, by way of well-known read command instructions along the control bus line 22, to the data source 12, thereby specifying the address of the datum to be transferred by the bus 10.
  • the controller 16 can generate an address, by a way of well-known write command instructions along the control bus line 22, to the data destination device 14, thereby specifying the address in the data destination device 14 to which the datum is to be now transferred along the data bus lines 20.
  • Fig. 1 bus structure 10 conforms, generally, to a speed transmission vs. power consumption curve shown in Fig. 2.
  • the Fig. 2 curve suggests that the speed of data transmission is directly proportional to the power requirements of the bus structure.
  • Fig. 1 bus structure 10 increased speed of data transmission may be accommodated/ for example, by way of adding extra data bus lines to the structure 10, (as shown), to thereby (incrementally) handle 8, 16, 32, 64 ... bit capacities.
  • this action is at the expense or trade-off of increased power consumption.
  • Fig. 2 suggests that a relative reduction in the Fig. " 1 bus structure power consumption requires a corresponding diminution in the speed of the data transmission. (This trade-off of speed versus power, is in part a consequence of the two-step controller addressing process, alluded to above.)
  • a bus structure that operates in accordance with the Fig. 2 speed/power curve, has been acceptable for use in modular image processing systems, since the data source and data destination devices typically comprise large, heavy and independent units. These non-portable units can be adequately equipped with A.C. power supplies typically rated in excess of 200 watts power consumption, to thereby accommodate a satisfactory speed of data transmission.
  • the integrated system is specified to be not only small (e.g., less than 10 pounds), but have a power consumption of less than 5 watts, while retaining the data speed capabilities of at least that of the modular image processing systems.
  • the novel electrical bus structure has a critical advantage of facilitating the advent of portable image processing systems that can preserve all the features and capabilities of large-scale modular image processing systems, including high speeds of data transmission, for example, image data transmission, while at the same time, dispensing with the heretofore seemingly dictated (Fig. 2) high power consumption supply, in favor of a portable, low power (A.C. or D.C.) supply, e.g., less than 5 watts, battery-operated supply.
  • A.C. or D.C. portable, low power
  • the novel electrical bus structure comprises: a) a controller comprising a central processing unit (CPU); b) a data source device comprising an interface control unit; c) a data destination device comprising an interface control unit; d) an address bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; e) a first data bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; f) a control bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; g) a second data bus that can connect the data source device to the data destination device; and h) a transfer control bus that can connect the control unit of the data source device to the control unit of the data destination device.
  • CPU central processing unit
  • a data source device comprising an interface control unit
  • c) a data destination device comprising an interface control unit
  • Fig. 1 shows an extant electrical bus structure
  • Fig. 2 shows an electrical bus structure function comprising a speed of data transmission versus power consumption curve
  • Fig. 3 shows a novel electrical bus structure of the present invention
  • Fig. 4 shows a flowchart incorporated in an operation of the Fig. 3 bus structure.
  • the Fig. 3 shows a preferred bus structure 24.
  • the bus structure can function as an interface between at least one data source device 26 comprising, for example, a memory device or an encryption device, and at least one data destination device 28 comprising, for example, a compression device, a display or a memory device.
  • the data source device 26 and the data destination device 28 each include an interface control unit (numerals 30, 32).
  • the illustrative interface control unit 30 preferably comprises at least one conventional diode circuit 34, comprising a "Ready” signal input line 36 (i.e., a signal which is “True” when the data source device 26 is ready to output a datum) , an "Enable” signal output line 38 (i.e., a signal which enables the data source device 26 to output a datum), and an interconnect line 40 (40*) to a transfer control bus 42.
  • the interface control units 30, 32 act cooperatively with the transfer control bus 42, to function as a wired AND gate.
  • Fig. 3 shows that the electrical bus structure 24 further includes a controller 44 comprising a conventional central processing unit (CPU) .
  • the controller 44 can communicate with the data source device 26 and the data destination device 28 by way of an address bus 46, a first data bus 48, and a control bus 50.
  • the Fig. 3 bus structure 24 is completed by noting firstly that the interface control units 30, 32 of the data source device 26 and the data destination device 28, respectively, can directly communicate by way of a second data bus 52.
  • the "Enable" signal output line 38 is connected via the second data bus 52 to an "Enable” signal input line 54 in the interface control unit 32.
  • an optional clock line 56 can be provided for synchronous coordination of a data flow.
  • the controller 44 may be programmed so that it can dedicate low speed data transmission (hence low power consumption) to that part of the bus structure 24 comprising the address bus 46, the first data bus 48, and the control bus 50. Further, a low speed datum may be processed by the controller 44 along these routes (46, 48, 50) from the data source device 26 to the data destination device 28, and by the two stage process described above for the bus structure 10 shown in Fig. 1. As noted above, the two-stage process is relatively slow, but since a low speed datum has been assigned to this process, there is no overall loss of efficiency; at the same time, the power consumption is kept desirably low.
  • the controller 44 may be programmed so that it can dedicate the transfer of high speed data, for example, image data, again initially by way of the address bus 46, the first data bus 48, and the control bus 50, but now with a further constraint that a high speed datum is only to be transferred from the data source device 26 to the data destination device 28 by way of the interface control units 30, 32 and the second data bus 52.
  • the transfer takes place via the wired AND gate logic disclosed above, and therefore the transfer of the datum takes place when all the "Ready" signal input lines are (preferably) logic high. Since the transfer takes place, accordingly, as a one step wired AND gate process, the transfer of high speed data can be effected concurrently with a desirable low power consumption.
  • the flowchart 58 comprises a program that can be effected by the Fig. 3 controller 44.
  • An instruction 60 comprises that the controller 44 load a data source device 26 address.
  • An instruction 62 comprises that the controller 44 enables the data source device 26.
  • a further instruction 64 comprises that the controller 44 loads a data destination device 28 address.
  • An instruction 66 comprises that the controller 44 enables the data destination device 28.
  • the final flowchart instruction 68 signifies that when all the enablements are effected, a transfer of at least one datum occurs along the second data bus 52, and with synchronization with the logic on the transfer control bus 42.

Abstract

A novel electrical bus structure suitable for use in an integrated, portable image processing system. The bus structure provides an interface between components of the image processing system, the components comprising a data source device and a data destination device. The bus structure has concurrent capabilities of realizing very high speeds of data transmission and very low power consumption.

Description

NOVEL ELECTRICAL BUS STRUCTURE
BACKGROUND OF THE INVENTION This invention relates to an electrical bus structure.
INTRODUCTION TO THE INVENTION An electrical bus structure is a known and important entity that can function, for example, in a modular image processing system, as an interface between, on the one hand, a data source device including e.g., memory devices, encryption devices or transmission devices, and on the other hand, a data destination device, including e.g., memory devices, compression devices or displays.
Fig. 1 shows a typical electrical bus structure 10. The bus structure 10 can function as an interface between a data source device 12 and a data destination device 14. To this end, the bus structure 10 further includes a controller 16 i.e., a conventional central processing unit (CPU) , and address bus lines 18, data bus lines 20, and control bus lines 22. The bus structure further includes sundry interconnect lines between the three sets of bus lines 18, 20, 22, and the controller 16 and source and destination devices 12, 14, respectively.
In operation, the Fig. 1 bus structure 10 can transfer a datum from the data source device 12, to the data destination device 14, by way of a two-step process. First, the controller 16 can generate an address, by way of well-known read command instructions along the control bus line 22, to the data source 12, thereby specifying the address of the datum to be transferred by the bus 10. Second, the controller 16 can generate an address, by a way of well-known write command instructions along the control bus line 22, to the data destination device 14, thereby specifying the address in the data destination device 14 to which the datum is to be now transferred along the data bus lines 20.
SUMMARY OF THE INVENTION The operation of the Fig. 1 bus structure 10 conforms, generally, to a speed transmission vs. power consumption curve shown in Fig. 2. The Fig. 2 curve suggests that the speed of data transmission is directly proportional to the power requirements of the bus structure.
Accordingly, for the Fig. 1 bus structure 10, increased speed of data transmission may be accommodated/ for example, by way of adding extra data bus lines to the structure 10, (as shown), to thereby (incrementally) handle 8, 16, 32, 64 ... bit capacities. However, this action is at the expense or trade-off of increased power consumption. On the other hand. Fig. 2 suggests that a relative reduction in the Fig." 1 bus structure power consumption requires a corresponding diminution in the speed of the data transmission. (This trade-off of speed versus power, is in part a consequence of the two-step controller addressing process, alluded to above.)
Heretofore, a bus structure that operates in accordance with the Fig. 2 speed/power curve, has been acceptable for use in modular image processing systems, since the data source and data destination devices typically comprise large, heavy and independent units. These non-portable units can be adequately equipped with A.C. power supplies typically rated in excess of 200 watts power consumption, to thereby accommodate a satisfactory speed of data transmission.
In contrast to the modular image processing systems, and their acceptable speed/power specifications, I am now required to design a bus structure that is suitable for use as an interface between data source and destination devices for a small, portable and integrated image processing system. The integrated system is specified to be not only small (e.g., less than 10 pounds), but have a power consumption of less than 5 watts, while retaining the data speed capabilities of at least that of the modular image processing systems.
For this situation, I have determined that the extant bus structure architectures, while suitable for the modular image processing systems, may not be viable for the portable integrated system. This follows since the extant bus structures conform to the Fig. 2 speed/power trade-offs, while the portable integrated system, in sharp contrast, must realize high speed concurrently with very low power consumption.
I have now invented a novel electrical bus structure that can provide an interface between data source and data destination devices, and that is suitable for use in an integrated, portable image processing system. The novel electrical bus structure has a critical advantage of facilitating the advent of portable image processing systems that can preserve all the features and capabilities of large-scale modular image processing systems, including high speeds of data transmission, for example, image data transmission, while at the same time, dispensing with the heretofore seemingly dictated (Fig. 2) high power consumption supply, in favor of a portable, low power (A.C. or D.C.) supply, e.g., less than 5 watts, battery-operated supply.
The novel electrical bus structure comprises: a) a controller comprising a central processing unit (CPU); b) a data source device comprising an interface control unit; c) a data destination device comprising an interface control unit; d) an address bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; e) a first data bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; f) a control bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; g) a second data bus that can connect the data source device to the data destination device; and h) a transfer control bus that can connect the control unit of the data source device to the control unit of the data destination device.
BRIEF DESCRIPTION OF THE DRAWING The invention is illustrated in the accompanying drawing, in which: Fig. 1 shows an extant electrical bus structure;
Fig. 2 shows an electrical bus structure function comprising a speed of data transmission versus power consumption curve;
Fig. 3 shows a novel electrical bus structure of the present invention; and
Fig. 4 shows a flowchart incorporated in an operation of the Fig. 3 bus structure.
DETAILED DESCRIPTION OF THE INVENTION A detailed description of a preferred electrical bus structure of the present invention, as summarized above, is first set forth with reference to Fig. 3. The operation of the Fig. 3 bus structure is then disclosed, with particular attention to the Fig. 4 flowchart.
The Fig. 3 shows a preferred bus structure 24. The bus structure can function as an interface between at least one data source device 26 comprising, for example, a memory device or an encryption device, and at least one data destination device 28 comprising, for example, a compression device, a display or a memory device. The data source device 26 and the data destination device 28 each include an interface control unit (numerals 30, 32). The illustrative interface control unit 30 preferably comprises at least one conventional diode circuit 34, comprising a "Ready" signal input line 36 (i.e., a signal which is "True" when the data source device 26 is ready to output a datum) , an "Enable" signal output line 38 (i.e., a signal which enables the data source device 26 to output a datum), and an interconnect line 40 (40*) to a transfer control bus 42. Note that the interface control units 30, 32 act cooperatively with the transfer control bus 42, to function as a wired AND gate.
Fig. 3 shows that the electrical bus structure 24 further includes a controller 44 comprising a conventional central processing unit (CPU) . The controller 44 can communicate with the data source device 26 and the data destination device 28 by way of an address bus 46, a first data bus 48, and a control bus 50.
The Fig. 3 bus structure 24 is completed by noting firstly that the interface control units 30, 32 of the data source device 26 and the data destination device 28, respectively, can directly communicate by way of a second data bus 52. In particular, the "Enable" signal output line 38 is connected via the second data bus 52 to an "Enable" signal input line 54 in the interface control unit 32. Secondly, an optional clock line 56 can be provided for synchronous coordination of a data flow. The operation of the Fig. 3 bus structure 24, in overview, is as follows.
First, the controller 44 may be programmed so that it can dedicate low speed data transmission (hence low power consumption) to that part of the bus structure 24 comprising the address bus 46, the first data bus 48, and the control bus 50. Further, a low speed datum may be processed by the controller 44 along these routes (46, 48, 50) from the data source device 26 to the data destination device 28, and by the two stage process described above for the bus structure 10 shown in Fig. 1. As noted above, the two-stage process is relatively slow, but since a low speed datum has been assigned to this process, there is no overall loss of efficiency; at the same time, the power consumption is kept desirably low.
Second, the controller 44 may be programmed so that it can dedicate the transfer of high speed data, for example, image data, again initially by way of the address bus 46, the first data bus 48, and the control bus 50, but now with a further constraint that a high speed datum is only to be transferred from the data source device 26 to the data destination device 28 by way of the interface control units 30, 32 and the second data bus 52. The transfer takes place via the wired AND gate logic disclosed above, and therefore the transfer of the datum takes place when all the "Ready" signal input lines are (preferably) logic high. Since the transfer takes place, accordingly, as a one step wired AND gate process, the transfer of high speed data can be effected concurrently with a desirable low power consumption.
Attention is now directed to the Fig. 4 flowchart 58, which references this operation. The flowchart 58 comprises a program that can be effected by the Fig. 3 controller 44.
An instruction 60 comprises that the controller 44 load a data source device 26 address. An instruction 62 comprises that the controller 44 enables the data source device 26.
A further instruction 64 comprises that the controller 44 loads a data destination device 28 address. An instruction 66 comprises that the controller 44 enables the data destination device 28. The final flowchart instruction 68 signifies that when all the enablements are effected, a transfer of at least one datum occurs along the second data bus 52, and with synchronization with the logic on the transfer control bus 42.

Claims

WHAT IS CLAIMED IS:
1. An electrical bus structure comprising: a) a controller comprising a central processing unit (CPU) ; b) a data source device comprising an interface control unit; c) a data destination device comprising an interface control unit; d) an address bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; e) a first data bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; f) a control bus that can connect i) the CPU and the data source device; and ii) the CPU and the data destination device; g) a second data bus that can connect the data source device to the data destination device; and h) a transfer control bus that can connect the control unit of the data source device to the control unit of the data destination device.
2. An electrical bus structure according to claim 1, wherein the data source device comprises a memory.
3. An electrical bus structure according to claim 1, wherein the data destination device comprises a display.
4. An electrical bus structure according to claim 1, wherein a wired AND gate circuit comprises a) the transfer control bus; b) the control unit of the data source device; and c) the control unit of the data destination device.
5. An electrical bus structure according to claim 4, wherein the wired AND gate circuit comprises a diode circuit.
PCT/US1992/003977 1991-05-17 1992-05-14 Novel electrical bus structure WO1992021088A1 (en)

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US70264591A 1991-05-17 1991-05-17
US702,645 1991-05-17

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WO2000025225A1 (en) * 1998-10-12 2000-05-04 Oce Printing Systems Gmbh Data bus and method for establishing communication between two modules by means of such a data bus
US7047340B1 (en) 1998-10-12 2006-05-16 Oce Printing Systems Gmbh Databus and method for the communication of two assemblies by means of such a databus

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