WO1993014581A1 - An audio switching system - Google Patents

Abstract

An analogue time division multiplexing (TDM) switching system is used to emulate a matrix switch and provide high quality audio switching. The TDM switching system comprises multiple multiplexers (30) each having a user operable computer associated therewith. Audio signals from several sources are fed to the multiplexer inputs together with control data from the computer, and these signals are multiplexed onto a coaxial cable (39) together with a synchronising signal. The coaxial cables (39) from the multiplexers are fed to multiple demultiplexers (50) via equalising circuits (60). The demultiplexers (50) are controlled by control demultiplexers (80) which control the demultiplexers (50) in accordance with the control data in the multiplexed signals. The control demultiplexers (80) are also connected to the multiplexer computers via a serial data link. Several techniques, including two-stage sampling switches, are used to reduce crosstalk. The switching system uses distributed software control, enabling a user to switch a demultiplexer output to any selected input of any selected multiplexer. The switching system has particular application in radio broadcasting studios to provide high quality switching of a selected one of a range of audio inputs to a selected output.

Description

"AN AUDIO SWITCHING SYSTEM"

THIS INVENTION relates to a signal switching system. In particular, the invention is directed to a very high quality, computer-controlled, audio switching

5 system using analogue time division multiplexing (TDM).

* In the preferred embodiment, the TDM audio switching *^ system is used in the studio of a broadcasting station, to emulate a matrix switch.

The disclosure of Australian patent application 10 no. PL0333 is incorporated herein by reference.

BACKGROUND ART There has been a large increase in the diversity of audio sources used in radio broadcasting over the last decade or so. As well as the traditional 15 turntables, tape cartridges and tape recorders, studios are now equipped with CD players, DAT recorders, multiple satellite feeds, digital editing and storage devices, etc. This has resulted in a need for programmable fader inputs on both on-air and production consoles in order to 20 cope with this wide range of sources.

Further, in some areas, there is a need to be able to produce two or more separate programs from one studio complex. To do this efficiently requires the ability to conveniently switch the studios to the 25 transmitters, and to be able to share equipment such as time delay units, telephone interfaces and possibly automation systems.

These considerations gave rise to the requirement for a switching system that had as its inputs

30 all of the signal sources available within the radio station, and which could be capable of switching any one

* of its outputs to any one of these inputs. } ' The traditional approach to audio switching has

^" -* been to build a matrix of crosspoint switches which can

35 then switch any input to any output. If there are M inputs and N outputs, then MxN crosspoint switches are required. However, adding one more input requires another N switches, while adding one more output requires M more switches. Thus, the larger the switch the more expensive it is to expand its size.

One solution to this problem is to break the matrix down into smaller sub-matrices which are interconnected by trunks. With this approach however, the number of outputs that can be used at any one time is limited by the number of trunks. In a radio station it is quite conceivable that all outputs may be required to be active at once, so this approach is not feasible.

It is an object of this invention to provide an improved switching system which overcomes the abovedescribed disadvantage of matrix switches.

SUMMARY OF THE INVENTION In one broad form, the present invention provides apparatus for switching a selected one of a plurality of input signals to a selected one of a plurality of outputs, at least some of the input signals being audio signals, the apparatus comprising a plurality of multiplexers, each having plural inputs adapted to receive respective ones of the input signals and providing an analogue time multiplexed signal thereof, a plurality of demultiplexers, each having inputs connected to the multiplexed signals from the multiplexers and providing a respective one of the plurality of outputs, whereby in use, each demultiplexer is selectively controllable to provide as its output a selected one of the input signals of a selected multiplexer.

According to this invention therefore, a matrix switch is emulated and synthesised by using time division multiplexing ( DM). Each input to a multiplexer is sampled sequentially, so that the multiplexed output from the multiplexer is divided in time between each of the inputs. Each multiplexer output is connected to each demultiplexer. The selected demultiplexer samples the multiplexed signal from the selected multiplexer each time the required input signal is present. A hold circuit retains this sample value until the next sample of that signal is available. Provided that each input is sampled at a rate equal to at least twice the bandwidth of the signal, the demultiplexer can faithfully reproduce the selected input signal at its output.

In its simplest form, the TDM system of this invention may consist of a single multiplexer with M inputs and whose output is connected by cable to N demultiplexers. Such a system requires M switches in the input multiplexer and one switch in each of the N demultiplexers, so the total number of switches is only M+N. Furthermore, adding another input or output requires the addition of just one more switch regardless of the existing size of the switching system.

Due to practical limitations such as the switching speed of the electronic switches used, the number of input signals that can be multiplexed onto a single cable is not infinite. In the preferred embodiment, a hybrid of a matrix switch and a time division multiplexed switch is used. Instead of having just one multiplexer, up to 16 can be used, and each demultiplexer has a selector switch on its input to select which of these multiplexers to look for the desired signal on.

In the embodiment described herein, each multiplexer has 32 timeslots. Of these one^' is used to synchronise the demultiplexers while another is used for control data. Two further timeslots are reserved for special applications, leaving a total of 28 audio channels. Thus, with the full complement of 16 multiplexers the system is capable of handling 448 input signals.

The number of demultiplexers is in principle unlimited, since the demultiplexers are bridging across the multiplexer outputs. In practice however, there is an addressing limit of 1536 demultiplexers, which is more than enough to meet any conceivable application. (To implement a switching system of this size as a matrix switch would require 688,128 crosspoint switches).

Typically, the switching apparatus is software controlled. Each multiplexer may have its own associated computer for "local" control. One or more computers can also be provided for "global" control. A control demultiplexer controls the operation of the demultiplexers in accordance with control data included in the multiplexed output signal from the multiplexers. The control demultiplexer may be connected to the multiplexer computer(s) for return control and alarm signals.

In a preferred embodiment, the switching apparatus is used for high quality switching of audio signals in a broadcasting environment.

The multiplexers sample the audio inputs and transmit them sequentially over a coaxial cable. Each multiplexer has 28 general purpose audio inputs, a data input, a talkback input, and one other input reserved for future expansion. Inputs may be used singly as mono signals or paired for stereo signals. Demultiplexers are grouped into boxes, which are further grouped into racks. A demultiplexer extracts a pair of signals from the selected multiplexer, and produces either a stereo output or a mono output consisting of left input only, right input only or the sum of left and right inputs.

Hitherto, time division multiplexing was found to be unsatisfactory for high quality switching of audio signals due to unacceptable levels of crosstalk between the signals. However, the switching apparatus of this application uses several techniques to reduce crosstalk to a negligible level. Such techniques include the use of (i) two-stage selector switches in the multiplexers and demultiplexers, (ii) equaliser circuits at the end of multiplexer output cables, (iii) output impedances on the multiplexers and equaliser circuits which match the characteristic impedances of the respective transmission lines, (iv) synchronising the demultiplexers to a master clock, and (v) reverse orientation of switches in the two-stage switches to cancel out second order nonlinearities.

The multiplexers and demultiplexers are organised by the software to form a logical switching system. This system consists of up to 16 zones, each of which may contain up to 32 input signals or "sources". The outputs of the logical switcher are referred to as "channels". Each channel may be switched to any source (except in certain special cases to be described later).

All sources are global, in the sense that they are accessible from any channel. Channels may be either global or local. Global channels can be controlled from any zone, whereas local channels can only be controlled from one zone. Sources and channels can be mono or stereo. In addition stereo local channels can be forced under user control to produce a mono output.

In order that the invention may be more fully understood and put into practice, an embodiment thereof will now be described by way of example only, with reference to the accompanying drawings. Further inventive features of the switching apparatus will be evident from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS ' Fig. 1 is a schematic diagram of an audio switching system of one embodiment of this invention;

Fig. 2 is a circuit diagram of a resistive termination circuit of Fig. 1;

Fig. 3 is a schematic diagram of a multiplexer of Fig. 1;

Fig. 4 illustrates time waveforms for Fig. 3, ; Fig. 5 is a circuit diagram of the multiplexer; Figs. 6 to 7 are circuit diagrams of an equaliser circuit of Fig. 1;

Figs. 8 to 11 are circuit diagrams of the demultiplexer of Fig. 1; Fig. 12 illustrates timing waveforms for the demultiplexer;

Figs. 13 to 18 are circuit diagrams of the control demultiplexer of Fig. 1;

Fig. 19 illustrates data formats for the control demultiplexer;

Fig. 20 illustrates timing waveforms for the control demultiplexer; and

Fig. 21 is a schematic diagram of the shift register circuit of the control demultiplexer. DESCRIPTION OF PREFERRED EMBODIMENT

SYSTEM ARCHITECTURE

The layout of the switching circuit (or "switcher") of the preferred embodiment of this invention is illustrated schematically in Fig. 1. (For simplicity, only one multiplexer and one demultiplexer (and associated components) are shown). In each "zone", twenty-eight balanced audio inputs 10 are fed to a multiplexer 30 via respective resistive termination circuits 20. Resistive Termination Card

The resistive termination circuits for each zone are mounted on a resistive termination board or card which .is the audio input for the switching system. The card accepts 28 balanced inputs which are buffered and converted to unbalanced form for connection to the multiplexer 30, and optionally terminated in 600 ohms. DIP switches may be used to configure each input 10 as terminating or bridging.

A resistive termination circuit 20 is shown in more detail in Fig. 2. Each resistive termination circuit 20 consists of a differential amplifier 22 with a gain of 0.5. The gain-setting resistors Rl, R2 are preferably specified to a tolerance of 0.1% in order to maximise the common mode rejection. A 600 ohm termination resistor R3 may be switched across each input 10 by DIP switch 21 if required. Otherwise, the input of each circuit 20 is bridging with an input resistance of 40k ohm. The ordering of the output connections matches the permutated inputs of the multiplexer, so that the inputs to the resistive termination card are in strict timeslot order. Multiplexer

The twenty-eight unbalanced outputs 11 from the resistive termination board are fed to a multiplexer 30. Each multiplexer 30 takes up to thirty-one unbalanced inputs, samples them each at a rate of 62.5 kHz and time division multiplexes them along with a sync pulse onto a coaxial cable 39. A simplified diagram of the multiplexer is shown in Fig. 3, and a more detailed circuit diagram is shown in Fig. 5.

The input signals 11 each pass through a respective low pass filter 31 which attenuates any high frequency components that could cause aliasing or interference and also provides a small amount of pre- emphasis to compensate for the high frequency rolloff due to the sample and hold process in the demultiplexing gate.

The output from each of the filters 31 is then attenuated by 6dB. The attenuator 32 serves two purposes. First, it ensures that the clipping level is set by the filter amplifiers 31 so that following CMOS switches are never overdriven. Secondly, it limits the peak current drawn from the filter amplifiers 31 in charging the CMOS switch capacitances when the switches operate.

The outputs of the filters 31 are organised into four groups of eight. Within each group a CMOS switch 33 sequentially selects one of the eight signals.

The output of each CMOS switch 33 is buffered by a unity gain amplifier 34, and a CMOS switch 35 then selects one of the four signals. The two-stage multiplexing switch reduces crosstalk.

Each sample produced by the switches 33 is 2μs long, and is sampled by the switch 35 during the third quarter of this interval. This allows lμs for the output of the switches 33 to stabilise, and is preferable because of the relatively high capacitance of the switches 33 (35 pF plus strays) and the high source impedance (500 ohms) driving them. To achieve this, the switching of the switches 33 is staggered to coincide with the sampling of the switches 35, and this is achieved by shift registers. Each shift register 41 delays the address bits for CMOS switches 33 by 0.5 μs, and is configured so that the address bits for each switch 33 change 0.5 μs after the switch 35 has sampled it.

The timing waveforms are shown in Fig. 4. In each cycle of the sampling by switch 35, U12 (Fig. 5) is the first switch 33 to be sampled. However, it belongs to group 4. To compensate, the ordering of the inputs on U12 switch 33 is shifted around by one position compared to the .other switches 33. Thus, the sync pulse is actually connected to its X0 input, with audio input 25 going to XI, etc.

The output of the switch 35 is buffered by buffer circuit 36 containing transistors Ql, Q2, Q3 and Q4. This is essentially a high current version of the buffers 34, and operates in class A to ensure low distortion. The output signal passes through a 47 ohm resistor 37 to set the source impedance of the multiplexer to about 50 ohms. This is to suppress multiple reflections on the coaxial cable which could otherwise lead to crosstalk. This also attenuates the signal by 6 dB.

A voltage controlled crystal oscillator 42 (Fig. 5) can be tuned over a range of approximately +/- 100 Hz from its nominal centre frequency of 4 MHz. This allows the multiplexer 30 to be synchronised to the system clock. The oscillator output is divided down to 62.5 kHz by U21 and U20 which are carry-look-ahead binary 5 counters. The outputs of the counters provide the addressing for the CMOS switches 33, 35 and the 62.5 kHz ^ output is also made available on pin c3 of the card connector as a data clock.

The 32nd timeslot is used as a sync pulse, and 10 this is set by resistors R133 and R134. The correct level for the sync pulse is -4 V at the output of the multiplexer when it is terminated in 50 ohms.

The capacitors are not fitted to the filters for time slots 29, 30 and 31, as these are reserved for 15 non-audio use. In particular, slot 31 is used for demultiplexer control data which is synchronised to the multiplexer sampling rate. Pulldown resistors are fitted in place of C21, C29 and C37 to prevent these inputs from floating. The data applied to input 31 may itself be a 20 multiplexed signal of several data lines.

The multiplexer .output 38 goes into a 50 ohm coaxial cable 39. In this embodiment, the outputs of sixteen multiplexers are fed by respective cables to centralised demultiplexer racks which contain

25 demultiplexers, with twenty-four demultiplexers in each six-unit high card frame. The sixteen multiplexers 30 are self-contained modules which may be located up to 200 metres from the demultiplexer racks. Because of the high frequency rolloff that occurs in the coaxial cables used

30 to feed the signals from the multiplexers 30 to the racks, the cables are equalised to minimise crosstalk due to the samples smearing into each other. Thus each of the incoming multiplexed signals 38 is passed through an

₃ equaliser board 60 before being applied to the

35 demultiplexers 50. An equaliser card 60 is shown in more detail in Figs. 6 to 8.

Dual Equaliser In coaxial cable, the losses increase in proportion to the square root of frequency. It can be shown that in a time division multiplexed system this will result in crosstalk that will decay at a rate proportional to the time difference raised to the power of 1.5. Since coaxial cable losses increase exponentially with cable length, it follows that crosstalk is similarly related to cable length.

The purpose of the equaliser 60 is to correct for these cable losses, so as to minimise this source of crosstalk. This is achieved by introducing a series of three pole-zero pairs into the frequency response, which are selected to closely match the amplitude response of the coaxial cable. Since a coaxial cable can be modelled as an ideal time delay plus a minimal phase network, it follows that by correcting the amplitude response the phase response will also be correct. Thus additional phase compensation is not required.

As shown in Fig. 6, the equaliser card contains dual equaliser circuits 60A, (60B). One equaliser circuit 60A is shown in more detail in Fig. 7, the other (60B) being substantially identical. Each equaliser circuit 60A, (60B) has a differential input whose gain is set by the ratio of the collector resistor Rll and emitter coupling impedance made up of trimpot VR2 and a compensation network. By varying VR2, the spacing between the poles and zeros may be varied, thus controlling the amount of correction introduced.

Transistor Ql is an inverting amplifier whose main task is to compensate for the DC offset introduced by the differential amplifier. The DC offset may be fine trimmed by trimpot VR1. Resistor R20 controls the overall gain without affecting the DC offset.

The output of each equaliser circuit is buffered by U4 which is a unity gain amplifier. As the ribbon cable is unterminated, overshoot may otherwise occur. However, a 120 ohm resistor R17 is connected in series with the output to match the characteristic impedance of the vertical ribbon cable in the rack and prevent overshoot on the ribbon cable, thereby reducing crosstalk. Transistor Q4 is an active noise filter to remove regulator noise from the negative supply rail. This is used since the differential amplifier has poor immunity to noise on the negative supply (but its immunity on the positive supply is much better). The equaliser card 60 also contains a phase comparator 61 for locking the multiplexer 30 to the master clock, as well as the master clock oscillator itself.- Tristate inverting buffer U2 is used as the 4MHz oscillator, and is only enabled on one equaliser card. The oscillator output is divided down to 62.5 kHz by Ul and is fed via another buffer in U2 to the other cards in the rack. U2 is enabled by means of a jumper on the equaliser backplane.

The sync pulses from the multiplexer 30 are detected by U8A and compared in phase with the clock by

U7. The error voltage is buffered by U9A and returned to the multiplexer VCXO, while comparator U8B drives the lock indicator LED and alarm output.

The DC offset should be adjusted with a 50 ohm termination connected to the input, but no multiplexer, and VR1 is adjusted for zero voltage on the equaliser outputs.

The outputs from the equalisers 60 are distributed down each demultiplexer rack in ribbon cable and are picked up by a buffer board 70 in each demultiplexer card frame. Buffer

The buffer card 70 consists of sixteen unity gain amplifiers used to isolate the vertical ribbon from the demultiplexers 50 in each card frame.

The buffer outputs are required to drive a short unterminated transmission line having a variable number of capacitive loads shunted across it. (This depends on how many demultiplexers are switched to a particular multiplexer). A 12ohm output resistor on each amplifier is used to suppress multiple reflections on the transmission line while still providing a reasonably low source impedance to cope with this variable capacitive load.

Because the transmission line is so short the large mismatch between this source impedance and the characteristic impedance of the line can be tolerated, with the reflections dying away in a very short time compared to the width of the samples.

Input resistors (1 kohm) are used principally for stability, but also serve to prevent excessive loading of the equaliser outputs when power is removed from a card frame. (However, the buffer card should be removed if it is to be unpowered for any length of time).

The buffer outputs are distributed along the card frame backplane to demultiplexers 50 which are arranged in pairs on demultiplexer boards, shown in more detail in Figs. 8 to 11. Demultiplexer

The demultiplexers 50 are each of double circuit configuration and provide two stereo outputs from the switcher. Each demultiplexer 50 selects one of sixteen multiplexed inputs from the multiplexers 30, and extracts the audio information from an adjacent pair of timeslots on that input. This pair of signals is then matrixed to produce a stereo, left only, right only or left plus right mono signal.

As shown in Fig. 8, the demultiplexer is controlled by a 12 bit parallel data input (from a control demultiplexer) which is latched by a board select signal. Each demultiplexer circuit consists of four sections, namely an "oak" switch (Fig. 9), a control section (Fig. 10), a gate (Fig. 11) and a filter.

The oak switch is a static 16 way CMOS switch used to select the required multiplexed input. (It performs the same function as a mechanical rotary selector switch).

The control section contains the logic circuitry to control the operation of the oak switch and gate. It includes data latches, a phase locked loop and a sampling pulse generator.

The gate is a pair of CMOS switches which demultiplex the two audio samples required to make up the stereo pair. Each switch is closed at the centre of the timeslot which it is required to sample, and the sampled voltage is stored on a capacitor. Another static CMOS switch - is used to select the required stereo or mono mode. The filter converts the samples generated by the gate into a continuous audio signal by removing the high frequency sampling products. The filtered audio is finally converted into a balanced output capable of driving a 600 ohm load. In the following circuit description and Figs.

9 to 11, component designations given refer to demultiplexer circuit A on each board. Demultiplexer circuit B on that board is electrically identical, except that the demultiplexer select input OP9 is inverted for demultiplexer B.

(i) Oak Switch

As shown in Fig. 9, the 16 way input switch consists of two sections each made up of four-way CMOS switches. The sixteen inputs are arranged in four groups of four, and one signal is selected from each group by U4 and U5. These four signals are buffered by U7, U8, U10 and U13, and another four-way switch U16 then selects one of these four signals. The output of switch U16 is buffered by U18. The input switch is divided in this manner to minimise the input capacitance of the demultiplexer and hence reduce crosstalk. If a single 16 way switch were to be used, the capacitance seen at the selected input would be the total capacitance of all 16 switches, and this would present an excessive load on the buffer board if all demultiplexers in the card frame were to be set to the same multiplexed signal. With the layered switch however, the capacitance seen at the selected input is only made up from four switches plus the input capacitance of the buffer.

Comparator U24B is used to extract the sync pulse from the selected input. Diode DI, resistor R27 and capacitor C33 form a peak detector which produces a

■ DC voltage at the inverting input of the comparator one diode drop (approximately 0.6V) higher than the most negative peak of the input waveform. The input waveform itself is applied to the non-inverting input, so that the comparator output is low whenever the input waveform is more negative than the peak detector voltage. Because the sync pulse level is -4V and the peak audio level is

3V, this only occurs during the sync pulse. (ii) Control Section

As shown in Fig. 10, the parallel input data is latched by U6 and U56 on the falling edge of the TOGGLE input when the demultiplexer select bit (0P9) is low (for the A demultiplexer). Inputs OP0...OP3 are latched to produce the oak switch control bits OAKA0..0AKA3.

Inputs OP5-.OP8 are used to select the pair of timeslots to be sampled- Inputs 0P4, OP10 and 0P11 are the mode control bits-

Transistor Ql is a voltage controlled crystal oscillator. The crystal frequency is adjusted by varicap diode D3, and an increase in control voltage results in an increase in frequency. The tuning range is approximately 300 Hz either side of 4 MHz.

The oscillator output is buffered by U52 and fed to U51 which is configured as a two bit ring counter.

This divides the crystal frequency down to 1 MHz, which is used to clock the four bit counter U58. Data comparator U57 compares the four output bits of U58 with the timeslot select bits latched from 0P5..0P8, and the A=B output of the comparator (pin 6) goes high when all four bits match. Flip flops U43A and U43B are used to generate the sampling gate pulses. The flip flops are clocked by the 4 MHz oscillator output via inverter U52D, but are normally held in their reset state until the output of the comparator goes high. Flip flop U43A is activated for 250ns during the first timeslot, while U43B is activated during the second timeslot. Transistors Q2 and Q3 perform a logic level translation to produce a pulse from -5.V to +5V. The detailed operation of this pulse generator is illustrated by the timing waveforms in Fig. 12.

The A=B input of the data comparator (pin3) disables the comparator when it is low. This prevents the sampling pulses from being generated, and is used to turn the demultiplexer off. The status of this on/off control (M0DEA2 derived from bit 0P11) is indicated by LED1, which lights when the demultiplexer is on.

The QD output of counter U58, which is a 62.5 kHz square wave, is fed to phase comparator U35 along with the output of the sync separator. The p2 output of U35 (pin 13) is normally in a high impedance state, but pulses low if the counter output lags behind the sync pulses, or pulses high if the counter leads the sync pulses. These pulses are integrated by U34 to produce a DC control voltage for the crystal oscillator.' Since the integrator is inverting, if the counter starts to get ahead of the sync pulses, the phase comparator will drive the output of the integrator lower, causing the oscillator frequency to fall. This brings the counter output back into lock with the sync pulses. The PP output (pin 1) of the phase comparator

U35 is normally high, but pulses low whenever there is a phase error. These pulses are smoothed by R36 and C35 to produce a lock indicator voltage at the inverting input of comparator U24A. This lights LED2 if the voltage is greater than about 4V, indicating that the oscillator is locked to the sync pulse. Pin 3 of latch U56 is fed from the glitch detect input bit GLIN, and the corresponding latch output GLOUTA is NOR'ed with GLOUTB by U50D (Fig. 8) to produce the glitch alarm output. Diode D5 makes this effectively an "open collector" output, since the glitch alarm output is commoned to all demultiplexers in the card frame.

The phase locked loop lock indicators are OR-ed together by U60C and U60D (Fig. 8) to produce a lock alarm output for the board. This signal is used by the control demultiplexer to generator an alarm message if either PLL becomes unlocked.

(iii) Gate

Referring now to Fig 11, CMOS switch U19 is used to sample the output of the oak switch to produce the required stereo signal. U19A and U19C select the left channel (this is the first timeslot of the pair addressed by OP5..0P8), while U19B and U19D select the right channel. Two switches are used in series for each gate to minimise the leakage capacitance across the switch, which would lead to crosstalk problems. As shown in Fig. 11, the switches of each gate (U19A, U19C),

(U19B, U19D) are of reverse orientation to cancel out second order nonlinearities. Resistors R4 and R5 limit the current drawn through the switch at turn-on, and this minimises distortion. The sampled voltage, is stored by capacitors C30 and C29 and buffered by U23 and U22.

CMOS switch U30 is used to select full stereo or one of the mono modes. When mode control bits MODEA0 and MODEAl are both high, the left and right inputs are passed directly to the X and Y outputs of U30 respectively. When the control bits are both low, the outputs are both connected to the junction of R107 and R108 which produces a left plus right mono signal. When only MODEAO is high, the left channel is passed to both outputs, while if only MODEAl is high the right channel is passed to both outputs. Control bit M0DEA3 comes from the PLL lock indicator U24A (Fig. 10), and is used to inhibit the audio output if the phase locked loop is unlocked.

The outputs of U30 are AC coupled to buffers U28B and U28C. The corner frequency is set by C42/R34 or C41/R33 for each channel respectively, and is about 3 Hz. (iv) Filter

A 5th order Butterworth low pass filter is preferably used to remove the high frequency sampling products produced by the demultiplexing gate. The filter corner frequency (-3dB point) is about 26 kHz. The output of the filter is buffered by a buffer which suitably has a gain of 2. The left and right outputs are made available as unbalanced outputs (LUA and RUA), and these are converted to balanced signals (L+A, L-A, R+A, R-A). Resistors are used to set the balanced output resistance to about 40 ohms.

(v) Power Supplies

Regulators U45 and U44 (Fig. 8) produce +9V and -9V rails from the raw 13V inputs respectively. U46 produces a +5V rail, while U59 produces a -5V rail. The audio output buffers operate directly from the 13V inputs in order to achieve maximum output swing. The inherent power supply noise rejection of these amplifiers is sufficient to prevent power supply noise from reaching the outputs. A double demultiplexer board according to the illustrated embodiment typically consumes about 280 mA from the positive supply and 160mA from the negative supply.

Control Demultiplexer The data in the 31st timeslot of each multiplexed signal is sampled by a control demultiplexer 80 in each demultiplexer card frame (Fig. 1). The control demultiplexer 80 circuit is shown in detail in Figs. 13 to 18.

The control demultiplexer 80 is required to extract data in serial form from the multiplexed outputs of each multiplexer 30, and deliver it in parallel form to the appropriate demultiplexer. It also monitors the demultiplexers 50 for latch glitches or PLL lock failure, and sends appropriate alarm messages to the studio processors 85, i.e. computers associated with the multiplexers 30.

Each control demultiplexer 80 can control one card frame containing up to 12 double demultiplexers 50, and simultaneously monitors up to 16 multiplexed inputs for data addressed to it. The control demultiplexer 80 of the illustrated embodiment uses five erasable programmable logic devices (EPLD's). Four 5C060's are used as input latches, while a single 5C180 contains most of the digital logic which controls the operation of the control demultiplexer. The 5C180 is internally divided into four quadrants, and for convenience these are shown separately on the circuit diagram of Figs. 16, 18 as U47A, U47B, U47C and U47D. (i) Data Formats

Two separate data paths are used to control and monitor the operation of the switcher. Commands from the studio processors 85 to the demultiplexers 50 are sent via the dedicated data channel on the multiplexers 30, using an asynchronous 32 bit word. Acknowledgments and alarms from the control demultiplexers 80 back to the studio processors 85, as well as direct communications between studio processors 85, use an RS485 twisted pair data bus 86 (as shown in Fig. 1). Synchronous data link control (SDLC) is used with non-return-to-zero-inverted (NRZI) signalling for packet transfers on this bus. (i)(a) Demultiplexer Control Data

Data from the studio processors 85 to the control demultiplexer 80 is used for either demultiplexer control or updating the alarm mask register. The preferred formats for these two types of frame are shown in Fig. 19.

In both cases, the first bit of byte 1 is the start bit, and is always high. (The idle state for the data channel is low). This is followed by 6 box address bits, which identify one of 64 control demultiplexers. The eighth bit identifies the type of frame.

In a demultiplexer control frame, the first four bits of byte 2 identify which of 12 demultiplexer cards is being addressed. The second four bits identify the zone to which the demultiplexer is to be set. Byte 3 selects- the slot to which the addressed demultiplexer is to be set. Also included in byte 3 is the "D" bit that selects which of the two demultiplexers on the card is being addressed, and the three mode bits that control stereo/mono/off switching. Byte 4 is reserved for future use.

In an alarm mask frame, the first four bits of byte 2 contain the mask bits for the group of four demultiplexers selected by. bits 5 and 6. Bytes 3 and 4 unused.

(i)(b) Return Data Bus

Data on this bus 86 is sent as packets using the SDLC protocol. Each packet consists of an opening flag, which has a bit pattern 01111110, a 1 byte destination address field, a 1 byte source address field, 3 bytes of data, a 2 byte cyclic redundancy check (CRC) field, and a closing flag, as shown below:

The receiver uses the flag bit pattern to identify the start and end of the packet. A special destination address of 11111111 is reserved as a global address, and packets sent with this address will be received by all processors. This is used by the control demultiplexer for alarm messages. NRZI signalling is used for the physical data transmission on this bus. Rather than using different voltage levels for l's and 0's, NRZI uses a transition to indicate a 0, and the absence of a transition to indicate a 1. This is generated in the control demultiplexer by using a toggle flip-flop within the EPLD.

NRZI has two main advantages in this application. Firstly, since it relies only on transitions, it does not matter if the polarity of the electrical signal becomes reversed. This is particularly advantageous for use with the RS485 bus, since it is a balanced signal sent on a twisted pair cable, and it is very easy for the pairs to become reversed. With NRZI this is of no consequence. The second advantage of NRZI is in clock extraction. Since SDLC is a synchronous protocol, the receiver needs to be able to synchronise its internal clock with the transmitted data. Rather than send a separate clock signal, it is possible to extract this synchronisation from the data itself, provided transitions occur reasonably frequently. When NRZI is used in conjunction with SDLC, this is guaranteed, since if zeros are being sent, there is a transition with every bit, and "bit stuffing" ensures that at most, six l's can appear in a row (this being a flag - at other times the maximum number of consecutive l's is five). A digital phase locked loop circuit is incorporated into the SCC's used in the processors, which uses the transitions to lock the receiver clock to the incoming data. ' The use of this packet format for the return data ensures that data is received correctly, even if two packets are sent simultaneously. In such an event, a CRC error will occur because of the collision, and the received packet will be rejected. By having each retry time set slightly differently, on the next attempt the collision will be avoided and both packets will get through. (ii) Operation

The control demultiplexer 80 is broken up into five logical parts, these being the comparators (Fig. 14) which extract the multiplexed data, the input latches (Fig. 15), which provide temporary buffering for the extracted data, the shift register (Fig. 16), which clocks in the data from all sixteen inputs and converts it into parallel form, the outputs (Fig. 17), which send the parallel data to the demultiplexers, and the transmitter (Fig. 18), which sends acknowledgments and alarms to the studio processors. (ii)(a) Comparators - As shown in. Fig. 14, two comparators are used for each multiplexed input. (For simplicity, the comparator pairs for only some of the inputs are shown, the others being of substantially identical design). The "A" comparator is used to detect the sync pulse on the input signal, and produces a positive pulse on its output. The "B" comparator extracts the actual data from the time slot preceding the sync pulse, and this delayed by a 390pF capacitor on the comparator output so that the data is valid on the rising edge of the sync output. The logical sense of the data output is inverted. (ii)(b) Input Latches As illustrated in Fig. 15, four 5C060 EPLD's are used for the input latches. Each EPLD is programmed to contain eight latches, four of which hold the data seen on the rising edge of the sync pulse, with the remaining four latches being used to signal that a sync pulse has occurred. The latter latches are cleared by the data ready clear signal on input 4, which is directed to the appropriate latch by the chip select line on input 1 and the latch select inputs 2 and 3.

The outputs of the data and data ready latches from each EPLD are multiplexed by CMOS switches U21, U22, U26 and U27, which are in turn selected by the 2-line to 4-line decoder U29. This method of data extraction requires that the control demultiplexer clock run slightly faster than the multiplexer, otherwise data bits will be missed. This is ensured by using a crystal oscillator U40E which runs at a frequency of 4.194 MHz, compared with the 4 MHz used in the multiplexers.

(ii)(c) Shift Register

As shown in Fig. 16, the serial data from the input latches is converted into parallel form using a 32 bit shift register made up of U31, U32, U33 and U34, and a 32 bit by 16 location memory made up of U35, U36, U37, U38. The shift register and memory are under the control of a 5C180 EPLD (U47).

The 4.194 MHz signal from the oscillator U40E is divided by 4 using two EPLD registers configured as a ring counter. (These appear on pins 10 and 11). These are used to generate a counter enable signal on pin 9 of the EPLD, which enables counter U39 once each microsecond. This four bit counter is used to select which of the 16 inputs is being sampled. Since the data rate is 62.5kbit/s, data can be received on all 16 inputs simultaneously.

Referring to the timing diagram of Fig. 20, within each lμs sampling period there are four phases, identified by the state of the EPLD registers on pins 10 and 11. During the first phase (phase 0), the 32 bit memory word addressed by U39 is loaded into the shift register. In phase 1, the data ready input is examined, and if high, the data ready clear line is activated and at the end of this phase the data signal from the input latches is shifted into the shift register. In phase 2, the shifted data is written back into the memory. The shift register and memory are inactive during phase 3.

The data from the studio processors takes the form of a 32 bit frame, as shown in Fig. 19. The first bit of this frame is the start bit, and is always high.

When this bit reaches the end of the shift register (output H of U34) the next six bits (which form the address field of the data frame) are compared with the box address by address comparators U45 and U46, and feed an address match signal to pin 21 of the EPLD. If output H of U34 (DAO), which connects to pin

14 of the EPLD, is high during phase 0 (indicating receipt of a start bit on the previous shift), the data shifting is inhibited. If the address match line is low, the shift register is cleared using the CT2 output from pin 4 of the EPLD. Otherwise, provided monostable U44B is not set, the tx send line (EPLD pin 59) goes high at the beginning of phase 1, and the send enable line (EPLD .pin 57) goes high at the end of phase 3. If U44B is set, nothing happens until it is cleared. During the period between tx send and send enable going high, the eighth data bit (DA7) is examined, via pin 15 of the EPLD, to determine whether the frame contains demultiplexer data or an alarm mask. In the case of the former, the output enable line (EPLD pin 29) goes low twice, firstly at the end of phase 1 with the glitch bit low, and then again at the end of phase 3 with the glitch bit set high (see (ii)(f) below). In the case of an alarm mask frame, the write mask line (EPLD pin 30) goes low during phase 1. (ii)(d) Outputs

The output circuits are shown in Fig. 17. When the tx send line goes high, the parallel data from the shift register is loaded into the output latches U48, U49 and ^"U50. When output enable goes low, the four bit demultiplexer address is decoded by U51 and U52 to pull low one of twelve demultiplexer toggle lines. Data is latched by the demultiplexers on the falling edge of the toggle line.

PLL lock failure alarm signals from the demultiplexers are multiplexed in groups of four by U53 and U54. Each group of four is compared in turn with the four bit mask word stored in the four word register U56. A discrepancy between the alarm status of any demultiplexer and its corresponding mask bit will cause the alarm signal to the EPLD to go high. Pull-up resistors are included so as to trigger an alarm if a demultiplexer board is removed.

(ii)(e) Transmitter

The transmitter circuit is shown in Fig. 18.

The purpose of the transmitter section is to send acknowledgments and alarms to the studio processors. SDLC packet format with NRZI signalling is used, for compatibility with the SCC fitted to the processors, as described above. All control demultiplexers and processors are connected together using an RS485 bus, and

U57 provides the interface to this bus. Any data transfer taking place on the bus will trigger monostables U44A and U44B. U44A provides a 500ms re- ry time for alarms, while U44B provides a 0.2 ms hold-off for acknowledgments. This is to prevent a control demultiplexer from commencing to transmit if the bus is busy. The outputs of U44A and U44B are fed to

EPLD pins 55 and 47 respectively.

When the control demultiplexer has a message to send (either an acknowledgment or an alarm) and the relevant busy signal is low, the tx send output from the EPLD (pin 59) becomes high, enabling the RS485 line driver and loading the current count on U39 into register U42. Address comparator U41 produces a high output whenever tx send is high and the count on U39 equals the number stored in U42. This signal (tx address) is used by the EPLD to generate a tx clock signal (pin 12) which is used to clock the transmitter shift registers and the internal counters set up in the EPLD. This results in a transmit data rate of about 65.5 kilobits per second.

The EPLD also generates a shift register load signal on pin 27, which loads U23 (the flag shift register) with the flag character, U58 (the destination address shift register) with the current count on U39 (which is the address of the studio processor being acknowledged), U28 (the source address shift register) with the demultiplexer box address, and U30 (the alarm shift register) with the alarm status. Sixteen registers within the EPLD are used for CRC generation, and these are also preset to 1 at this time.

For the first eight cycles of tx clock, shifting is inhibited and eight 0 bits are sent. Since the NRZI equivalent of a 0 is a transition, this results in eight transitions which ensure that the receivers have properly locked on to the clock rate by the time the data transmission begins.

- Referring also to fig. 21, in the case of an acknowledgment, serial data flows into the flag shift register, via pins 43 and 50 of the EPLD, from the destination and source address shift registers, which in turn are fed data, via pins 44 and 48 of the EPLD, from pin 17 of U33 in the receiver shift register. In this way, the last 24 bits of the received data are sent back to the originator, so that the studio processor can check for correctness.

For an alarm packet, the process is similar, except that serial data from the alarm shift register is fed into the address registers via EPLD pin 49. Pin 45 of the EPLD sets the 7th bit in the source address shift register to indicate that the packet is an alarm. Furthermore, during the time that the first address byte is being sent, the EPLD forces pin 43 high to create a global (hex FF) address, so that the alarm packet is received by all processors.

All EPLD registers are cleared whenever power is first applied to the device, and this feature is used on -pin 13 of the EPLD as a power fail indicator. When this pin is low, an alarm frame is sent, and it is set high when an alarm mask frame is received. The status of this pin is reflected as a bit in the transmitted alarm packet, via pin 2 of U30. This power fail indicator is also used within the EPLD to clear the receiver shift register while the alarm frame is being sent. This is to remove any random data that may be contained in the shift register and memory following the application of power, which may otherwise have been misinterpreted as received data.

Once the four data bytes have been shifted through to the flag shift register, the EPLD switches pin

43 to its internal CRC register, in order to send the two checksum bytes. Finally, the shift register load signal is pulsed again to reload the flag character into the flag shift register to complete the packet, and tx send is finally taken low when the closing flag has been sent.

The output of the flag shift register drives pin 54 of the EPLD, which is programmed to convert the serial data into NRZI format on pin 68.

Counter U43 is used to perform bit stuffing, by taking the shift inhibit line (EPLD pin 56) high if 5 consecutive l's have been shifted into the flag shift register. The shift inhibit line stops all of the other shift registers (including the EPLD's CRC register and the receive shift register) from shifting, and also forces pin 43 of the EPLD to go low. This inserts a zero into the data stream going into the flag shift register, which in turn resets U43.

(ii)(f) Glitch Detection

Once data is sent to a demultiplexer, it is stored indefinitely in latches within the demultiplexer. Since these latches are only updated when a change is being made, it is conceivable that an error or "glitch" may occur which corrupts this data. To detect such an occurrence, one bit in each demultiplexer's latch is set aside for glitch detection- This bit is driven from the glitch bit output on pin 34 of the EPLD (Fig. 16), via inverter U40C.

When a demultiplexer is being updated, the output enable signal is activated twice, firstly with the glitch line high, and then again (500ns later) with the glitch line set low.

The glitch bit outputs from the demultiplexers are wire-OR-ed back to the glitch input on the control demultiplexer. This serves two purposes. Firstly, the glitch input going low after the first output enable pulse serves as an acknowledgment that the demultiplexer has received the data, and this is sent back to the originating processor as the 8th bit in the source address field of the acknowledgment packet. The second output enable pulse then causes the glitch input to return to its normal high state. The glitch line output from the- control demultiplexer is then returned high.

If a glitch occurs on a demultiplexer toggle input, this high signal will be latched in the demultiplexer's glitch bit, causing the glitch input to the control demultiplexer to go low. This generates an alarm condition which causes an appropriate packet to be sent by the control demultiplexer. The glitch bit in the address field indicates the cause of the alarm.

The glitch input going low during the acknowledge cycle will not generate an alarm, since alarms are suppressed by the EPLD during acknowledgments. The studio processors 85 can determine which demultiplexer caused the glitch alarm by updating each demultiplexer in turn. While the glitch input remains low, the output enable line is only activated once, with the glitch bit output line set low. Thus, when the glitched demultiplexer is reset, the glitch indicator bit in the acknowledgment frame will be high, thereby identifying the glitched demultiplexer. This information can be logged for maintenance purposes. (iii) Data Integrity

The data path from the multiplexers to the control demultiplexer is via the data channel on the multiplexer output. Since the control demultiplexer uses time division to effectively look at all sixteen inputs at once, collisions cannot occur on the incoming data. It is quite permissible for two processors to send data simultaneously, and the time division multiplexing within the control demultiplexer will ensure that no conflict occurs (unless both processors address the same demultiplexer, in which case the last one wins).

The EPLD prevents an acknowledgment or alarm packet from being initiated while it is sending another, and subsequent acknowledgments are automatically queued. The busy signal will prevent a transmission from starting if the return data bus is busy, however because of the finite time delays involved it is possible for two -control demultiplexers to start sending at the same time. In such a case, the packets will corrupt each other, and the SDLC protocol will ensure that the resultant packet is rejected. Thus neither studio processor will receive the acknowledgment, and will retry after a random length of time.

A collision of alarms will result in, no action being taken to clear the alarm, so that alarm will repeat once the busy monostable has timed out. (This acts as a retry timer).

By sending the received data back as part of the acknowledgment packet, the originating processor can check that the data received by the control demultiplexer was correct. The use of the glitch bit ensures that the demultiplexer has received something.

Thus the processor originating a demultiplexer control or alarm mask frame is assured as far as possible that the frame has been correctly received and acted upon. Filter Card

A filter card 90 is provided to remove any high frequency noise that may be present on the audio and data cables that connect to the demultiplexer racks.

Each filter section is a balanced pi network having a cutoff frequency of 500 kHz. The filter ground connections are taken back to the common ground point at the top of the rack.

Broadcasting Applications In a typical radio station environment a multiplexer would be located in each studio, with additional multiplexers for satellite and landline inputs, etc. The signal sources produced within each studio are fed into the studio multiplexer, and are available to any demultiplexer in the system.

The demultiplexers may be used to provide programmable inputs to console faders, tape recorders etc., as well as for distributing signals to the transmitter and other outgoing lines. Time delay units, telephone line interfaces and other signal processing equipment may also be integrated into the system, making these units available to any studio requiring them.

The nature of time-division-multiplexed switching makes this system very flexible in both size and shape. An output may be added by connecting up another one demultiplexer only, and all signals in the system become instantly available to it. Similarly an input may be added by connecting another signal into a multiplexer, or if necessary adding another multiplexer. Again, this added input becomes instantly available to all demultiplexers in the system. SYSTEM CONTROL

In addition to the switching apparatus itself, this invention also provides an improved method of controlling the switching of the audio signals. Much of the switching system's versatility is due to the methods used to control the operation of the switcher.

The method of controlling the switching system is based upon the principle of distributed control. Rather than having one central controller for the whole system, each multiplexer 30 has its own computer 85 connected to it. In the context of a radio station, the multiplexers 30 are located in the studios, and each studio may have its own computer 85 as the studio processor. In one specific embodiment of this invention, the distributed control system consists of IBM AT compatible PC's in each zone.

The demultiplexers 50 are controlled by means of serial data sent via each multiplexer. The control demultiplexer 80 monitors the data channels on all of the multiplexer cables, and can control one card frame containing up to 24 demultiplexers. As described above, the control demultiplexer uses erasable programmable logic devices (EPLD*s) to integrate the complex logic functions required.

A twisted pair serial data bus connects all of the computers and control demultiplexers together. This allows the control demultiplexers to send acknowledgments and alarm messages back to the computers, and allows the computers to communicate with each other. However this data bus is of secondary importance only. The switcher can still operate without it, since the forward data path between the computers and - the demultiplexer is via the multiplexers.

Demultiplexers are logically grouped into those belonging to one particular computer (referred to as "local") and those belonging to the whole system

(referred to as "global"). In the application of the switcher to a radio station for example, local demultiplexers are used to feed signals back into the studios for use as fader and tape recorder inputs, while the global demultiplexers are used for outgoing lines to the transmitter and other stations and for communal devices such as time delay units and telephone interfaces. The distinction between local and global demultiplexers is done entirely in software. The hardware allows any computer to control any demultiplexer.

More specifically, the local demultiplexers may be used to implement programmable console faders, where each fader is fitted with an alphanumeric display which shows the name of the signal that it is currently switched to. A dual concentric rotary switch is preferably used to program the faders, with the inner switch selecting the multiplexer and the outer switch selecting the signal on that multiplexer. A layered menu also appears on the computer's monitor screen to assist in quickly locating the desired signal. The global demultiplexers can be controlled from any computer, and are displayed on each monitor screen. Again, a concentric switch can be used to select the signal to be used.. Global demultiplexers can also be automatically switched at certain times through preprogrammed events. These events may be either one-off or can be programmed to repeat on selected days each week.

As described previously, the demultiplexer control data is transferred to the demultiplexer racks via timeslot 31 on the zone multiplexers at a rate of

62.5 kbit/sec. The 62.5 kHz clock output from the multiplexer is used to synchronise this data to the multiplexer sampling rate. The data is sent as a 32 bit frame. The control demultiplexer boards in the demultiplexer racks extract the demultiplexer control data from each of the zone coaxial cables, and transfer it to the addressed demultiplexer board via a 20 bit parallel data bus on the demultiplexer backplane. PLL failure and glitch alarm signals from the demultiplexers and equalisers are monitored by the control demultiplexers, and are transmitted back to the zone PC's via the RS485 bus. Demultiplexer commands are also acknowledged via this bus. The serial communications requirements of the

PC are handled by an Industrial Computer Source ACB-2

Advanced Communications Board. This board uses an Intel 82530 (equivalent to Zilog Z8530) Serial Communications Controller (SCC) . Port A of the SCC is used to communicate with the RS485 bus, while port B is used to send data to the demultiplexer racks. Within each zone, a Console Interface Board facilitates data transfer to Fader Display Boards, Local Control Board, Monitor Display board, manual event buttons and indicators and miscellaneous buttons and indicators. The Console Interface Board provides the address decoding, output latches and input buffering required to drive the various displays, indicators and switches- used within each zone.

The Console Interface Board connects to the PC via one channel of a Quatech PXB-721 Parallel Expansion

Adapter. This provides 24 I/O bits as well as power supply connections on a 34 conductor ribbon cable. The other 2 channels of the PXB-721 are unused.

In a rack room zone, an Industrial Computer Source DI08 Isolated I/O Interface Board is used for signalling delay units and telephone interface units. This board provides 8 relay outputs and 8^" opto-isolated inputs. The inputs have a switchable low pass filter which should be enabled in this application of the switching system.

The Local Control Board contains a 2 line by 8 character LED display, input ports for the local knobs and buttons and output drivers for the mode indicator LED's. The Fader Display Board holds the alphanumeric

LED readouts, mode indicator LEDs and select buttons for the programmable console faders. A 16 conductor ribbon cable provides the common data, addressing and power supply connections to all boards, while individual select lines for the displays, LEDs and buttons and connect back to the address decoders on the Console Interface Board.

The Monitor Display Board is similar to the Fader Display Board except that an LCD display is used in place of the LED readouts. An additional 7 bit diode isolated input port is provided for connection to a concentric knob and mode select buttons, to allow this board to be used as a remote selector.

Each concentric knob used for menu selection is a 12 position continuously rotating switch, and is encoded with two bits such that when rotating clockwise the sequence is 11, 01, 10. The two least significant bits are used for the inner knob, and the next two bits are the outer knob.

Special software facilities may suitably be provided- for integrating equipment such as audio time delay units and telephone interfaces into the system. Such units receive audio signals from a demultiplexer, and feed their output into a multiplexer input, and can therefore be used anywhere within the system. (The time delay and telephone interface can even be interlocked so that telephone calls cannot be put to air unless the requisite delay is present) .

Configuration and current status information is stored on disk by each computer so that this information can be retrieved in the event of a failure. Since each computer has knowledge of the whole . system, full operation is possible even with only one computer operating. The configuration of the system may be changed on-line, with all computers being informed step by step of alterations, additions and deletions made.

Multiplexer inputs and demultiplexer outputs may be configured in software as mono or stereo. Stereo inputs occupy an adjacent pair of multiplexer timeslots, and stereo and mono inputs may be freely mixed within a multiplexer. The demultiplexers are all inherently stereo, but software switchable audio matrixing on the outputs can produce a mono output consisting of left channel or right channel only or a summation of left and right channels. The software for the system is written in C++, an object-oriented extension of the popular C language. This language allows a close and concise relationship to be established between software "objects" and the physical hardware of the switcher. Layered menus and display screens can be used to allow rapid and intuitive operation of the system by non-technical operators. A more detailed description of the operation software can be found in Australian patent application no. PL0333. The software is structured in three distinct layers. The lowest layer is the hardware layer or physical interface. The hardware layer is responsible -for communications between computers, and from the computers to the control demultiplexers. It is concerned with communicating with the hardware, and deals with coaxial cables, slots, control demultiplexer and demultiplexer addresses, and demultiplexer mode switching. This layer receives commands from the higher layers via specific function calls, and passes operational and alarm messages back via dynamic message queues. It is also invoked via hardware interrupts by data packets received from control demultiplexers and other computers.

Above the physical layer is the logical layer. It deals with zones, sources and channels, and the various sub-species of these- There are also parent classes which group these into tables for use in menus.

The logical layer is invoked by user commands and by information coming off the message queues. At the top is the human interface layer, which is responsible for the screen and LED displays and command entry. This layer interacts directly with the logical layer, so that the user works with zone and source names rather than coax cable and slot numbers. The interface layer also isolates the user from the different types of source and channel, so that all sources appear as signal inputs and all channels as signal outputs.

The foregoing describes only one embodiment of the invention, and modifications which are obvious to those skilled in the art may be made thereto without departing from the scope of the invention. For example, voice-overs may be effected by overlapping input signals or signal from two (or more) multiplexers. The same input signal may be switched to two or more outputs at the same time, or different input signals may be simultaneously switched to respective outputs.

Although the invention has been described with particular reference to its application in a broadcasting studio, the switching system may also be used in language studios or multi-lingual conference facilities in which a number of audio inputs need to be selectively switched to any one of a number of outputs.

Claims

CLAIMS :

1. Apparatus for switching a selected one of a plurality of input audio signals to a selected one of a plurality of outputs, the apparatus comprising a multiplexer having plural inputs adapted to receive respective ones of said input signals and providing an analogue time division multiplexed signal thereof, and a plurality of demultiplexers each connected to the multiplexed signal of the multiplexer, each demultiplexer providing a respective one of said plurality of outputs, whereby in use, each demultiplexer is selectively controllable to provide as ^•an output a selected one of the input signals of the multiplexer.

2. Apparatus for switching a selected one of a plurality of input signals to a selected one of a plurality of outputs, at least some of the input signals being audio signals, the apparatus comprising a plurality of multiplexers, each having plural inputs adapted to receive respective ones of the input signals and providing an analogue time division multiplexed signal thereof, a plurality of demultiplexers, each having inputs connected to the multiplexed signals from the multiplexers and providing a respective one of the plurality of outputs, whereby in use, each demultiplexer is selectively controllable to provide as its output a selected one of the input signals of a selected multiplexer.

3. Switching apparatus as claimed in claim 2, further comprising at least one control demultiplexer circuit for controlling the operation of one or more of the demultiplexers, each control demultiplexer circuit also being connected to the multiplexed signals from the multiplexers.

4. Switching apparatus as claimed in claim 3, wherein one of the input signals to each multiplexer comprises control data, and further wherein the control demultiplexer circuit is responsive to the control data in the multiplexed signal of a selected multiplexer to control the operation of its associated demultiplexers) .

5. Switching apparatus as claimed in claim 4 further comprising user-operable computer means operatively associated with each multiplexer, the computer means providing the control data to its respective multiplexer.

6. Switching apparatus as claimed in claim 5, further- comprising a serial data link between the computer means and the control demultiplexer circuit.

7. Switching apparatus as claimed in claim 5 when used for switching audio signals in a broadcasting station, wherein at least one multiplexer and its associated computer and at least one demultiplexer are located in a studio of the broadcasting station, at least some of the inputs of the multiplexer being connected to audio signal sources in the studio and the output of the demultiplexer being connected to a console fader.

8. Switching apparatus as claimed in claim 7, further comprising a time delay circuit having an input connected to an output of one of the demultiplexers, and an output connected to the input of one of the multiplexers.

9. Switching apparatus as claimed in claim 7, wherein at least some of the multiplexer inputs and the demultiplexer outputs are configured in software as stereo inputs and outputs, respectively.

10. Switching apparatus as claimed in claim 2, wherein each multiplexer comprises a two stage multiplexing switch.

11. Switching apparatus as claimed in claim 2, wherein the multiplexed signal of each multiplexer is connected to the demultiplexers via a respective coaxial cable, the apparatus further comprising an equaliser circuit connected between each cable and the demultiplexers-

12. Switching apparatus as claimed in claim 11, wherein the multiplexed signal from each multiplexer includes a synchronising signal component, the equaliser circuit further comprising a master clock and means responsive to the synchronising signal component for synchronising the multiplexer to the master clock.

13. Switching apparatus as claimed in claim 11, wherein the outputs of the equaliser circuits are connected to the demultiplexers by a ribbon cable, further- comprising a matching impedance connected between the output of each equaliser circuit and the ribbon cable.

14. Switching apparatus as claimed in claim 2, wherein the multiplexed signal from each multiplexer includes a synchronising signal component, and each demultiplexer comprises means responsive to the synchronising signal component for synchronising the demultiplexer to the multiplexer.

15. Switching apparatus as claimed in claim 2, wherein each demultiplexer comprises input switch means having a first two-stage switch for selecting the multiplexed signal output of one of the multiplexers, and a second two-stage switch for sampling the selected multiplexed signal.

16. Switching apparatus as claimed in claim 15, further comprising a user-operable dual concentric rotary switch for controlling the input switch means.

17. Switching apparatus as claimed in claim 15 wherein the second two-stage switch comprises two series- connected switches of reverse orientation.