WO1993017455A3 - Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die - Google Patents

Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die Download PDF

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Publication number
WO1993017455A3
WO1993017455A3 PCT/US1993/001490 US9301490W WO9317455A3 WO 1993017455 A3 WO1993017455 A3 WO 1993017455A3 US 9301490 W US9301490 W US 9301490W WO 9317455 A3 WO9317455 A3 WO 9317455A3
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WIPO (PCT)
Prior art keywords
integrated
bonding
circuit die
packaging
conductive traces
Prior art date
Application number
PCT/US1993/001490
Other languages
French (fr)
Other versions
WO1993017455A2 (en
Inventor
Young Il Kwon
Louis H Liang
Original Assignee
Vlsi Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology Inc filed Critical Vlsi Technology Inc
Priority to JP5514969A priority Critical patent/JP2691799B2/en
Publication of WO1993017455A2 publication Critical patent/WO1993017455A2/en
Publication of WO1993017455A3 publication Critical patent/WO1993017455A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/19101—Disposition of discrete passive components
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    • H01L2924/20654—Length ranges larger or equal to 3000 microns less than 4000 microns

Abstract

A package design configuration for an integrated-circuit die (104) includes a leadframe having its bonding fingers (106) connected to the periphery of an electrically-insulated, heat-conductive substrate (102), formed, for example, of a ceramic material. A number of electrically conductive traces (110), or bonding islands, serve as intermediate bonding locations for shorter bonding wires (112, 116) connecting bonding pads (114) on the integrated-circuit die (104) to the bonding fingers (106) of the leadframe. The integrated-circuit die overlies the conductive traces while still providing an exposed portion of the conductive traces as a respective intermediate attachment area for respective bonding wires. The conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques.
PCT/US1993/001490 1992-02-20 1993-02-19 Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die WO1993017455A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5514969A JP2691799B2 (en) 1992-02-20 1993-02-19 Integrated circuit package design with intervening die attach substrate bonded to leadframe

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83919192A 1992-02-20 1992-02-20
US07/839,191 1992-02-20

Publications (2)

Publication Number Publication Date
WO1993017455A2 WO1993017455A2 (en) 1993-09-02
WO1993017455A3 true WO1993017455A3 (en) 1993-11-25

Family

ID=25279091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/001490 WO1993017455A2 (en) 1992-02-20 1993-02-19 Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die

Country Status (2)

Country Link
JP (1) JP2691799B2 (en)
WO (1) WO1993017455A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598031A (en) * 1993-06-23 1997-01-28 Vlsi Technology, Inc. Electrically and thermally enhanced package using a separate silicon substrate
KR960703274A (en) * 1993-06-23 1996-06-19 토마스 씨, 토코스 ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE
US5757070A (en) * 1995-10-24 1998-05-26 Altera Corporation Integrated circuit package
WO2001027996A1 (en) * 1999-10-14 2001-04-19 Motorola Inc. Reconfigurable pinout ball grid array
TWI325617B (en) 2006-12-18 2010-06-01 Chipmos Technologies Inc Chip package and method of manufacturing the same
US11476182B2 (en) * 2017-10-10 2022-10-18 Shenzhen Chipuller Chip Technology Co., Ltd Assembly of flexible and integrated module packages with leadframes

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (en) * 1979-12-28 1981-10-07 Fujitsu Limited Multi-lead plug-in type package for circuit element
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
EP0351581A1 (en) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG High-density integrated circuit and method for its production
EP0443044A1 (en) * 1989-09-12 1991-08-28 Kabushiki Kaisha Toshiba Lead frame for semiconductor device and semiconductor device using the lead frame

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0036907A1 (en) * 1979-12-28 1981-10-07 Fujitsu Limited Multi-lead plug-in type package for circuit element
US4754317A (en) * 1986-04-28 1988-06-28 Monolithic Memories, Inc. Integrated circuit die-to-lead frame interconnection assembly and method
US4774635A (en) * 1986-05-27 1988-09-27 American Telephone And Telegraph Company At&T Bell Laboratories Semiconductor package with high density I/O lead connection
EP0351581A1 (en) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG High-density integrated circuit and method for its production
EP0443044A1 (en) * 1989-09-12 1991-08-28 Kabushiki Kaisha Toshiba Lead frame for semiconductor device and semiconductor device using the lead frame

Also Published As

Publication number Publication date
WO1993017455A2 (en) 1993-09-02
JPH06507276A (en) 1994-08-11
JP2691799B2 (en) 1997-12-17

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