WO1993022728A1

WO1993022728A1 - A method and a system to transfer digital signals between a digital signal processor and peripheral circuits connected to it

Info

Publication number: WO1993022728A1
Application number: PCT/FI1993/000170
Authority: WO
Inventors: Hannu Tapani Esala; Esko Tapio Rautanen
Original assignee: Nokia Telecommunications Oy
Priority date: 1992-04-23
Filing date: 1993-04-23
Publication date: 1993-11-11
Also published as: FI90708C; FI921821A0; FI90708B; DE4391850T1; AU3955293A; DE4391850C2

Abstract

The description relates to a method and a system to transfer digital signals between a digital signal processor or a DSP circuit (3) and peripheral circuits (1, 2) connected to it, the signals being transferred between the peripheral circuits and the DSP circuit relatively often compared to the operational speed of the DSP circuit. Then there is a difficulty in that other activities of the DSP circuit repeatedly must be interrupted in order to transmit and receive signals, which i.a. makes it difficult to write the program. Acccording to the invention this problem is obviated in that the digital signals are transferred from a peripheral circuit (1) to the DSP circuit (3) via a switching matrix (5), whereby a certain number of signals are assembled in the switching matrix and transmitted as a respective cluster to the DSP circuit or from the DSP circuit, and correspondingly between the assembled signals there remains a longer continuous period for signal processing in the DSP circuit. A typical example is an A/D-converter, which transmits digital signals in time slots on a time-division bus to the DSP circuit. With the aid of the switching matrix several signal samples can be grouped into sequential time slots and correspondingly the intervals between the groups add to form a continuous processing period.

Description

A method and a system to transfer digital signals between a digital signal processor and peripheral circuits connected to it

The object of the present invention is a method to transfer digital signals between a digital signal processor or a DSP circuit and peripheral circuits connected to it, a peripheral circuit transmitting signals to the DSP circuit or receiving signals from the DSP circuit relatively often compared to the speed of the DSP circuit. The invention also relates to a system to realize the method.

The invention is below described in a case where the peripheral circuit is an A/D-converter or a D/A-converter, respectively, but is should be understood that the invention is applicable also when the peripheral circuit is some other circuit transmitting signals to the DSP circuit or receiving signals from the DSP circuit. In other words, the peripheral circuit may in fact also be another DSP circuit.

Such circuits are generally interconnected through their serial interface or serial interfaces, the transmission mode usually being synchronous transmission. Then, depending on the situa¬ tion, we need one or two conductors for the signals to be processed, a clock signal and generally at least one frame signal indicating a significant location, such as the beginning of the transmitted signal.

The enclosed figure 1 shows an example of a usual connection between a DSP circuit and an A/D-converter or a D/A-converter, respectively. The A/D-converter 1 converts the input analog signal into a sampled digital signal (Data 1) , which is further supplied to the DSP-circuit 3 at a rate determined by the clock and frame signals. After processing of the digital signal the DSP circuit supplies the signal (Data 2) to the D/A-converter 2, which outputs an analog signal. Both the input signal Data 1 and the output signal Data 2 pass through the serial interface 4 of the DSP circuit. Figure 2 shows the signal flow diagram of the interface according to figure 1. The signals Data 1 and Data 2, respectively, are transmitted as frames containing 16 data bits, whereby the periods between the frames constitute periods during which Data 1 is available to the DSP circuit and during which Data 2 has to be available to the D/A-converter. The diagram is somewhat simplified, but it shows details essential to the matter under study.

In the prior art arrangement there occur problems when the DSP circuit receives and transmits signals relatively often compared to the operating speed of the circuit. Then signal transmission and reception often interrupt other activities and complicate the design of its program.

In a traditional way of connection the DSP circuit has to interrupt its other activities at regular intervals, receive data from the A/D-converter and output data to the D/A-converter. If the application is such (as often is the case) that the DSP circuit outputs and inputs data from other units besides the converters, this operation causes interrupts in addition to the previous interrupts. As an end result the DSP circuit has no continuous period longer than the sampling interval, which is known to be available for calculations without interrupts.

In addition to the actual signal processing calculations other operations are often required, e.g. message transfers between the DSP-circuits or between the DSP circuit and the main processor of the unit. To split this task into pieces and perform it little by little is very cumbersome.

The object of the present invention is to provide a method and a system which are suitable for cases like these, and which can obviate too frequent interrupts of the DSP circuit activities.

In order to achieve this objective the method according to the invention is characterized in what is said in the enclosed claim 1. The method according to the invention is characterized in claim 4, respectively.

Essential to the invention is thus that between the DSP circuits and the peripheral circuits is connected a switching matrix able to change the timing of input and output signals or messages, so that several sequential signals are temporally assembled, whereby respective signal time slots can be added to ^■ a continuous longer time slot, during which the DSP circuit is able to carry out the signal processing.

In an illustrative case where the signals are formed by sequential frames, preferably a certain number of frames are assembled into a cluster to be transmitted to the DSP circuit and accordingly out from the DSP circuit via the switching matrix.

The invention and its other features and advantages are described below as an example and with reference to the enclosed drawings, in which:

figures 1 and 2 show the circuit already described, and a signal flow diagram related to it; figure 3 shows a system according to the invention; and figures 4 and 5 show signal flow diagrams related to the operation of the system in figure 3.

In the example of figure 3 the DSP circuit has as peripheral circuits an A/D-converter 1 and a D/A-converter 2, in the same way as in the example of figure 1. However, the signals of the A/D- and D/A-converters are not supplied directly to the DSP circuit, but to the switching matrix 5, which further exchanges signals with the DSP circuit 3. The signal from the A/D- converter 1 comprises at equal distances situated samples S (Fig. 5) of 16 bits, which in this example are transmitted in the time slots on a 2 bit/s serial bus. A frame comprises 32 8-bit time slots TSO - TS31, one sample corresponding to two time slots. The frame structure of the serial buses is shown in figure 4.

Here we assume that the switching matrix has two Mbit/s serial buses, Bus 1 and Bus 2. In practice the switching matrix can have more buses, but this is not necessary in the example. Further we assume that the converters and the DSP circuit all use the same clock signal 2,048 MHz. The notations input direction and output direction in figure 5 always refer to the switching matrix. As is seen in figure 4 and figure 5, the switching matrix assembles four 16-bit samples into a respective cluster C and transfers this further to the DSP circuit. In a corresponding way the time slots are added to form a continuous processing period P when no samples are received, this period thus being available to the DSP circuit for signal processing.

Let us still compare the cases of figures 1 - 2 and 3 - 5.

In the time diagram we see that according to prior art those moments (shown by the arrows) when data is available to the DSP circuit are distributed at equal intervals. In many cases data must be read from the internal register of the DSP circuit very soon after it reached the register, because otherwise the next data will overwrite the previous data or will not be received at all. Modern systems use a sampling frequency of up to 48 kHz

(DAT recorder, full tape speed) to process sound signals. Then the sampling interval is about 20,8 μs. However, in order to simplify the examples we assume a sampling frequency of 32 kHz.

Then the sampling interval is 31,25 μs. This corresponds to a situation with half speed in DAT operation.

In a traditional way to make the connection the DSP circuit thus must interrupt its other operations at equal intervals of 31,25 μs and receive data from the A/D-converter and output data to the D/A-converter. In the arrangement according to the invention, or according to the figures 3 - 5, we obtain in the example the following time values:

- frame length 125 μs, period to read/write samples (8/32) x 125 μs = 31,25 μs, continuous period available for calculations 24/32) x 125 μs = 93,75 μs.

Thus the DSP circuit has a continuous processing period, which is threefold compared to a situation without the switching matrix.

As a further advantage the switching matrix according to the invention provides an excellent flexibility in signal proces¬ sing. In more extensive equipment, where several different circuits are connected to the DSP circuits, it is possible with the switching matrix to change the circuit connected to the time slots used by the DSP circuit. In principle this would also nowadays be possible with DSP circuits without a switching matrix, but then it is required that the DSP circuit itself changes the moment when it connects to the common serial bus. When a switching matrix is used the change can be made by the unit's main processor, and it is not even necessary that the DSP circuit knows about the change in the connection.

The arrangement according to the invention of course requires a little more equipment due to the need for the switching matrix.

The switching matrix further must be controlled into the correct state, i.e. it requires a program in the unit's main processor.

However, it must be noted that nowadays commercial switching matrix circuits are available at advantageous prices which are suited for circuits according to the presented example. ^•

If we use a sampling frequency which is not a sub-harmonic of the switching matrix clock signal, then the switching matrix clock signal must be separated from the clock signal of the A/D- and D/A-converters and the clock frequencies must be adapted by an adaptation circuit added between the converters and the switching matrix. The situation is like this if for example the sampling frequency is 48 kHz and the clock frequency of the switching matrix is 2,048 MHz. However, the use of an adaptation circuit does not change the practice according to the invention presented above, and does not affect the advantages which are provided.

Claims

1. A method to transfer digital signals between a digital signal processor or a DSP circuit (3) and peripheral circuits (1, 2) connected to it, the signals being transferred between the peripheral circuits and the DSP circuit relatively often compared to the operational speed of the DSP circuit, characterized in that the digital signals are transferred between the peripheral circuits (1, 2) and the DSP circuit (3) via a switching matrix (5) , whereby a certain number of signals are assembled in the switching matrix and transmitted as a respective cluster to the DSP circuit or from the DSP circuit, and correspondingly between signals thus assembled there remains a respective longer continuous period for signal processing in the DSP circuit.

2. A method according to claim 1, characterized in that the signals are transferred between the peripheral circuits (1, 2) and the DSP circuit (3) in time slots of frames, and that a certain number of time slots are respectively assembled into the cluster.

3. A method according to claim 1 or 2, in which an A/D-converter (1) and a D/A-converter (2^ is connected to the DSP circuit (3) , characterized in that signals from the A/D-converter (1) and signals to the D/A-converter (2) are transferred on one bus in the switching matrix (5) and that signals to and from the DSP circuit (3) are transferred on a second bus.

4. A system to interconnect digital signal processors or DSP circuits (3) and peripheral circuits (1, 2) connected to them, e.g. A/D-converters and D/A-converters, in which system signals are transferred between the peripheral circuits and a DSP circuit (3) relatively often compared to the operational speed of the DSP circuit, characterized in that between the peripheral circuits (1) and the DSP circuit (3) is connected a switching matrix (5) , which is arranged to assemble a certain number of digital signals transmitted from a peripheral circuit (1) and to " transfer these in one cluster to the DSP circuit (3) , whereby a respective longer continuous period remains for signal processing in the DSP circuit.

5. A system according to claim 4, characterized in that the peripheral circuits (1, 2) are arranged to transfer the digital signals in time slots of frames, and that the switching matrix (5) is arranged to assemble a certain number of respective time slots into one cluster for the DSP circuit (3) , whereby the intervals between the frames correspondingly add to form a continuous signal processing period in the DSP circuit.

6. A system according to claim 4 and 5, in which a signal transmitting A/D-converter (1) and a signal receiving D/A- converter (2) is connected to the DSP circuit (3) , characterized in that the switching matrix (5) has at least two buses, whereby a first bus operates between the switching matrix (5) and the converters (1, 2) transferring the signals in an original sequence, i.e. at equal intervals between the switching matrix and the converters, and a second bus operates between the switching matrix (5) and the DSP circuit (3) transferring signals between the switching matrix and the DSP circuit as clusters in time slots at unequal intervals.