WO1994003979A1 - Logic cell for field programmable gate array having optional input inverters - Google Patents

Abstract

Logic cells (310, 320, 330) in a logic device include optional inverters (300) on each input (A1, A2, A3, A4) to the cell. This selective inversion allows the designer to use inverters (301, 302, 303, 304) without consuming resources available for other functions, and eliminates the need for output inverters.

Description

LOGIC CELL FOR FIELD PROGRAMMABLE GATE ARRAY HAVING OPTIONAL INPUT INVERTERS

FIELD OF THE INVENTION The invention relates to programmable logic devices formed in integrated circuit semiconductor chips. More particularly, the invention relates to logic cells which are part of field programmable gate array chips.

BACKGROUND OF THE INVENTION Programmable devices are currently available in several different architectures. Earliest of the programmable devices are the programmable logic array (PLA) devices which comprise a plurality of AND gates programmably connected to a second plurality of OR gates. These devices can generate any combinational logic function, because any combinational logic function can be written as a sum of products, the products being generated in the AND array and the sums being generated in the OR array. These two level logic devices (one AND level and one OR level) are simple to program, and it is easy to predict the time delay for generating an output. However, the silicon area needed to calculate a complex logic function can be undesirably large. More recently, programmable logic devices called field programmable gate arrays or FPGAs have been developed. These devices comprise an array of programmable logic cells which can be interconnected by programmable interconnect lines to generate complex logic functions. In an FPGA device, a function need not be calculated as a two-level sum of products because it is possible to feed the output of any one logic cell to an input of any other logic cell, and thereby form a chain, generating a function which has multiple levels of logic. Thus it is possible to implement complex logic in a smaller physical area. Several architectures of these field programmable logic devices are available today. The various devices differ in the complexity of a single logic cell. Some manufacturers offer devices having logic cells such as shown in Fig. 1 which are quite small (fine grained architecture) . Others offer devices having logic cells such as shown in Fig. 2 which are considerably larger and which handle larger functions within a single logic block (coarse grained architecture) . A small logic cell such as shown in Fig. 1 has the advantage of being able to be completely filled by the logic of a user, and thereby not leave unused logic resources within the cell. It may be possible to generate either combinational or sequential functions from a plurality of small logic cells. However, with fine grained architectures made up of small logic cells, it requires many logic cells to generate a complex logic function. A function which must make use of more than one logic cell must use programmable interconnect line to generate the function. When the signal path passes through resistive programmable elements, the time delay associated with capacitive and resistive interconnect line considerably slows down the response of the sequential function. The larger celled (coarse grained) logic devices can generate complex functions quickly within a single logic block. However, if the user specifies a set of functions which do not make full use of the rather large logic cell, portions of the logic cell will be unused. Also, some of the fairly large logic cells include separate resources for generating combinational functions and for generating sequential functions. The cell of Fig. 2 is such a cell. If a user wants a circuit which uses many combinational functions and few sequential functions, many sequential resources will be unused. Likewise, if the user wants many sequential functions and few combinational functions, many combinational functions will go unused. Another significant consumer of silicon faced by designers is that signals must be inverted, and using a configurable cell to generate an inverter consumes resources otherwise available for more powerful functions. Prior efforts have been made to provide dedicated hardware for the invert function. A structure described by Quicklogic in a publication entitled pASIC™ 1 Family ViaLink™ Technology Very High Speed CMOS FPGAs published May 1991 shows a programmable structure using two-input AND gates which have one inverted input and one non-inverted input. This structure thus gives a choice of applying a signal to the inverted or the non-inverted input. Though this solution allows for applying signals to both the inverted and noninverted inputs, when used simply to offer an optional inversion, this solution doubles the number of input lines needed. Thus using the above structure to achieve optional inverters adds considerable silicon area and complexity to a cell.

SUMMARY OF THE INVENTION According to the present invention, logic cells in a logic device include optional inverters on each input to the cell. This selective inversion allows the designer to use inverters without consuming resources available for other functions, and eliminates the need for output inverters. Since any number of inputs to the cell can be inverted, the cell can decode any address equally fast, and a designer can therefore rely on the time required to decode an address regardless the ratio and arrangement of 0's and l's (inversions and noninversions) in the address. Also a signal which fans out from an output port and is inverted at some destinations and not others is handled easily with the present invention, because providing inverters on all inputs allows full flexibility. The invention is preferably implemented by providing two paths for each input signal, one path which passes through an inverter and one path which bypasses the inverter. Pass transistors on each path select which path forwards the input signal. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a prior art logic cell having a small cell size. Fig. 2 shows a prior art logic cell having a large cell size as used in the Xilinx 3000 series parts. Fig. 3 shows a logic cell according to the present invention. Figs. 4A and 4B show a two-input multiplexer and its implementation using the cell of Fig. 3. Figs. 5A and 5B show an exclusive-OR gate and its implementation using the cell of Fig. 3. Figs. 6A and 6B show an exclusive-NOR gate and its implementation using the cell of Fig. 3. Figs. 7A and 7B show a sum-of-products circuit and its implementation using the cell of Fig. 3. Figs. 8A and 8B show a latch with clear and its implementation using the cell of Fig. 3. Figs. 8C shows the equivalent circuit formed by the circuit of Fig. 8B. Figs. 8D and 8E show a latch with clear having the opposite clock polarity from that of Figs. 8A-8C. Fig. 8F shows the equivalent circuit formed by the circuit of Fig. 8E. Figs. 9A and 9B show a set-reset latch and its implementation using the cell of Fig. 3. Figs. 10A and 10B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The logic cell of Figure 3 comprises seven major sections: (1) a programmable input inverter stage 300, (2) a cascade-in first combinational stage 310, (3) a feedback first combinational stage 320, (4) a second combinational stage 330, (5) an output driver stage 340, (6) a selective global reset circuit 350, and (7) a set of configuration control units CCUl through CCU7 for controlling the configuration of the cell.

Overview of the Seven Sections of Fiσ. 3 Input buffer stage 300 comprises four input buffers 301 through 304, each of which can be inverting or non-inverting as selected by the user. Providing optional inverters at every input allows the elimination of inverters at the outputs, thus combinational logic resources never need be used simply for the purpose of inverting a signal. Cascade-in first combinational stage 310 comprises a 3- input NAND gate 311 and a 2-input OR gate 312. OR gate 312 receives a cascade enable control input 313 and a cascade input 314 from an adjacent cell. OR gate 312 provides input to NAND gate 311. Also provided as input to NAND gate 311 are outputs from selectively inverting input buffers 301 and 302. Feedback first combinational stage 320 also comprises a three-input NAND gate 321 fed by output signals from selectively inverting input buffers 303 and 304. ΝAΝD gate 321 further receives input from OR gate 322 which receives on one of its input terminals a feedback signal 332 and on another input terminal a feedback enable control input 323. Second combinational stage 330 can be programmed to provide a ΝAΝD or a NOR function of outputs from the cascade combinational stages 310 and 320. Second combinational stage 330 provides an output signal 332 which can be fed back by OR gate 322 to AND gate 321, can further be provided as a cascade OUT signal which becomes a cascade IN signal to an adjacent cell, and which is provided to output driver stage 340, where it can be driven onto the interconnect structure and used as input to other cells. Output driver stage 340 includes a buffer 341 of sufficient strength to drive the output signal onto an interconnect structure represented in Fig. 3 by interconnect lines 1 and 12 . Global reset circuit 350 allows the cell to be reset when used as a latch or flip flop. Circuit 350 includes means for pulling low the output 332 of second combinational stage 330 in response to a global reset signal. It is necessary to reset only the cells which are used as latches or flip flops in the array. Thus circuit 350 provides a reset voltage only when feedback stage 320 is configured as a latch, and only at the part of a clock cycle when the cell is latching and is not in the data receive mode. The circuit adds minimum capacitance when inactive and draws minimum power when resetting the array. Configuration control units CCUl through CCU7 store configuration information which configures the cell during normal operation.

Example Implementations of the Circuits of Fiσs . 4A through 10A Shown in Fiσs. 4B through 10B Respectively Figs. 4A through 10A show some of the functions which can be implemented in a single cell of Fig. 3. Figs. 4B through 10B show the configuration control bits which are applied to the cell of Fig. 3 to implement the respective functions. It can be seen by tracing the signal path through the cell of Fig. 3 that none of the functions implemented in the cell of Fig. 3 use a signal path through an antifuse or other interconnect configuration means. Thus the cell offers fast implementation of these functions. For example, Fig. 4A shows a two-input multiplexer having two inputs IN0 and INI, and a select input SEL. Fig. 4B shows an implementation of this two-input multiplexer. Input IN0 is applied to line Al and input INI is applied to line A4. Select input SEL is applied to lines A2 and A3. A logical 0 stored in the memory cell which controls configuration control unit CCU3 causes optional inverter 301 to be noninverting. (The configuration control units are discussed in more detail below.) Thus the value of IN0 is provided by optional inverter 301 to the B input of NAND gate 311. A logical 1 stored in the memory cell which controls configuration control unit CCU4 causes optional inverter 302 to invert the SEL select signal on line A2 and apply the inverted signal to the A input of NAND gate 311. The logical 0 controlling optional inverter 303 allows the SEL signal to be applied to the A input of NAND gate 321. Finally, the logical 0 controlling inverter 304 allows input INI to be passed noninverted to the B input of NAND gate 321. Three more memory cells control the cell of the invention, as represented by CCUl, CCU2, and CCU7. A logical 0 in CCU2 is inverted at the input to OR gate 312, causing OR gate 312 to apply a high signal to NAND gate 311 regardless of the signal on line 314. Thus NAND gate 311 is configured as the logical equivalent of a two-input NAND gate, as shown in Fig. 4A. A logical 0 in CCU7, inverted at the input to NAND gate 321 disables the feedback loop, so that NAND gate 321 operates as a two-input NAND gate as shown in Fig. 5A. Finally, a logical 1 in CCUl causes second combinational stage 330 to operate as a NAND gate. Recall that by deMorgan's theorem a NAND gate with inverted inputs is equivalent to an OR gate, thus NAND gates 311 and 321 in combination with NAND gate 330 form the AND gates and OR gate shown in Fig. 4A. Thus the circuit of Fig 3 configured as shown in Fig. 4B implements the multiplexer of Fig. 4A.

Implementation of XOR. XNOR. Sum-of-Products of Figs. 5A. 6A, and 7A Shown in Figs. 5B, 6B, and 7B, Respectively Figs. 5B, 6B, and 7B show the arrangement of logical 0's and l's in the seven CCUs of the cell of Fig. 3 to implement the functions shown in Figs. 5A, 6A, and 7A respectively. An understanding of these implementations can be understood from the detailed multiplexer description above.

Fiσs. 8A through 8F: Latch with Clear Fig. 8A shows a latch with clear which can be implemented by the circuit of Fig. 3. As shown in Fig. 8B, the D (data) input of Fig. 8A is provided on line Al of Fig. 3. Latch enable signal LE of Fig. 8A is applied to lines A2 and A3. Optional inverter 302 is set to be inverting and optional inverter 303 is set to be noninverting. The Reset input of Fig. 8A is provided to line A4. Feedback control unit CCU7 stores a logical 1 which enables the feedback path by applying a logical 0 to the C input of OR gate 322. The Q output signal is thus fed back through the D input of OR gate 322 to NAND gate 321. AND gates ANDl and AND2 and OR gate ORl of Fig. 8A are achieved (according to DeMorgan's theorem) by configuring second combinational stage 330 as a NAND gate. Fig. 8D illustrates a latch with clear in which the latch enable signal LE has the opposite polarity of that in Fig. 8A. Both polarities are needed when sequential latches are needed, for example in a flip flop. Fig. 8E shows the implementation of the latch of Fig. 8D in the Fig. 3 circuit, and Fig. 8F shows the equivalent circuit which results. Optional inverter 302 is configured to pass the LE signal through to the A input of NAND gate 311 and optional inverter 303 is configured as an inverter, passing the complement of A3 to the A input of NAND gate 321.

Set/Reset Latch Fig. 10A shows a set/reset latch which can be implemented as shown in Fig. 10B using the cell of Fig. 3.

4-Inout AND Gate Figs. 11A and 11B show a 4-input AND gate with one inverted input, and its implementation using the cell of Fig. 3. Note that second combinational stage 330 is configured as a NOR gate by a logical 0 from CCUl. With the two inverted inputs (the inverted outputs of NAND gates 311 and 321) second combinational stage provides the AND function. In the example of Fig. 11A, the A2 input is inverted. Therefore, a logical 1 in CCU4 causes optional inverter 302 to act as an inverter. Clearly any combination of inverted inputs may be selected. Other embodiments of the invention will become obvious to those skilled in the art in light of the above description. For example, another embodiment provides some but not all cell inputs with optional inverters. For a cell having many inputs, this may be a desirable alternative. These other embodiments are intended to fall within the scope of the present invention.

Claims

I claim: 1. A field programmable logic device comprising: a plurality of interconnect lines; a plurality of logic cells programmable to provide one of a plurality of logic functions, each logic cell having a plurality of input leads; for at least one of said input leads an optional inverter having: an optional inverter input terminal which can be connected to at least one of said interconnect lines, an optional inverter output terminal which connects to said at least one of said input leads, and means to provide on said optional inverter output terminal a selected one of a signal on said optional inverter input terminal and the complement of said signal on said optional inverter input terminal.

2. A field programmable logic device as in Claim 1 in which said optional inverter comprises: an inverter having an inverter input terminal connected to said optional inverter input terminal and having an inverter output terminal; means for selectively connecting one of said inverter output terminal and said inverter input terminal to said optional inverter output terminal.

3. A field programmable logic device as in Claim 2 in which said means for selectively connecting comprises: a first pass transistor connected between said inverter input terminal and said optional inverter output terminal; a second pass transistor connected between said inverter output terminal and said optional inverter output terminal; and a memory cell having true and complement outputs, one of said true and complement outputs connected to the control terminal of said first pass transistor, and the other of said true and complement outputs connected to the control terminal of said second pass transistor.

4. A field programmable logic device as in Claim 3 in which said memory cell is part of a shift register.

5. A field programmable logic device as in Claim 3 in which said shift register includes memory cells for controlling other parts of said logic cell.

6. A field programmable logic device as in Claim 1 in which said optional inverter for at least one of said input leads comprises one optional inverter for each of said input leads.