WO1994005039A1 - Semiconductor wafer for lamination applications - Google Patents

Semiconductor wafer for lamination applications Download PDF

Info

Publication number
WO1994005039A1
WO1994005039A1 PCT/US1993/007893 US9307893W WO9405039A1 WO 1994005039 A1 WO1994005039 A1 WO 1994005039A1 US 9307893 W US9307893 W US 9307893W WO 9405039 A1 WO9405039 A1 WO 9405039A1
Authority
WO
WIPO (PCT)
Prior art keywords
material layer
integrated circuit
electrically conductive
layer
electrically
Prior art date
Application number
PCT/US1993/007893
Other languages
French (fr)
Inventor
David A. Capps
Tyra M. Szwarc
Original Assignee
Capps David A
Szwarc Tyra M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Capps David A, Szwarc Tyra M filed Critical Capps David A
Priority to AU58357/94A priority Critical patent/AU5835794A/en
Publication of WO1994005039A1 publication Critical patent/WO1994005039A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing

Definitions

  • the present invention relates, in general, to integrated circuits and, more particularly, to multi ⁇ layer or three-dimensional integrated circuits and fabrication methods therefor. Description of the Art:
  • Integrated circuits are typically fabricated from semiconductor wafers cut from a large crystal.
  • the semiconductor wafers are generally from 200 ⁇ m to 400 ⁇ m thick and are of uniform crystalline material.
  • the actual integrated circuit is formed on the top surface of the wafer by various doping, oxide, metal deposition and etching processes. Since this provides a basic two- dimensional structure, the overall density of such integrated circuits per given area is limited. In an effort to overcome this density limit and to produce devices having greater densities, it has been proposed to form semiconductor devices using multiple layers of integrated circuitry. The greatest obstacle in the production of multiple layers of integrated circuits is the solid semiconductor crystalline wafer. Vertical conductive paths are required for multiple layer construction.
  • a solid wafer is not directly usable without expensive and time consuming processing methods used to produce the required vertical conductive paths.
  • Many ways of forming such multiple layer, integrated circuit devices are known, the most common of which is through the use of alternating layers of insulating material and semiconductive material applied to the semiconductive wafer through various deposition processes, such as chemical vapor deposition or molecular beam epitaxy. Through these processes, multiple layers may be formed with circuits integrated in each semiconductor layer.
  • the main drawback of these processes is that as multiple layers of integrated circuits are formed, the number of defective devices increases. In the basic two-dimensional integrated circuit, each integrated circuit formed on a wafer is tested and the defective circuits discarded.
  • the present invention is a multiple layer integrated circuit and method of fabrication therefor.
  • the multiple layer integrated circuit is formed by the method comprising the steps of:
  • the method also includes the step of forming an enlarged base pad in the insulating material layer which supports each electrically conductive post.
  • the step of separating the substrate from the integrated circuit layer preferably includes the steps of removing a peripheral flange formed on the protective material layer which surrounds the side edge of the dissolvable material layer to expose the dissolvable material layer to water or other solution to dissolve the material layer and thereby separate the substrate from the protective material layer.
  • the protective material layer is then removed by placing the integrated circuit layer in a suitable acid.
  • a low temperature melting point layer may be disposed on the exposed ends of the conductive posts to provide electrical and mechanical interconnection between a plurality of like formed integrated circuit dies which are arranged in a stacked alignment.
  • the individual conductive traces on each integrated circuit in each layer are connected to the conductive posts to provide electrical circuit interconnection between the various integrated circuit layers.
  • the multi-layer integrated circuit laminate of the present invention is ideally suited for use in a high density memory application.
  • the memory cells or matrix are formed in a predetermined size on each integrated circuit layer.
  • the memory cells are preferably concentrated towards the center of each integrated circuit die so as to provide peripheral space for the electrically conductive posts extending through each die to adjacent dies.
  • the drivers, sensors and decode logic associated with a typical memory device are preferably formed in a separate integrated circuit layer which is supported by a substrate providing heat sink characteristics.
  • the active circuit is preferably concentrated in the center of the integrated circuit die with the electrically conductive posts being concentrically arranged in rows surrounding the active circuit. Peripheral conductive pads may also be formed on this integrated circuit layer and connected to the posts, the active circuit or to provide connections to other integrated circuits.
  • a semiconductor wafer suitable for lamination applications is formed by a process comprising the steps of:
  • the method preferably also includes the post- processing steps of:
  • the electrically conductive posts also include an enlarged base pad which supports each electrically conductive post.
  • the step of forming the electrically insulating layer over all surfaces of the dissolvable material core and the optional electrically conductive posts preferably includes the step of oxidizing a thin semiconductor material layer disposed on the core and/or the conductive posts to form an insulating layer around the optional electrically conductive posts and over the exposed surface of the core.
  • the step of dissolving the core material includes the step of inserting the wafer into a dissolving solution, such as a suitable acid.
  • a low temperature melting point layer of electrically conductive metal or other suitable alloy may be disposed on the exposed ends of the electrically conductive posts during or after the formation of integrated circuits or other semiconductor devices.
  • the purpose of low temperature melting point layer is to provide electrical and mechanical interconnection between a plurality of like formed integrated circuit dies which are arranged in a stacked alignment.
  • the individual conductive traces on each integrated circuit or semiconductor device are connected to the conductive posts to provide electrical circuit interconnection between the various semiconductor layers arranged in a stacked alignment.
  • the wafer of the present invention is ideally suited for use in fabricating and constructing multiple layer integrated circuit assemblies.
  • the multiple layer integrated circuit device and fabrication method therefor of the present invention uniquely enables a thin integrated circuit die to be formed with planar surfaces thereby avoiding surface distortion problems and enabling electrically conductive posts to be formed in and through each integrated circuit layer or die.
  • the dies may be easily interconnected in an aligned stack by electrically and mechanically interconnecting the conductive posts extending through each die thereby providing electrical connection between each integrated circuit layer. This enables a high density integrated circuit device to be formed.
  • the fabrication method of the present invention provides a single thin layer integrated circuit which is strong and rigid enough to remain intact during the various processing steps employed to form an integrated circuit or semiconductor device thereon while at the same time eliminating the expensive and time consuming post processing methodology previously employed to form conductive posts in semiconductor dies.
  • Figures 1-8 are partial, cross sectional views showing the sequential steps of one embodiment of the present fabrication method for forming an integrated circuit laminate or layer for use in a multiple layer integrated circuit device;
  • Figure 9 is a partial, cross sectional view showing the multiple layer stacking of individual integrated circuit laminates made according to the present method and shown in Figures 1-8;
  • Figure 10 is a plan elevational view of an alternate embodiment of a multiple layer integrated circuit device constructed in accordance with the teachings of the present invention;
  • Figure 11 is a partial, cross sectional view showing the mounting of heat conductors in the integrated circuit device shown in Figure 10;
  • Figure 12 is a plan view of a base integrated circuit layer of a multiple layer integrated circuit 10 device devised for memory applications;
  • Figure 13 is a cross sectional view generally taken along line 13-13 in Figure 12;
  • Figure 14 is a partial, cross sectional view showing a multiple layer integrated circuit device 15 including the layer shown in Figures 12 and 13;
  • Figures 15-19 are partial, cross sectional views showing the sequential steps in a second fabrication method of the present invention used to form a single thin wafer; 20.
  • Figures 20, 21, 23 and 24 are partial, cross sectional views showing the sequential steps in the post ⁇ processing of the wafer shown in Figure 19 after the semiconductor circuit has been formed in the top surface of the wafer; 25
  • Figure 22 is a partial, cross sectional view of the holding fixture and wafer used for handling the wafer in Figure 21; and
  • Figure 25 is a partial, cross sectional view of like formed integrated circuit dies arranged in a stacked 30 alignment.
  • Figures 1-8 depict the various steps of the fabrication method of the present invention used in forming individual integrated circuit lamination layers 35 which are subsequently stacked into a multiple layer integrated circuit device. It should be understood that Figure 1-8 depict a portion of an overall structure having a predetermined size and shape, such as a generally disc-like shape, which will include a number of identical integrated circuits, as described hereafter.
  • a substrate 10 is initially provided in a predetermined shape, such as a disc-like shape.
  • the substrate 10 is formed of a suitable rigid material, such as a ceramic, for example only.
  • the substrate 10 has opposed top and bottom surfaces 12 and 14, respectively, and a peripheral side edge 16.
  • the overall size of the substrate 10 could be that of a conventional semiconductor wafer used to form a plurality of integrated circuits.
  • a thin layer 18 of a dissolvable material is formed or disposed by conventional means on the top surface 12 of the substrate 10.
  • the layer 18 may be applied by coating, for example, the top surface 12 of the substrate 10.
  • the dissolvable material forming the layer 18 may be any suitable material which is dissolvable in water or other weak solutions and has a melting point above 1200°C.
  • the dissolvable material can be calcium aluminate or other suitable material. It is also important that the dissolvable material will not react with the semiconductor material used in the present method, as described hereafter.
  • a protective material layer 20 is formed or disposed over the top of the dissolvable material layer 18.
  • the protective material layer 20 is preferably formed of a metallic material, such as chromium, and is applied in such a way so as to form a smooth, flat surface for the formation of an epitaxial layer thereover, as described hereafter.
  • the protective material layer 20 is formed with an outer peripheral flange 22 which extends over the entire side edge of the dissolvable material layer 18 and a portion of the side edge 16 of the substrate 10 to completely seal the dissolvable material layer 18 therein.
  • a plurality of electrically conductive posts are formed on the top surface 24 of the protective material layer 20.
  • each of the posts 26, 28, etc. is preferably identical for each individual integrated circuit formed on the substrate 10 so as to enable stacking of such integrated circuits as described hereafter.
  • the conductive posts 26 and 28 are each provided with an enlarged base pad 30 which is formed on the top surface 24 of the protective material layer 20 by several layers of metal deposition.
  • the base pad 30 has a larger cross sectional area than the conductive posts 26 and 28 and forms a mechanical lip so as to prevent the unintentional removal of metal from the conductive posts 26 and 28.
  • the individual conductive posts 26 and 28 are then formed by several layers of metal deposition on each base pad 30.
  • the base pads 30 and the conductive posts 26 and 28 may be formed of any suitable electrically conductive material, such as electrically conductive metals or alloys thereof. Suitable refractory metals, such as titanium, may also be employed.
  • the base pads 30 and the conductive posts 26 and 28 may be formed by any suitable means, such as metal deposition, electro-plating, etc.
  • the conductive posts 26 and 28 may be of any shape, such as circular or square, in cross section and may be relatively thin, approximately 5 ⁇ m in thickness. However, each post 26 and 28 must extend vertically for the minimum anticipated thickness of the semiconductive material layer which is approximately 25 ⁇ m to 50 ⁇ m.
  • an electrically insulating material layer 32 is disposed or deposited over the entire surface of the protective material layer 20 and the entire peripheral surface of the base pads 30 and the electrically conductive posts 26 and 28.
  • the insulating material layer 30 also extends over the side lip 22 of the protective material layer 20 and into contact with the substrate 10.
  • the insulating material layer 32 may be formed of any suitable electrically insulating material, such as, for example, calcium fluoride. Oxidized silicon may also be used. The semiconductor materials are then oxidized to form the insulating layer 32 which will ultimately become the bottom surface of each integrated circuit layer or laminate.
  • the insulating material layer 32 provides insulation between the various integrated circuit layers, as described hereafter, and also reduces migration of contaminants throughout the various layers.
  • a layer 36 of semiconductive material is deposited by suitable means over the insulating material layer 32 and slightly in excess of the height of the conductive posts 26 and 28, as shown in Figure 4.
  • the semiconductive material layer 36 may be formed by any suitable method, such as molecular beam epitaxy or chemical vapor deposition.
  • the top surface is polished or otherwise treated to remove excess material and to create a flat surface 38, shown in Figure 5, which exposes the top ends 40 of each conductive post 26, 28, etc.
  • the desired circuit is then integrated into the top surface 38 of the semiconductive material layer 36 by standard processes and the required conductive surface traces 39 formed and extending from the integrated circuit to the conductive posts 26, 28, etc.
  • each upper electrically conductive pad 42 is then formed on the exposed top surface 40 of each conductive post 26, 28, etc.
  • the conductive pads 42 may be formed during the formation of the integrated circuit in the semiconductive material layer 36 as part of the conductive surface traces 39.
  • each upper conductive pad 42 may be formed of a suitable conductive material, such as a metal, i.e., aluminum, etc.
  • a low melting point, electrically conductive material layer or pad 44 is then formed or disposed on each upper conductive pad 42. Tin, zinc, or alloys thereof may be used to form the low melting point electrically conductive material layer 44 or pads so as to provide both electrical and mechanical connection between the integrated circuit laminations or layers. This completes the formation of the integrated circuits on a single wafer. Each circuit may then be tested, with defective circuits being marked in a normal manner for non-use.
  • the semiconductive layer 36 with its bottom located insulating material layer 32 is separated from the substrate 10 by first removing, such as by grinding, the peripheral edges of the semiconductive material layer 36, the insulating material layer 32 and, more importantly, the peripheral side lip 22 and adjacent flange of insulating material from the peripheral side edge of the substrate 10, as shown in Figure 7.
  • a holding means 50 in the form of a vacuum holder is employed to prevent cracking or other damage to the integrated circuit laminate and to provide an easy means for handling the integrated circuit laminate during further processing.
  • a holding means 50 may include a suitably formed holder 52 having a shape slightly larger than the integrated circuit wafer.
  • the holder 52 is formed with an annular rim 54 which surrounds and extends below a portion of the side edge of the semiconductive material layer 36 on the wafer.
  • An annular seal ring 56 is supported in the annular rim 54 of the holder 52 and seals against the peripheral edge of the semiconductive layer 36 and a porous support member 58 mounted in the holder 52.
  • the porous support 58 is formed of any suitable porous material so as to enable a vacuum source applied to an inlet 60 formed in the holder 52 to be used to releasably attach the integrated circuit wafer to the holder 52.
  • the holder 52 is used to place the integrated circuit laminate in water or other solution to dissolve the dissolvable material layer 18. Since the peripheral side edge of the dissolvable material layer 18 has been exposed by the grinding or removal step described above, water or any other solution readily dissolves the dissolvable material layer 18 to separate the substrate 10 from the protective material layer 20.
  • the integrated circuit laminate is then placed via the holder 52 into a suitable solution, such as dilute sulfuric acid, so as to remove the protective material layer 20 from the insulating material layer 32 thereby exposing the insulating material layer 32 which forms the bottom surface of the integrated circuit laminate.
  • the holder 52 is then separated from the integrated circuit lamination or layer by releasing the vacuum therefrom.
  • a base layer 74 which may be another integrated circuit, a printed circuit board, etc., is provided with conductive base pads 76 which are aligned with and engage the low melting point pads 62 connected to the base pads 30 of the conductive posts 26 and 28 in the lowermost integrated circuit die 70.
  • a number of like integrated circuit dies shown by reference numbers 72 and 73, are stacked on the integrated circuit die 70, with the bottom base pads 30 of each integrated circuit die 72 and 73 being aligned with the corresponding upper conductive pads 42 of the adjacent die to form a stacked, aligned arrangement of integrated circuit dies 70, 72, 73, etc. It will be understood that the number of individual dies interconnected in a stack may be varied to suit the requirements of a particular application.
  • a topmost layer 76 of a protective insulating material may be applied over the uppermost integrated circuit die 73 to complete the multiple layer integrated circuit device made according to the teachings of the present invention.
  • a multiple layer integrated circuit device constructed in accordance with the teachings of the above-described method affords several advantages over previously devised multiple layer integrated circuits.
  • a multiple layer integrated circuit device of the present invention has a high density and, further, has a high yield since defective integrated circuits in each layer or laminate are removed before the integrated circuits are arranged in a vertical, stacked arrangement. Further, since each laminated layer is fabricated separately, collective surface distortion which occurs when multiple layers are deposited onto underlying layers is avoided. As such, each integrated circuit layer has its own flat base surface and is not dependent upon the surface geometry of the underlying layers.
  • Figure 10 and 11 Another embodiment of the present invention is shown in Figure 10 and 11. In this embodiment.
  • Figure 10 depicts a plan view of the top layer or laminate of an integrated circuit device fabricated according to the present invention, with the top protective insulating layer 76 being removed for clarity.
  • the electrically conductive posts of which only two posts 26 and 28 are numbered, are provided in a predetermined pattern about the periphery of the integrated circuit die forming the laminate 73. Each conductive post is vertically aligned with a corresponding post in an underlying integrated circuit laminate, as described above.
  • the conductive traces from the integrated circuit formed in the semiconductive material 36 are connected to the posts 26, 28, etc., in a normal manner.
  • Such apertures 80 may be formed by any suitable means, such as by use of a laser.
  • the apertures 80 in each integrated circuit die 70, 72, 73, etc., are aligned so as to form one or more openings extending continuously through all of the dies or layers in the multiple layer integrated circuit device.
  • a heat conductive means such as a metallic rod 84, extends through each coaxial alignment of apertures 80 in the multi-layer integrated circuit stack as shown in Figure 11.
  • Each conductive rod 84 is insulated from the surrounding integrated circuit by the insulating layer 82, but is capable of transmitting heat generated by the integrated circuits from each layer outward from each die or layer of the multi-layer integrated circuit stack to the top of the stack.
  • An enlarged heat conductive plate 86 may be disposed below the lowermost integrated circuit layer 70 and connected to the plurality of heat conductive rods 84, as shown in Figure 11.
  • Figures 12 and 13 depict another embodiment of the present multiple layer integrated circuit which is designed specifically for a high density memory application.
  • This application utilizes individual integrated circuit layers or dies constructed in accordance with the fabrication method described above.
  • the memory circuits can be formed by any conventional crystalline or amorphic process and may be either volatile or non-volatile in nature.
  • the semiconductive material used to form each layer may be any silicon based semiconductor, as well as germanium or GaAs material.
  • the integrated circuitry forming the drivers, sensors and memory decode logic are concentrated in a central area 102 in a semiconductive layer 96.
  • Surface traces 98 extend outward from the peripheral edges of the integrated circuit to electrically conductive pads 100 mounted on the top surface of the base layer 96.
  • the conductive pads 100 are arranged in concentric rows, as shown in Figure 12, for purposes which will be described in greater detail hereafter.
  • Conductive traces 94 are also are formed between the semiconductive material layer 96 and a base layer 92 and extend through the layer 96 to the drivers, etc..
  • the base layer 92 acts as a substrate and may be formed of any suitable material which provides high heat transmissibility.
  • the base 92 thus acts as a heat sink for the active circuit elements formed in the semiconductive material layer 96.
  • a plurality of peripherally mounted terminals 104 may also be formed on the base layer 92 and connected to the drivers, decode and sensor circuitry in the layer 96 by the traces 94 to other external integrated circuits.
  • Individual integrated circuit layers containing the desired number of memory cells or circuits are stacked in a vertical arrangement over the base layer and semiconductive material layer all denoted generally by reference number 90 as shown in Figures 13 and 14.
  • Each of the integrated circuit layers 104, 106, 108 and 110 are formed as described above with through extending electrically conductive posts 112.
  • Each of the posts 112 are electrically connected to one of the conductive pads 100 on the base layer 90 by means of a low temperature melting point material layer similar to the layer 44 described above.
  • Surface conductive traces 114 extend between each of the electrically conductive posts 112 in each layer to the active circuit elements of the integrated circuit formed in each layer. It will be understood that the number of individual layers 104, 106, 108 and 110 may be varied depending upon the requirements of a particular application. In addition, the size or density of memory cells in each layer may also be varied. Another feature of this embodiment of the present invention is shown in Figure 14.
  • electrically conductive posts 112 are arranged in concentric rows on the base layer 90 and through the succeeding stacked layers 104, 106, 108 and 110, certain rows of electrically conductive posts may be eliminated from uppermost layers or, even if present, not electrically connected to the next adjacent upper layer as such connections may not be necessary.
  • FIG. 15-23 Another fabrication process according to the present invention is shown in Figures 15-23. This process is particularly devised for forming a thin, single layer integrated circuit.
  • a core or substrate A core or substrate
  • the core or substrate 130 is formed of a dissolvable material such as chromium. This material provides a rigid substrate; while being easily dissolvable so as to be easily removed from the other material layers forming semiconductor wafer.
  • the next step of the present method is optional and involves the formation of at least one and preferably a plurality of electrically conductive posts 132.
  • a base pad 134 of a larger cross sectional area than the post 132 is formed on the core or substrate 130 by normal metal deposition and etching.
  • the conductive posts 132 are also formed by metal deposition and etching from a suitable material, such as tungsten.
  • the conductive posts 132 may be of any shape, such as circular or square, in cross section and may be relatively thin, i.e., approximately five ⁇ in thickness. Further, each conductive post 132 extends vertically from the base pad 134 for a suitable distance equal to the minimum anticipated thickness of the semiconductive material layer which will be applied thereover.
  • each of the posts 132 may be varied as desired to suit the particular application of the integrated circuit or semiconductor device to be formed on the core 130.
  • the arrangement of the conductive posts 132 is identical for each integrated circuit die formed on the wafer.
  • the entire top, bottom and side surfaces of the core 130, the base pads 134 and the electrically conductive posts 132 are covered with a thin layer of a protective, electrically insulating material, such as polysilicon 136.
  • the polysilicon layer 136 is then oxidized to form an electrically insulating layer 136 which surrounds all of the exterior surfaces of the core 130, the base pads 134 and the electrically conductive posts 132.
  • the next step in the present method involves the application of one or more layers of a single cyrstalline silicon material 138 over the electrically insulating layer 136 covering the top surface of the core 130, the base pads 134 and the electrically conductive posts 132.
  • the semiconductive material layer 138 completely surrounds all of the exterior surfaces of the electrically conductive posts 132 and the base pads 134.
  • the single crystalline material forming the layer 138 is deposited by suitable means, such as molecular beam epitaxy, chemical vapor deposition, or other suitable processes. Further, the depth of deposition of the layer 138 exceeds the height of the vertical electrically conductive posts 132 and can vary, for example, from five ⁇ m to 10 ⁇ m.
  • the top surface 140 of the semiconductive material layer 138 is ground and polished to expose the top ends 142 of the electrically conductive posts 132.
  • the exposed top end 142 of the conductive posts 132 thus forms a finished surface for the fabrication of integrated circuits or other semiconductor devices.
  • the grinding and polishing step forms a smooth surface on the semiconductor layer suitable for integrated circuit formation.
  • a top electrically conductive pad 144 is then formed on the top ends 142 of each of the electrically conductive posts 132.
  • the pads 144 may be formed by suitable means, such as metal deposition and etching, for example only.
  • the conductive pads 144 are formed of a suitable electrically conductive, low temperature melting point material to provide electrical connections through the conductive posts 132 on one integrated circuit die to conductive posts on additional semiconductor dies in different layers of a multiple stack of such integrated circuit dies. Such pads 144 are not needed in the case where the integrated circuit dies formed on the wafer are to be used in a non-stacked application.
  • the bottom surface 131 of the core or substrate 130 and the peripheral side edge 133 of the core 130 are ground to remove the insulating layer 136 previously disposed thereover and to expose the bottom surface 131 and the side edge surface 133 of the core 130. This essentially forms the wafer 145.
  • the wafer 145 is then placed in a suitable holding fixture 50 as shown in Figure 22.
  • the holding fixture 50 is the same as that described above and shown in Figure 8.
  • the top surface of the pads 144 is placed against a porous ceramic support 58 mounted in the holder 50.
  • the holder 50 and the wafer 145 mounted therein is then inserted into a dissolving solution such as an acid, i.e., sulfuric acid, to dissolve and remove the core 130, as shown in Figure 23.
  • Bottom pads 148 formed of a low temperature melting point, electrically conductive material are then attached to each of the base pads 134 by suitable metal deposition and etching, for example as shown in Figure 24.
  • the bottom pads 148 provide an electrical and mechanical bond between like formed integrated circuits or other semiconductor devices formed on like wafers 145.
  • the wafer 145 can then be cut by laser or other suitable means to separate each die from the complete wafer 145.
  • individual dies may then be assembled in a stacked arrangement with the individual electrically conductive posts 132 vertically aligned through the stack of dies 150, 152 and 154.
  • the aligned conductive posts 132 in each of the dies 150, 152 and 154 are electrically and mechanically connected through the use of a suitable flux and light pressure applied while heating the assembly to the melting point of the top and bottom pads 144 and 148 on each die 150, 152 and 154. This forms a secure connection between all of the die 150, 152 and 154.
  • the multiple layer integrated circuit device is formed of individual integrated circuit dies having through extending electrically conductive posts.
  • the fabrication method of the present invention enables a thin integrated circuit die to be formed without cracking or other damage and, at the same time, provides the through extending electrically conductive posts for ease of stacking multiple layers into a high density, small volume integrated circuit device.
  • the fabrication method of the present invention provides a single thin layer integrated circuit which is strong and rigid enough to remain intact during the various processing steps employed to form an integrated circuit or semiconductor device thereon while at the same time eliminating the expensive and time consuming post processing methodology previously employed to form conductive posts in semiconductor dies.

Abstract

A multi-layer integrated circuit and method utilizes a substrate (10) covered by a dissolvable material layer (18), which is coated by a protective material layer (20). Electrically conductive posts (26, 28), an electrically insulating material layer (32), and a semiconductive material layer (36) are formed on the protective material layer. The electrically conductive posts extend through the electrically insulating material layer and the semiconductive material layer. An IC is formed in the top surface of the semiconductive material layer. Upper conductive pads (42) are formed on the exposed ends of the conductive posts. A low temperature melting point material (44) is disposed on the conductive pads. The substrate, dissolvable material layer and protective material layer are used to support each thin integrated circuit layer during fabrication and are subsequently removed to interconnect the stack.

Description

SEMICONDUCTOR WAFER FOR LAMINATION APPLICATIONS CROSS REFERENCE TO CO-PENDING APPLICATION
This application is a continuation-in-part of co-pending United States Patent Application Serial No. 07/933,359, filed August 20, 1992, in the name of David F. Capps and Tyra M. Szwarc, and entitled "MULTI-LAYER INTEGRATED CIRCUIT AND FABRICATION METHOD".
BACKGROUND OF THE INVENTION Field of the Invention:
The present invention relates, in general, to integrated circuits and, more particularly, to multi¬ layer or three-dimensional integrated circuits and fabrication methods therefor. Description of the Art:
Integrated circuits are typically fabricated from semiconductor wafers cut from a large crystal. The semiconductor wafers are generally from 200μm to 400μm thick and are of uniform crystalline material. The actual integrated circuit is formed on the top surface of the wafer by various doping, oxide, metal deposition and etching processes. Since this provides a basic two- dimensional structure, the overall density of such integrated circuits per given area is limited. In an effort to overcome this density limit and to produce devices having greater densities, it has been proposed to form semiconductor devices using multiple layers of integrated circuitry. The greatest obstacle in the production of multiple layers of integrated circuits is the solid semiconductor crystalline wafer. Vertical conductive paths are required for multiple layer construction. A solid wafer is not directly usable without expensive and time consuming processing methods used to produce the required vertical conductive paths. Many ways of forming such multiple layer, integrated circuit devices are known, the most common of which is through the use of alternating layers of insulating material and semiconductive material applied to the semiconductive wafer through various deposition processes, such as chemical vapor deposition or molecular beam epitaxy. Through these processes, multiple layers may be formed with circuits integrated in each semiconductor layer. The main drawback of these processes is that as multiple layers of integrated circuits are formed, the number of defective devices increases. In the basic two-dimensional integrated circuit, each integrated circuit formed on a wafer is tested and the defective circuits discarded. However, in multiple layer integrated circuit devices, as the number of layers increases, a point will be reached at which the number of usable devices approaches zero. Thus, it would be desirable to provide a semiconductor wafer that could include the vertical conductive paths where required for multiple layer applications. It would also be desirable to provide a semiconductor wafer which has a very thin but mechanically stable structure. It would also be desirable to provide a semiconductor wafer, suitable for multiple layer applications, that can be used with conventional, existing processing techniques and equipment. It would be desirable to provide an integrated circuit having thin layers of semiconductive material constructed in such a manner so as to duplicate the vertical conductive paths used in multiple layer integrated circuit devices as well as the multiple layer surfaces for circuit integration. It would also be desirable to provide a multiple layer integrated circuit device which can be made according to a fabrication process which increases the yield of usable individual integrated circuits. It would also be desirable to provide a multiple layer integrated circuit device which can be constructed using conventional, existing processing techniques and equipment. SUMMARY OF THE INVENTION In one embodiment, the present invention is a multiple layer integrated circuit and method of fabrication therefor. In one embodiment, the multiple layer integrated circuit is formed by the method comprising the steps of:
(1) forming a dissolvable material layer on a top surface of a planar substrate; (2) disposing a protective material layer over the dissolvable material layer, with the protective material layer extending over the side edges of the dissolvable material layer;
(3) forming at least one electrically conductive post on and extending away from the protective material layer, the electrically conductive post having a predetermined length;
(4) disposing an electrically insulating material layer over the protective material layer and all of the exterior surface of the at least one electrically conductive post;
(5) disposing a semiconductor material over the electrically insulating material layer to at least a top end of the electrically conductive post such that a substantially planar top surface is formed exposing the top end of the at least one electrically conductive post;
(6) forming an electronic or integrated circuit in the top surface of the semiconductive material layer; (7) forming an electrically conductive pad on the top end of the at least one electrically conductive post;
(8) separating the substrate, the dissolvable material layer and the protective material layer from the electrically insulating material layer; and (9) electrically connecting the electrically conductive posts and pads of a plurality of like formed integrated circuits in a stack.
Preferably, the method also includes the step of forming an enlarged base pad in the insulating material layer which supports each electrically conductive post.
The step of separating the substrate from the integrated circuit layer preferably includes the steps of removing a peripheral flange formed on the protective material layer which surrounds the side edge of the dissolvable material layer to expose the dissolvable material layer to water or other solution to dissolve the material layer and thereby separate the substrate from the protective material layer. The protective material layer is then removed by placing the integrated circuit layer in a suitable acid.
A low temperature melting point layer may be disposed on the exposed ends of the conductive posts to provide electrical and mechanical interconnection between a plurality of like formed integrated circuit dies which are arranged in a stacked alignment. The individual conductive traces on each integrated circuit in each layer are connected to the conductive posts to provide electrical circuit interconnection between the various integrated circuit layers.
The multi-layer integrated circuit laminate of the present invention is ideally suited for use in a high density memory application. In such an application, the memory cells or matrix are formed in a predetermined size on each integrated circuit layer. The memory cells are preferably concentrated towards the center of each integrated circuit die so as to provide peripheral space for the electrically conductive posts extending through each die to adjacent dies. The drivers, sensors and decode logic associated with a typical memory device are preferably formed in a separate integrated circuit layer which is supported by a substrate providing heat sink characteristics. The active circuit is preferably concentrated in the center of the integrated circuit die with the electrically conductive posts being concentrically arranged in rows surrounding the active circuit. Peripheral conductive pads may also be formed on this integrated circuit layer and connected to the posts, the active circuit or to provide connections to other integrated circuits. In another embodiment, a semiconductor wafer suitable for lamination applications is formed by a process comprising the steps of:
(1) forming a core in the shape of the wafer to be produced from a dissolvable material; (2) optionally, forming at least one electrically conductive post on and extending away from the dissolvable material core, the electrically conductive post having a predetermined length;
(3) form a layer of electrical insulating material over all surfaces of the dissolvable material core and the optional electrically conductive posts;
(4) disposing one or more semiconductor material layers on the electrical insulating material covering the optional electrically conductive posts and a top surface of the core or, in the case where no conductive posts are constructed, the surface of the core designated as the top surface; and
(5) grinding and polishing an exposed surface of the semiconductive material layer so to expose a top end of each of the optional electrically conductive posts or, in the case where no conductive posts are present, to produce a smooth surface, suitable for integrated circuit fabrication. An electronic or integrated circuit is then formed in the semiconductor material layer 138 by normal fabrication processes.
After the fabrication of integrated circuits or other semiconductor devices in the semiconductive material layer 138, the method preferably also includes the post- processing steps of:
(1) grinding a back surface layer and a side edge of the semiconductor material to expose the dissolvable material core;
(2) mounting the wafer in a holding fixture;
(3) dissolving the core material; and
(4) seperating the individual integrated circuits or semiconductor devices from the wafer. Preferably the electrically conductive posts also include an enlarged base pad which supports each electrically conductive post.
The step of forming the electrically insulating layer over all surfaces of the dissolvable material core and the optional electrically conductive posts preferably includes the step of oxidizing a thin semiconductor material layer disposed on the core and/or the conductive posts to form an insulating layer around the optional electrically conductive posts and over the exposed surface of the core.
The step of dissolving the core material includes the step of inserting the wafer into a dissolving solution, such as a suitable acid.
A low temperature melting point layer of electrically conductive metal or other suitable alloy may be disposed on the exposed ends of the electrically conductive posts during or after the formation of integrated circuits or other semiconductor devices. The purpose of low temperature melting point layer is to provide electrical and mechanical interconnection between a plurality of like formed integrated circuit dies which are arranged in a stacked alignment. The individual conductive traces on each integrated circuit or semiconductor device are connected to the conductive posts to provide electrical circuit interconnection between the various semiconductor layers arranged in a stacked alignment. The wafer of the present invention is ideally suited for use in fabricating and constructing multiple layer integrated circuit assemblies.
The multiple layer integrated circuit device and fabrication method therefor of the present invention uniquely enables a thin integrated circuit die to be formed with planar surfaces thereby avoiding surface distortion problems and enabling electrically conductive posts to be formed in and through each integrated circuit layer or die. The dies may be easily interconnected in an aligned stack by electrically and mechanically interconnecting the conductive posts extending through each die thereby providing electrical connection between each integrated circuit layer. This enables a high density integrated circuit device to be formed. The fabrication method of the present invention provides a single thin layer integrated circuit which is strong and rigid enough to remain intact during the various processing steps employed to form an integrated circuit or semiconductor device thereon while at the same time eliminating the expensive and time consuming post processing methodology previously employed to form conductive posts in semiconductor dies.
BRIEF DESCRIPTION OF THE DRAWING The various features, advantages and other uses of the present invention will become more apparent by referring to the following detailed description and drawing in which:
Figures 1-8 are partial, cross sectional views showing the sequential steps of one embodiment of the present fabrication method for forming an integrated circuit laminate or layer for use in a multiple layer integrated circuit device;
Figure 9 is a partial, cross sectional view showing the multiple layer stacking of individual integrated circuit laminates made according to the present method and shown in Figures 1-8; Figure 10 is a plan elevational view of an alternate embodiment of a multiple layer integrated circuit device constructed in accordance with the teachings of the present invention; 5 Figure 11 is a partial, cross sectional view showing the mounting of heat conductors in the integrated circuit device shown in Figure 10;
Figure 12 is a plan view of a base integrated circuit layer of a multiple layer integrated circuit 10 device devised for memory applications;
Figure 13 is a cross sectional view generally taken along line 13-13 in Figure 12;
Figure 14 is a partial, cross sectional view showing a multiple layer integrated circuit device 15 including the layer shown in Figures 12 and 13;
Figures 15-19 are partial, cross sectional views showing the sequential steps in a second fabrication method of the present invention used to form a single thin wafer; 20. Figures 20, 21, 23 and 24 are partial, cross sectional views showing the sequential steps in the post¬ processing of the wafer shown in Figure 19 after the semiconductor circuit has been formed in the top surface of the wafer; 25 Figure 22 is a partial, cross sectional view of the holding fixture and wafer used for handling the wafer in Figure 21; and
Figure 25 is a partial, cross sectional view of like formed integrated circuit dies arranged in a stacked 30 alignment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Figures 1-8 depict the various steps of the fabrication method of the present invention used in forming individual integrated circuit lamination layers 35 which are subsequently stacked into a multiple layer integrated circuit device. It should be understood that Figure 1-8 depict a portion of an overall structure having a predetermined size and shape, such as a generally disc-like shape, which will include a number of identical integrated circuits, as described hereafter. A substrate 10 is initially provided in a predetermined shape, such as a disc-like shape. The substrate 10 is formed of a suitable rigid material, such as a ceramic, for example only. The substrate 10 has opposed top and bottom surfaces 12 and 14, respectively, and a peripheral side edge 16. The overall size of the substrate 10 could be that of a conventional semiconductor wafer used to form a plurality of integrated circuits.
In a first step, a thin layer 18 of a dissolvable material is formed or disposed by conventional means on the top surface 12 of the substrate 10. The layer 18 may be applied by coating, for example, the top surface 12 of the substrate 10. The dissolvable material forming the layer 18 may be any suitable material which is dissolvable in water or other weak solutions and has a melting point above 1200°C. For example, the dissolvable material can be calcium aluminate or other suitable material. It is also important that the dissolvable material will not react with the semiconductor material used in the present method, as described hereafter.
Next, a protective material layer 20 is formed or disposed over the top of the dissolvable material layer 18. The protective material layer 20 is preferably formed of a metallic material, such as chromium, and is applied in such a way so as to form a smooth, flat surface for the formation of an epitaxial layer thereover, as described hereafter. As shown in Figure 1, the protective material layer 20 is formed with an outer peripheral flange 22 which extends over the entire side edge of the dissolvable material layer 18 and a portion of the side edge 16 of the substrate 10 to completely seal the dissolvable material layer 18 therein. In a next step, a plurality of electrically conductive posts are formed on the top surface 24 of the protective material layer 20. Although only two posts 26 and 28 are shown in Figures 2-8, it will be understood that any number of such posts can be formed according to the present invention. Further, the dimensional relationship and position of each of the posts 26, 28, etc., is preferably identical for each individual integrated circuit formed on the substrate 10 so as to enable stacking of such integrated circuits as described hereafter.
In a preferred embodiment, the conductive posts 26 and 28 are each provided with an enlarged base pad 30 which is formed on the top surface 24 of the protective material layer 20 by several layers of metal deposition. The base pad 30 has a larger cross sectional area than the conductive posts 26 and 28 and forms a mechanical lip so as to prevent the unintentional removal of metal from the conductive posts 26 and 28. The individual conductive posts 26 and 28 are then formed by several layers of metal deposition on each base pad 30. The base pads 30 and the conductive posts 26 and 28 may be formed of any suitable electrically conductive material, such as electrically conductive metals or alloys thereof. Suitable refractory metals, such as titanium, may also be employed. Further, the base pads 30 and the conductive posts 26 and 28 may be formed by any suitable means, such as metal deposition, electro-plating, etc. The conductive posts 26 and 28 may be of any shape, such as circular or square, in cross section and may be relatively thin, approximately 5μm in thickness. However, each post 26 and 28 must extend vertically for the minimum anticipated thickness of the semiconductive material layer which is approximately 25μm to 50μm.
As shown in Figure 3, in the next step of the present fabrication method, an electrically insulating material layer 32 is disposed or deposited over the entire surface of the protective material layer 20 and the entire peripheral surface of the base pads 30 and the electrically conductive posts 26 and 28. The insulating material layer 30 also extends over the side lip 22 of the protective material layer 20 and into contact with the substrate 10.
The insulating material layer 32 may be formed of any suitable electrically insulating material, such as, for example, calcium fluoride. Oxidized silicon may also be used. The semiconductor materials are then oxidized to form the insulating layer 32 which will ultimately become the bottom surface of each integrated circuit layer or laminate. The insulating material layer 32 provides insulation between the various integrated circuit layers, as described hereafter, and also reduces migration of contaminants throughout the various layers.
Next, a layer 36 of semiconductive material is deposited by suitable means over the insulating material layer 32 and slightly in excess of the height of the conductive posts 26 and 28, as shown in Figure 4. The semiconductive material layer 36 may be formed by any suitable method, such as molecular beam epitaxy or chemical vapor deposition. Once the semiconductive material layer 36 has been formed to the desired thickness, the top surface is polished or otherwise treated to remove excess material and to create a flat surface 38, shown in Figure 5, which exposes the top ends 40 of each conductive post 26, 28, etc. In a next step, the desired circuit is then integrated into the top surface 38 of the semiconductive material layer 36 by standard processes and the required conductive surface traces 39 formed and extending from the integrated circuit to the conductive posts 26, 28, etc.
Next, an upper electrically conductive pad 42 is then formed on the exposed top surface 40 of each conductive post 26, 28, etc. The conductive pads 42 may be formed during the formation of the integrated circuit in the semiconductive material layer 36 as part of the conductive surface traces 39. For example only, each upper conductive pad 42 may be formed of a suitable conductive material, such as a metal, i.e., aluminum, etc. As shown in Figure 7, a low melting point, electrically conductive material layer or pad 44 is then formed or disposed on each upper conductive pad 42. Tin, zinc, or alloys thereof may be used to form the low melting point electrically conductive material layer 44 or pads so as to provide both electrical and mechanical connection between the integrated circuit laminations or layers. This completes the formation of the integrated circuits on a single wafer. Each circuit may then be tested, with defective circuits being marked in a normal manner for non-use.
In the next step of the present method, the semiconductive layer 36 with its bottom located insulating material layer 32 is separated from the substrate 10 by first removing, such as by grinding, the peripheral edges of the semiconductive material layer 36, the insulating material layer 32 and, more importantly, the peripheral side lip 22 and adjacent flange of insulating material from the peripheral side edge of the substrate 10, as shown in Figure 7. To facilitate the holding of the relatively thin integrated circuit layer or laminate, a holding means 50 in the form of a vacuum holder is employed to prevent cracking or other damage to the integrated circuit laminate and to provide an easy means for handling the integrated circuit laminate during further processing.
By way of example only, a holding means 50, as shown in Figure 8, may include a suitably formed holder 52 having a shape slightly larger than the integrated circuit wafer. The holder 52 is formed with an annular rim 54 which surrounds and extends below a portion of the side edge of the semiconductive material layer 36 on the wafer. An annular seal ring 56 is supported in the annular rim 54 of the holder 52 and seals against the peripheral edge of the semiconductive layer 36 and a porous support member 58 mounted in the holder 52. The porous support 58 is formed of any suitable porous material so as to enable a vacuum source applied to an inlet 60 formed in the holder 52 to be used to releasably attach the integrated circuit wafer to the holder 52.
Next, the holder 52 is used to place the integrated circuit laminate in water or other solution to dissolve the dissolvable material layer 18. Since the peripheral side edge of the dissolvable material layer 18 has been exposed by the grinding or removal step described above, water or any other solution readily dissolves the dissolvable material layer 18 to separate the substrate 10 from the protective material layer 20. The integrated circuit laminate is then placed via the holder 52 into a suitable solution, such as dilute sulfuric acid, so as to remove the protective material layer 20 from the insulating material layer 32 thereby exposing the insulating material layer 32 which forms the bottom surface of the integrated circuit laminate. The holder 52 is then separated from the integrated circuit lamination or layer by releasing the vacuum therefrom. The individual integrated circuit dies in the laminate are then separated from each other, with the defective dies being discarded. This results in a number of identical, fully operational integrated circuit dies which then may be interconnected into a multiple layer or three-dimensional stack of integrated circuit dies as shown in Figure 9.
A thin coating 62 of a low temperature melding point metal or alloy, similar to the material used to form the pads 44, as described above, is applied to bases 30 on the integrated circuit die 70, shown in Figure 9, which forms the bottommost lamination of the multiple layer integrated circuit device.
As shown in Figure 9, a base layer 74 which may be another integrated circuit, a printed circuit board, etc., is provided with conductive base pads 76 which are aligned with and engage the low melting point pads 62 connected to the base pads 30 of the conductive posts 26 and 28 in the lowermost integrated circuit die 70. A number of like integrated circuit dies, shown by reference numbers 72 and 73, are stacked on the integrated circuit die 70, with the bottom base pads 30 of each integrated circuit die 72 and 73 being aligned with the corresponding upper conductive pads 42 of the adjacent die to form a stacked, aligned arrangement of integrated circuit dies 70, 72, 73, etc. It will be understood that the number of individual dies interconnected in a stack may be varied to suit the requirements of a particular application. A topmost layer 76 of a protective insulating material may be applied over the uppermost integrated circuit die 73 to complete the multiple layer integrated circuit device made according to the teachings of the present invention.
A multiple layer integrated circuit device constructed in accordance with the teachings of the above-described method affords several advantages over previously devised multiple layer integrated circuits. A multiple layer integrated circuit device of the present invention has a high density and, further, has a high yield since defective integrated circuits in each layer or laminate are removed before the integrated circuits are arranged in a vertical, stacked arrangement. Further, since each laminated layer is fabricated separately, collective surface distortion which occurs when multiple layers are deposited onto underlying layers is avoided. As such, each integrated circuit layer has its own flat base surface and is not dependent upon the surface geometry of the underlying layers. Another embodiment of the present invention is shown in Figure 10 and 11. In this embodiment. Figure 10 depicts a plan view of the top layer or laminate of an integrated circuit device fabricated according to the present invention, with the top protective insulating layer 76 being removed for clarity. As shown in Figure 10, the electrically conductive posts, of which only two posts 26 and 28 are numbered, are provided in a predetermined pattern about the periphery of the integrated circuit die forming the laminate 73. Each conductive post is vertically aligned with a corresponding post in an underlying integrated circuit laminate, as described above. The conductive traces from the integrated circuit formed in the semiconductive material 36 are connected to the posts 26, 28, etc., in a normal manner.
Due to the stacked nature of multiple integrated circuit laminates, it may be necessary to remove heat from certain types of electronic circuits formed in the laminates from the interior of the multiple layer integrated circuit device. As such, it is desirable to construct at least some and, preferably, all of the individual integrated circuit dies 70, 72, 73, etc. , with open, unused areas in the semiconductive material layers 36. At least one and, preferably, a plurality of apertures 80 are formed in each integrated circuit layer 73 in the open, unused areas thereof. A thin layer of an electrically insulating material is deposited on the exposed surface bounding each aperture 80. Four of such apertures 80 are shown in Figure 10 by way of example only.
Such apertures 80 may be formed by any suitable means, such as by use of a laser. The apertures 80 in each integrated circuit die 70, 72, 73, etc., are aligned so as to form one or more openings extending continuously through all of the dies or layers in the multiple layer integrated circuit device. A heat conductive means, such as a metallic rod 84, extends through each coaxial alignment of apertures 80 in the multi-layer integrated circuit stack as shown in Figure 11. Each conductive rod 84 is insulated from the surrounding integrated circuit by the insulating layer 82, but is capable of transmitting heat generated by the integrated circuits from each layer outward from each die or layer of the multi-layer integrated circuit stack to the top of the stack. An enlarged heat conductive plate 86 may be disposed below the lowermost integrated circuit layer 70 and connected to the plurality of heat conductive rods 84, as shown in Figure 11.
Figures 12 and 13 depict another embodiment of the present multiple layer integrated circuit which is designed specifically for a high density memory application. This application utilizes individual integrated circuit layers or dies constructed in accordance with the fabrication method described above. The memory circuits can be formed by any conventional crystalline or amorphic process and may be either volatile or non-volatile in nature. Further, the semiconductive material used to form each layer may be any silicon based semiconductor, as well as germanium or GaAs material.
Since the drivers, sensors, and decode logic associated with a memory device are known to generate substantial quantities of heat, according to this embodiment of the present invention, the integrated circuitry forming the drivers, sensors and memory decode logic are concentrated in a central area 102 in a semiconductive layer 96. Surface traces 98 extend outward from the peripheral edges of the integrated circuit to electrically conductive pads 100 mounted on the top surface of the base layer 96. According to the present invention, the conductive pads 100 are arranged in concentric rows, as shown in Figure 12, for purposes which will be described in greater detail hereafter. Conductive traces 94 are also are formed between the semiconductive material layer 96 and a base layer 92 and extend through the layer 96 to the drivers, etc.. The base layer 92 acts as a substrate and may be formed of any suitable material which provides high heat transmissibility. The base 92 thus acts as a heat sink for the active circuit elements formed in the semiconductive material layer 96. Further, as shown in Figure 12, a plurality of peripherally mounted terminals 104 may also be formed on the base layer 92 and connected to the drivers, decode and sensor circuitry in the layer 96 by the traces 94 to other external integrated circuits. Individual integrated circuit layers containing the desired number of memory cells or circuits are stacked in a vertical arrangement over the base layer and semiconductive material layer all denoted generally by reference number 90 as shown in Figures 13 and 14. Each of the integrated circuit layers 104, 106, 108 and 110 are formed as described above with through extending electrically conductive posts 112. Each of the posts 112 are electrically connected to one of the conductive pads 100 on the base layer 90 by means of a low temperature melting point material layer similar to the layer 44 described above. Surface conductive traces 114 extend between each of the electrically conductive posts 112 in each layer to the active circuit elements of the integrated circuit formed in each layer. It will be understood that the number of individual layers 104, 106, 108 and 110 may be varied depending upon the requirements of a particular application. In addition, the size or density of memory cells in each layer may also be varied. Another feature of this embodiment of the present invention is shown in Figure 14. As the electrically conductive posts 112 are arranged in concentric rows on the base layer 90 and through the succeeding stacked layers 104, 106, 108 and 110, certain rows of electrically conductive posts may be eliminated from uppermost layers or, even if present, not electrically connected to the next adjacent upper layer as such connections may not be necessary.
Another fabrication process according to the present invention is shown in Figures 15-23. This process is particularly devised for forming a thin, single layer integrated circuit. A core or substrate
130, as shown in Figure 15, is first formed in a size and shape compatible with existing semiconductor wafers. Preferably, the core or substrate 130 is formed of a dissolvable material such as chromium. This material provides a rigid substrate; while being easily dissolvable so as to be easily removed from the other material layers forming semiconductor wafer.
As shown in Figure 16, the next step of the present method is optional and involves the formation of at least one and preferably a plurality of electrically conductive posts 132. A base pad 134 of a larger cross sectional area than the post 132 is formed on the core or substrate 130 by normal metal deposition and etching. The conductive posts 132 are also formed by metal deposition and etching from a suitable material, such as tungsten. The conductive posts 132 may be of any shape, such as circular or square, in cross section and may be relatively thin, i.e., approximately five μ in thickness. Further, each conductive post 132 extends vertically from the base pad 134 for a suitable distance equal to the minimum anticipated thickness of the semiconductive material layer which will be applied thereover.
It will be understood that the number and dimensional relationship of each of the posts 132 may be varied as desired to suit the particular application of the integrated circuit or semiconductor device to be formed on the core 130. Preferably, for multiple stacking applications, the arrangement of the conductive posts 132 is identical for each integrated circuit die formed on the wafer. Next, as shown in Figure 17, the entire top, bottom and side surfaces of the core 130, the base pads 134 and the electrically conductive posts 132 are covered with a thin layer of a protective, electrically insulating material, such as polysilicon 136. The polysilicon layer 136 is then oxidized to form an electrically insulating layer 136 which surrounds all of the exterior surfaces of the core 130, the base pads 134 and the electrically conductive posts 132.
As shown in Figure 18, the next step in the present method involves the application of one or more layers of a single cyrstalline silicon material 138 over the electrically insulating layer 136 covering the top surface of the core 130, the base pads 134 and the electrically conductive posts 132. The semiconductive material layer 138 completely surrounds all of the exterior surfaces of the electrically conductive posts 132 and the base pads 134. The single crystalline material forming the layer 138 is deposited by suitable means, such as molecular beam epitaxy, chemical vapor deposition, or other suitable processes. Further, the depth of deposition of the layer 138 exceeds the height of the vertical electrically conductive posts 132 and can vary, for example, from five μm to 10 μm.
Next, as shown in Figure 19, the top surface 140 of the semiconductive material layer 138 is ground and polished to expose the top ends 142 of the electrically conductive posts 132. The exposed top end 142 of the conductive posts 132 thus forms a finished surface for the fabrication of integrated circuits or other semiconductor devices. In a construction where conductive posts are not used, the grinding and polishing step forms a smooth surface on the semiconductor layer suitable for integrated circuit formation.
As shown in Figure 20, a top electrically conductive pad 144 is then formed on the top ends 142 of each of the electrically conductive posts 132. The pads 144 may be formed by suitable means, such as metal deposition and etching, for example only. The conductive pads 144 are formed of a suitable electrically conductive, low temperature melting point material to provide electrical connections through the conductive posts 132 on one integrated circuit die to conductive posts on additional semiconductor dies in different layers of a multiple stack of such integrated circuit dies. Such pads 144 are not needed in the case where the integrated circuit dies formed on the wafer are to be used in a non-stacked application.
In the next step of the present method, as shown in Figure 21, the bottom surface 131 of the core or substrate 130 and the peripheral side edge 133 of the core 130 are ground to remove the insulating layer 136 previously disposed thereover and to expose the bottom surface 131 and the side edge surface 133 of the core 130. This essentially forms the wafer 145.
The wafer 145 is then placed in a suitable holding fixture 50 as shown in Figure 22. The holding fixture 50 is the same as that described above and shown in Figure 8. The top surface of the pads 144 is placed against a porous ceramic support 58 mounted in the holder 50. The holder 50 and the wafer 145 mounted therein is then inserted into a dissolving solution such as an acid, i.e., sulfuric acid, to dissolve and remove the core 130, as shown in Figure 23. This forms a bottom surface 146 after the core 130 has been dissolved and removed from the wafer 145 in which the base pads 134 are exposed and surrounded by the insulating material layer 136.
Bottom pads 148 formed of a low temperature melting point, electrically conductive material are then attached to each of the base pads 134 by suitable metal deposition and etching, for example as shown in Figure 24. The bottom pads 148 provide an electrical and mechanical bond between like formed integrated circuits or other semiconductor devices formed on like wafers 145.
The wafer 145 can then be cut by laser or other suitable means to separate each die from the complete wafer 145.
As shown in Figure 25, individual dies, only three of which are shown and denoted by reference numbers 150, 152 and 154, may then be assembled in a stacked arrangement with the individual electrically conductive posts 132 vertically aligned through the stack of dies 150, 152 and 154. The aligned conductive posts 132 in each of the dies 150, 152 and 154 are electrically and mechanically connected through the use of a suitable flux and light pressure applied while heating the assembly to the melting point of the top and bottom pads 144 and 148 on each die 150, 152 and 154. This forms a secure connection between all of the die 150, 152 and 154. In summary, there has been disclosed a unique multiple layer integrated circuit and fabrication method therefor which uniquely provides a high density integrated circuit device which utilizes minimal physical space. The multiple layer integrated circuit device is formed of individual integrated circuit dies having through extending electrically conductive posts. The fabrication method of the present invention enables a thin integrated circuit die to be formed without cracking or other damage and, at the same time, provides the through extending electrically conductive posts for ease of stacking multiple layers into a high density, small volume integrated circuit device. The fabrication method of the present invention provides a single thin layer integrated circuit which is strong and rigid enough to remain intact during the various processing steps employed to form an integrated circuit or semiconductor device thereon while at the same time eliminating the expensive and time consuming post processing methodology previously employed to form conductive posts in semiconductor dies.

Claims

What is Claimed is:
1. A single thin layer integrated circuit device formed by a method comprising the steps of: (1) forming a dissolvable material layer on a top surface of a planar substrate, the dissolvable material layer having opposed top and bottom surfaces and side edges; (2) disposing a protective material layer over the dissolvable material layer, with the protective material layer extending over the side edges of the dissolvable material layer; (3) disposing an electrically insulating material layer over the protective material layer; (4) disposing a semiconductive material over the electrically insulating material on the top surface of the substrate; (5) forming an integrated circuit in the top surface of the semiconductive material layer; and (6) separating the substrate, the dissolvable material layer and the protective material layer from the electrically insulating material layer to form a single thin layer integrated circuit device.
2. The single thin layer integrated circuit device formed by the method of Claim 2 wherein the step of separating further comprises the steps of: exposing at least one of the bottom surface and the side edges of the dissolvable material layer; dissolving the dissolvable material layer to separate the substrate from the protective material layer; and removing the protective layer from the electrically insulating layer to expose the at least one electrically conductive post.
3. The single thin layer integrated circuit device formed by the method of Claim 1 further comprising the step of: before the step of forming the insulating layer, forming at least one electrically conductive post on and extending away from the dissolvable material layer, the electrically conductive post having an exterior surface, a top end, a bottom end and a predetermined length.
4. The single thin layer integrated circuit device formed by the method of Claim 3 further comprising the step of: forming an electrically conductive pad on the top end of the at least one electrically conductive post.
5. A single thin integrated circuit device formed by the method of claim 4 further comprising the steps of: forming an electrically conductive pad on the bottom end of the at least one electrically conductive post; and electrically connecting the at least one electrically conductive post and electrically conductive pads on the top and bottom ends of the electrically conductive post of a plurality of like-formed integrated circuits in a stack.
6. A single thin layer integrated circuit device formed by a method comprising the steps of: (1) forming a substantially planar, dissolvable material layer having a top surface and side edges; (2) disposing a protective material layer over the top surface of the dissolvable material layer, with the protective material layer extending over side edges of the dissolvable material layer; 0 (3) disposing an electrically insulating 1 material layer over the protective material layer; 2 (4) disposing a semiconductive material over 3 the electrically insulating material such that a 4 substantially planar top surface is formed; 5 (5) forming an integrated circuit in the top 6 surface of the semiconductive material layer; 7 (6) exposing at least a portion of the 8 dissolvable material layer; and 9 (7) dissolving the dissolvable material layer 0 to form a single thin layer integrated circuit.
1 7. The single thin layer integrated circuit
2 device formed by the method of Claim 6 further comprising
3 the step of:
4 after forming the dissolvable material layer
5 and before forming the protective material layer thereon,
6 forming at least one electrically conductive post on and
7 extending away from the dissolvable material layer, the 8. electrically conductive post having an exterior surface, 9 opposed top and bottom ends, and a predetermined length; 0 the semiconductive material layer being 1 disposed on the top surface of the protective material 2 layer up to at least the top end of the electrically 3 conductive post.
1 8. A single thin layer integrated circuit
2 device formed by a method comprising the steps of:
3 (1) forming a dissolvable material substrate
4 having a top surface, a bottom surface and side edges;
5 (2) disposing an electrically insulating
6 material layer over all of the top and bottom surfaces
7 and the side edges of the dissolvable material;
8 (3) disposing a semiconductor material over
9 the electrically insulating material on the top surface 0 of the substrate; 11 (4) forming an integrated circuit in the
12 semiconductive material layer;
13 (5) exposing at least the bottom surface of
14 the dissolvable material substrate; and
15 (6) dissolving the substrate to leave a thin
16 layer integrated circuit device.
1 9. The single thin layer integrated circuit
2 device formed by the method of claim 8 further comprising
3 the steps of:
4 before the step of disposing the electrically
5 insulating material layer, forming at least one
6 electrically conductive post on and extending away from
7 the to surface of the dissolvable material substrate, the
8 electrically conductive post having a predetermined
9 length and a top end;
10 disposing the electrically insulating material
11 layer over all of the exterior surface of the dissolvable
12 material and the electrically conductive post; and
13. disposing the semiconductor material over the
14 electrically insulating material on the top surface of
15 the substrate to at least the top end of the electrically
16 conductive post.
1 10. A multiple layer integrated circuit device
2 formed by a method comprising the steps of:
3 (1) forming a dissolvable material substrate
4 having a top surface, a bottom surface and side edges;
5 (2) forming at least one electrically
6 conductive post on and extending away from the
7 dissolvable material substrate, the electrically
8 conductive post having a predetermined length and an
9 exterior surface with top and bottom ends;
10 (3) disposing an electrically insulating
11 material layer over all of the exterior surface of the
12 dissolvable material and the electrically conductive
13 post; (4) disposing a semiconductor material over the electrically insulating material on the top surface of the substrate to at least the top end of the electrically conductive post; (5) forming an integrated circuit in the semiconductive material layer; (6) forming an electrically conductive pad on the top end of the at least one electrically conductive post; (7) exposing at least the bottom surface of the dissolvable material substrate; (8) dissolving the substrate to leave a thin layer integrated circuit device; (9) forming an electrically conductive pad on the top end of the at least one electrically conductive post; and (10) electrically connecting the electrically conductive posts and the pads on the top and bottom ends thereof of a plurality of like formed integrated circuits in a stack.
11. A method of fabricating a multiple layer integrated circuit device comprising the steps of: (1) forming a dissolvable material layer on a top surface of a planar substrate; (2) disposing a protective material layer over the dissolvable material layer, with the protective material layer extending over the side edges of the dissolvable material layer; (3) forming at least one electrically conductive post on and extending away from the protective material layer, the electrically conductive post having a predetermined length; (4) disposing an electrically insulating material layer over the protective material layer and all of the exterior surface of the at least one electrically conductive post; (5) disposing a semiconductor material over the electrically insulating material layer to at least a top end of the electrically conductive post such that a substantially planar top surface is formed exposing the top end of the at least one electrically conductive post; (6) forming an integrated circuit in the top surface of the semiconductive material layer; (7) forming an electrically conductive pad on the top end of the at least one electrically conductive post; (8) separating the substrate, the dissolvable material layer and the protective material layer from the electrically insulating material layer; and (9) electrically connecting the electrically conductive posts and pads of a plurality of like formed integrated circuits in a stack.
12. The method of Claim 11 further comprising the step of: forming an electrically conductive base pad on the protective material layer to support the at least one electrically conductive post thereon.
13. The method of Claim 11 wherein the step of electrically connecting the posts and pads further comprises: applying a layer of a low temperature melting point electrically conductive material onto the electrically conductive pad.
14. The method of Claim 11 wherein the separating step comprises the steps of: removing the portion of the protective material layer from the side edges of the dissolvable material layer to expose the side edges of the dissolvable material layer; and disposing the integrated circuit in a fluid to dissolve and remove the dissolvable material layer from the protective material layer.
15. The method of Claim 14 further comprising the step of removing the protective material layer from the insulating material layer.
16. The method of Claim 11 further comprising the step of forming a plurality of integrated circuits in the semiconductive material layer, each integrated circuit having a plurality of electrically conductive posts extending therethrough arranged in a predetermined positional arrangement with respect to each integrated circuit.
17. The method of Claim 14 further comprising the step of: stacking a plurality of integrated circuits with the conductive pads of each integrated circuit connected to the conductive posts of adjacent integrated circuits by the low temperature melting point material layer.
18. The method of Claim 17 further comprising the steps of: forming at least one aperture through each semiconductive material layer and insulating material layer; and forming an insulating material layer on the exposed. surfaces of at least the semiconductive material layer bounding the at least one aperture.
19. The method of Claim 18 further comprising the steps of: disposing a heat conductive member in aligned apertures in a plurality of stacked integrated circuits to conduct heat away from each integrated circuit.
20. The method of Claim 17 further comprising the step of: forming a plurality of spaced apertures through each semiconductive material layer and insulating material layer; and disposing a heat conductive member in aligned apertures in the plurality of integrated circuits to conduct heat away from each integrated circuit.
21. A multiple layer integrated circuit device formed by a method comprising the steps of: (1) forming a dissolvable material layer on a top surface of a planar substrate, the dissolvable material layer terminating in side edges; (2) disposing a protective material layer over the dissolvable material layer, with the side edges of the protective material layer extending over the side edges of the dissolvable material layer; (3) forming at least one electrically conductive post on and extending away from the protective material layer, the electrically conductive post having an exterior surface, top and bottom ends, and a predetermined length; (4) disposing an electrically insulating material layer over the protective material layer and all of the exterior surface of the at least one electrically conductive post; (5) disposing a semiconductor material over the electrically insulating material layer to at least a top end of the electrically conductive post such that a substantially planar top surface is formed exposing the top end of the at least one electrically conductive post; (6) forming an integrated circuit in the top surface of the semiconductive material layer; (7) forming an electrically conductive pad on the top end of the at least one electrically conductive post; (8) separating the substrate, the dissolvable material layer and the protective material layer from the electrically insulating material layer; and (9) electrically connecting the electrically conductive posts and pads of a plurality of like formed integrated circuits in a stack.
22. The integrated circuit device of Claim 21 formed by the method further comprising the step of: forming an electrically conductive base pad on the protective material layer to support the at least one electrically conductive post thereon.
23. The integrated circuit device of Claim 21 formed by the method wherein the step of electrically connecting the posts and pads further comprises: applying a layer of a low temperature melting point electrically conductive material onto the electrically conductive pad.
24. The integrated circuit device of Claim 21 formed by the method wherein the separating step comprises the steps of: removing the portion of the protective material layer from the side edges of the dissolvable material layer to expose the side edges of the dissolvable material layer; and disposing the integrated circuit in a fluid to dissolve and remove the dissolvable material layer from the protective material layer.
25. The integrated circuit device of Claim 24 formed by the method further comprising the step of removing the protective material layer from the insulating material layer.
26. The integrated circuit device of Claim 21 formed by the method further comprising the step of forming a plurality of integrated circuits in the semiconductive material layer, each integrated circuit having a plurality of electrically conductive posts extending therethrough arranged in a predetermined positional arrangement with respect to each integrated circuit.
27. The integrated circuit device of Claim 23 formed by the method further comprising the step of: stacking a plurality of integrated circuits in alignment with the conductive pads of each integrated circuit connected to the conductive posts of adjacent integrated circuits by the low temperature melting point material layer.
28. The integrated circuit device of Claim 27 formed by the method further comprising the steps of: forming at least one aperture through each semiconductive material layer and insulating material layer; and forming an insulating material layer on the exposed surfaces of at least the semiconductive material layer bounding the at least one aperture.
29. The integrated circuit device of Claim 28 formed by the method further comprising the steps of: disposing a heat conductive member in aligned apertures in a plurality of stacked integrated circuits to conduct heat away from each integrated circuit.
30. The integrated circuit device of Claim 27 formed by the method further comprising the step of: forming a plurality of spaced apertures through each semiconductive material layer and insulating material layer; and disposing a heat conductive member in aligned apertures in the plurality of integrated circuits to conduct heat away from each integrated circuit.
31. An integrated circuit die comprising: a substantially planar insulating base layer; a plurality of electrically conductive posts formed on and extending from the insulating material layer, a bottom surface of each post extending through and exposed at an end through the insulating material layer; a semiconductive material layer formed on the insulating material layer and surrounding the plurality of electrically conductive posts, a top end of each post being exposed through the semiconductive material layer; an integrated circuit formed in the semiconductive material layer; an upper electrically conductive pad formed on the top end of each electrically conductive post; at least one aperture formed in and extending through the semiconductive material layer and the insulating material layer; and a heat conductive member extending through the aperture to conduct heat away from the integrated circuit formed in the semiconductive material layer.
32. The integrated circuit die of Claim 31 further comprising: a plurality of electrically conductive bases formed in and surrounded by the electrically insulating material layer, each conductive base being electrically connected to and supporting one of the electrically conductive posts.
33. A multiple layer integrated circuit device comprising: a substantially planar insulating base layer; a plurality of electrically conductive posts formed on and extending from the insulating material layer, a bottom surface of each post extending through and exposed at an end through the insulating material layer; a semiconductive material layer formed on the insulating material layer and surrounding the plurality of electrically conductive posts, a top end of each post being exposed through the semiconductive material layer; an integrated circuit formed in the semiconductive material layer; an upper electrically conductive pad formed on the top end of each electrically conductive post; a plurality of like integrated circuit dies arranged in a stack, with each electrically conductive post of each die electrically contacting a like positioned electrically conductive post in adjacent integrated circuit dies; a low temperature melting point material disposed between the ends of electrically conductive posts in adjacent integrated circuit die to mechanically and electrically join the electrically conductive posts of the plurality of integrated circuit dies together after being heated and allowed to cool; at least one aperture formed in and extending through the semiconductive material layer and the insulating material layer of at least certain of the integrated circuit dies; and a heat conductive member extending through the aperture to conduct heat away from the integrated circuit dies.
34. The multiple layer integrated circuit device of Claim 33 wherein the electrically conductive posts in each layer are concentrically arranged about the integrated circuit formed in the semiconductive material layer in each layer.
35. The multiple layer integrated circuit device of Claim 33 further comprising: a heat sink base layer; a semiconductive material layer formed on the base layer; an integrated circuit formed in the semiconductive layer; a plurality of electrically conductive pads formed on the semiconductive material layer and electrically connected to the integrated circuit; and wherein "~ the plurality of like integrated circuit dies are arranged in a stack and electrically connected through the electrically conductive posts to the electrically conductive pads on the base.
36. A multiple layer integrated circuit device formed by a method comprising the steps of: (1) forming a substantially planar dissolvable material layer; (2) forming at least one electrically conductive post on and extending away from the dissolvable material layer, the electrically conductive post having a predetermined length; (3) disposing an electrically insulating material layer over the dissolvable material layer and all of the exterior surface of the at least one electrically conductive post; (4) disposing a semiconductor material over the electrically insulating material layer to at least a top end of the electrically conductive post such that a substantially planar top surface is formed exposing the top end of the at least one electrically conductive post; (5) forming an integrated circuit in the top surface of the semiconductive material layer; (6) forming an electrically conductive pad on the top end of the at least one electrically conductive post; (7) separating the dissolvable material layer from the electrically insulating material layer; and (8) electrically connecting the electrically conductive posts and pads of a plurality of like formed integrated circuits in a stack.
PCT/US1993/007893 1992-08-20 1993-08-20 Semiconductor wafer for lamination applications WO1994005039A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU58357/94A AU5835794A (en) 1992-08-20 1993-08-20 Semiconductor wafer for lamination applications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93335992A 1992-08-20 1992-08-20
US07/933,359 1992-08-20

Publications (1)

Publication Number Publication Date
WO1994005039A1 true WO1994005039A1 (en) 1994-03-03

Family

ID=25463797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/007893 WO1994005039A1 (en) 1992-08-20 1993-08-20 Semiconductor wafer for lamination applications

Country Status (2)

Country Link
AU (1) AU5835794A (en)
WO (1) WO1994005039A1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025982A1 (en) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Contact structure for vertical chip connections
US6090636A (en) * 1998-02-26 2000-07-18 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6150188A (en) * 1998-02-26 2000-11-21 Micron Technology Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6198168B1 (en) * 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6219237B1 (en) 1998-08-31 2001-04-17 Micron Technology, Inc. Structure and method for an electronic assembly
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
US6821802B2 (en) 1998-08-31 2004-11-23 Micron Technology, Inc. Silicon interposer with optical connections
US7101770B2 (en) 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761782A (en) * 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US3787252A (en) * 1968-07-05 1974-01-22 Honeywell Inf Systems Italia Connection means for semiconductor components and integrated circuits
US4225900A (en) * 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
US4231154A (en) * 1979-01-10 1980-11-04 International Business Machines Corporation Electronic package assembly method
US4710798A (en) * 1985-09-10 1987-12-01 Northern Telecom Limited Integrated circuit chip package
US4840923A (en) * 1986-04-30 1989-06-20 International Business Machine Corporation Simultaneous multiple level interconnection process
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787252A (en) * 1968-07-05 1974-01-22 Honeywell Inf Systems Italia Connection means for semiconductor components and integrated circuits
US3761782A (en) * 1971-05-19 1973-09-25 Signetics Corp Semiconductor structure, assembly and method
US4225900A (en) * 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
US4231154A (en) * 1979-01-10 1980-11-04 International Business Machines Corporation Electronic package assembly method
US4710798A (en) * 1985-09-10 1987-12-01 Northern Telecom Limited Integrated circuit chip package
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US4840923A (en) * 1986-04-30 1989-06-20 International Business Machine Corporation Simultaneous multiple level interconnection process
US4930001A (en) * 1989-03-23 1990-05-29 Hughes Aircraft Company Alloy bonded indium bumps and methods of processing same

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5846879A (en) * 1993-05-05 1998-12-08 Siemens Aktiengesellschaft Contact structure for vertical chip connections
WO1994025982A1 (en) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Contact structure for vertical chip connections
US6198168B1 (en) * 1998-01-20 2001-03-06 Micron Technologies, Inc. Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6709978B2 (en) 1998-01-20 2004-03-23 Micron Technology, Inc. Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer
US7547954B2 (en) 1998-02-26 2009-06-16 Micron Technology, Inc. Electronic systems using optical waveguide interconnects formed through a semiconductor wafer
US6150188A (en) * 1998-02-26 2000-11-21 Micron Technology Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6090636A (en) * 1998-02-26 2000-07-18 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US7164156B2 (en) 1998-02-26 2007-01-16 Micron Technology, Inc. Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer
US6995443B2 (en) 1998-02-26 2006-02-07 Micron Technology, Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer
US6995441B2 (en) * 1998-02-26 2006-02-07 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6777715B1 (en) 1998-02-26 2004-08-17 Micron Technology, Inc. Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same
US6526191B1 (en) 1998-02-26 2003-02-25 Micron Technology, Inc. Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same
US6723577B1 (en) 1998-02-26 2004-04-20 Micron Technology, Inc. Method of forming an optical fiber interconnect through a semiconductor wafer
US6219237B1 (en) 1998-08-31 2001-04-17 Micron Technology, Inc. Structure and method for an electronic assembly
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
US6570248B1 (en) 1998-08-31 2003-05-27 Micron Technology, Inc. Structure and method for a high-performance electronic packaging assembly
US6496370B2 (en) 1998-08-31 2002-12-17 Micron Technology, Inc. Structure and method for an electronic assembly
US6821802B2 (en) 1998-08-31 2004-11-23 Micron Technology, Inc. Silicon interposer with optical connections
US7022553B2 (en) 1998-08-31 2006-04-04 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6395630B2 (en) 1998-11-23 2002-05-28 Micron Technology, Inc. Stacked integrated circuits
US6314013B1 (en) 1998-11-23 2001-11-06 Micron Technology, Inc. Stacked integrated circuits
US6122187A (en) * 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US7101770B2 (en) 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections

Also Published As

Publication number Publication date
AU5835794A (en) 1994-03-15

Similar Documents

Publication Publication Date Title
US5432999A (en) Integrated circuit lamination process
JP4906994B2 (en) Method for transferring ultrathin substrate and method for manufacturing multilayer thin film device using the method
US5380681A (en) Three-dimensional multichip package and methods of fabricating
TWI286359B (en) Method for producing wiring substrate
US6624505B2 (en) Packaged integrated circuits and methods of producing thereof
TW577160B (en) Semiconductor device and manufacturing method thereof
US9240392B2 (en) Method for fabricating embedded chips
US6872594B2 (en) Method of fabricating an electronic component
CN101969053B (en) Semiconductor device and manufacturing method thereof
JPH0517708B2 (en)
US7408249B2 (en) Packaged integrated circuits and methods of producing thereof
JP2003501804A (en) Method for vertically integrating electrical components by back contact
JP2013175764A (en) Semiconductor packaging process using through silicon vias
CN101578703A (en) Wafer-level fabrication of lidded chips with electrodeposited dielectric coating
US20150279814A1 (en) Embedded chips
WO1994005039A1 (en) Semiconductor wafer for lamination applications
TW200525707A (en) Semiconductor device and method of manufacturing the same
US5904502A (en) Multiple 3-dimensional semiconductor device processing method and apparatus
CN111554648B (en) Die package and method of forming a die package
JP2796865B2 (en) Manufacturing method of electrical connection member
JP7382110B2 (en) Chip assembly by lamination with rotation
EP1041620A2 (en) Method of transferring ultrathin substrates and application of the method to the manufacture of a multi-layer thin film device
US3456334A (en) Method of producing an array of semiconductor elements
US3421204A (en) Method of producing semiconductor devices
JPS62209845A (en) Semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU CA JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA