WO1994008298A3 - Method for improving scsi operations by actively patching scsi processor instructions - Google Patents

Method for improving scsi operations by actively patching scsi processor instructions Download PDF

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Publication number
WO1994008298A3
WO1994008298A3 PCT/US1993/009363 US9309363W WO9408298A3 WO 1994008298 A3 WO1994008298 A3 WO 1994008298A3 US 9309363 W US9309363 W US 9309363W WO 9408298 A3 WO9408298 A3 WO 9408298A3
Authority
WO
WIPO (PCT)
Prior art keywords
scsi
operations
device driver
processor
jump
Prior art date
Application number
PCT/US1993/009363
Other languages
French (fr)
Other versions
WO1994008298A2 (en
Inventor
William C. Galloway
Original Assignee
Compaq Computer Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corporation filed Critical Compaq Computer Corporation
Priority to AU51690/93A priority Critical patent/AU5169093A/en
Publication of WO1994008298A2 publication Critical patent/WO1994008298A2/en
Publication of WO1994008298A3 publication Critical patent/WO1994008298A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level. This approach allows removal of all special operation conditional branching from the SCSI processor, greatly speeding up operations.
PCT/US1993/009363 1992-10-02 1993-09-29 Method for improving scsi operations by actively patching scsi processor instructions WO1994008298A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU51690/93A AU5169093A (en) 1992-10-02 1993-09-29 Method for improving scsi operations by actively patching scsi processor instructions

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US95584592A 1992-10-02 1992-10-02
US955,845 1992-10-02

Publications (2)

Publication Number Publication Date
WO1994008298A2 WO1994008298A2 (en) 1994-04-14
WO1994008298A3 true WO1994008298A3 (en) 1994-07-21

Family

ID=25497439

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1993/009363 WO1994008298A2 (en) 1992-10-02 1993-09-29 Method for improving scsi operations by actively patching scsi processor instructions

Country Status (3)

Country Link
US (1) US5463743A (en)
AU (1) AU5169093A (en)
WO (1) WO1994008298A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6629894A (en) * 1993-05-07 1994-12-12 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US5634081A (en) * 1994-03-01 1997-05-27 Adaptec, Inc. System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a first SCSI data transfer command that is not autotransfer
US6076141A (en) * 1996-01-24 2000-06-13 Sun Microsytems, Inc. Look-up switch accelerator and method of operating same
US5860156A (en) * 1996-07-26 1999-01-12 Western Digital Corporation Method for implementing an indexed jump table
US5835788A (en) * 1996-09-18 1998-11-10 Electronics For Imaging System for transferring input/output data independently through an input/output bus interface in response to programmable instructions stored in a program memory
US6112278A (en) * 1996-09-30 2000-08-29 Lsi Logic Corporation Method to store initiator information for SCSI data transfer
US6157963A (en) * 1998-03-24 2000-12-05 Lsi Logic Corp. System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients
JP4111472B2 (en) 1998-05-15 2008-07-02 キヤノン株式会社 COMMUNICATION CONTROL METHOD AND DEVICE AND COMMUNICATION SYSTEM
US6557064B1 (en) 1999-02-19 2003-04-29 Hewlett-Packard Development Company Set up time adjust
US6675244B1 (en) 1999-02-19 2004-01-06 Hewlett-Packard Development Company, L.P. SCSI data rate speed determination
US6546497B1 (en) 1999-02-19 2003-04-08 Hewlett-Packard Development Company, L.P. SCSI clock stretching
US6493785B1 (en) 1999-02-19 2002-12-10 Compaq Information Technologies Group, L.P. Communication mode between SCSI devices
US6636921B1 (en) 1999-02-19 2003-10-21 Hewlett-Packard Development Company, Lp. SCSI repeater circuit with SCSI address translation and enable
EP1390856B2 (en) * 2001-04-26 2020-07-22 The Boeing Company System and method for preloading a bus controller with command schedule
US20080181254A1 (en) * 2007-01-25 2008-07-31 Inventec Corporation Data transmission method
KR102395541B1 (en) * 2015-07-09 2022-05-11 에스케이하이닉스 주식회사 Memory control unit and data storage device including the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6394352A (en) * 1986-10-09 1988-04-25 Fujitsu Ltd System for protecting data in ram

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204951A (en) * 1989-10-02 1993-04-20 International Business Machines Corporation Apparatus and method for improving the communication efficiency between a host processor and peripheral devices connected by an scsi bus
JP2545482B2 (en) * 1990-03-15 1996-10-16 富士通株式会社 Interface device transfer parameter setting method
US5347638A (en) * 1991-04-15 1994-09-13 Seagate Technology, Inc. Method and apparatus for reloading microinstruction code to a SCSI sequencer
KR960001750B1 (en) * 1991-07-30 1996-02-05 Hitachi Ltd Scsi controller and the method for use on an information

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6394352A (en) * 1986-10-09 1988-04-25 Fujitsu Ltd System for protecting data in ram

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Dynamic Patch via Invalid Operations", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 15, no. 4, September 1972 (1972-09-01), NEW YORK US, pages 1248 - 1250 *
NOBLE: "Avoid Decisions", COMPUTERS IN PHYSICS, vol. 5, no. 4, July 1991 (1991-07-01), NEW YORK, US, pages 386 - 395 *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 331 (P - 755) 7 September 1988 (1988-09-07) *
SALE: "The Implementation of Case Statements in Pascal", SOFTWARE PRACTICE & EXPERIENCE, vol. 11, 19 February 1981 (1981-02-19), CHICHESTER GB, pages 929 - 942, XP002040457, DOI: doi:10.1002/spe.4380110905 *

Also Published As

Publication number Publication date
AU5169093A (en) 1994-04-26
WO1994008298A2 (en) 1994-04-14
US5463743A (en) 1995-10-31

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