WO1995001628A1 - Real time active addressing display device and method utilizing fast walsh transform circuit - Google Patents

Abstract

The device and method provide active-addressing drive signals foran LCD by utilizing an efficient implementation of Walsh functions. By implementation of a technique for determining fast Walsh transformations, real time active-addressing of the drive signals are provided by determining random access memory (RAM) addresses for sending preselected portions of the digital image data (PPDIDs) to a plurality of RAMs (106, 108, 110), and controlling simultaneous parallel input/output of data to/from the RAMs and a fast Walsh transform circuit (FWTC 102) such that fast Walsh transforms (FWTs) are performed on input digital image data. For example, active-addressing drive signals for one-half of a 240 by 640 column sized LCD may be determined in real time. Thus, two of the devices of the present invention may be utilized to provide a system for real time active-addressing for a typical visual graphics array (VGA) LCD.

Description

  
 



   REAL TIME ACTIVE ADDRESSING DISPLAY DEVICE AND
 METHOD UTILIZING FAST WALSH TRANSFORM CIRCUIT
 Field of the Invention
 The present invention relates to flat-panel display addressing techniques, and more particularly, to active addressing liquid-crystal display driving techniques.



   Background
 Liquid crystals have been known since the   1880s.   



  However, the effects of electric fields on liquid crystals were not effectively studied until the 1960s. Then, liquid crystal displays   (LCDs)    were developed based on the electric fieldgenerated rearrangement of the liquid crystal molecules, for example, twisted-nematic, field-effect displays. Electric field controls were typically grids that controlled activation of grid intersections, wherein each intersection controlled illumination of a dot, i.e., a pixel, in a dot matrix display of an image.



   Active Addressing displays were developed which use a different method of driving the rows and columns of a passive matricx LCD panel to control each pixel. Instead of using a single high-voltage select pulse for the rows, and applying that pulse to each row individually in sequence, the rows are driven by orthogonal binary sequences where all of the rows are driven simultaneously. The determination of the column drive signal for an active addressed display requires a large number of computations.  



   However, performance of an active addressing column drive signal determination during an actual time in which related physical processes transpire (i.e., real time active addressing), such that results of the signal determination are also used in guiding the physical processes, has not been accomplished. Thus, there is a need for a device and method for achieving real time active addressing for flat panel displays.



   Summary of the Invention
 A device and method are set forth for determining real time active addressing of drive signals for a plurality of preselected portions of digital image data (PPDIDs). The device includes a fast Walsh transform circuit (FWTC), operably coupled to each of a plurality of random access memories (RAMs), for performing a preselected fast Walsh transform (FWT) on each respective PPDID to provide FWT data for the PPDID, the plurality of RAMs, each RAM for receiving at least one of: a PPDID and FWT data, and an address unit, operably coupled to each of the RAMs and to the FWTC, for determining random access memory (RAM) addresses for the data and for controlling parallel input/output of data to/from the RAMs and the FWTC, such that active addressing drive signal data is provided in real time.



   The method includes the steps of determining random access memory (RAM) addresses for sending the PPDIDs to a plurality of RAMs and controlling simultaneous parallel input/output of data to/from the RAMs and a fast Walsh transform circuit (FWTC) such that fast Walsh transforms (FWTs) are performed on the PPDIDs using the FWTC and FWT data are provided for active addressing drive in real time. The  method may be selected to further implement steps of the operations of the units set forth for the device.



   Brief Descriptions of the Drawings
 FIG. 1 is a block diagram of a device in accordance with the present invention.



   FIG. 2 is a block diagram showing more detail of one embodiment of a device in accordance with the present invention.



   FIG. 3 is a block diagram of of a radix-4 butterfly unit in accordance with the present invention.



   FIG. 4 is a block diagram of one embodiment of a system in accordance with the present invention.



   FIG. 5 is a flow chart of a method in accordance with the present invention.



   Detailed Description of a Preferred Embodiment
 Active-addressing is a technique in which a writing voltage for the rows of an LCD panel are orthogonal binary sequences and the column drive signals for a liquid crystal display is computed by adding together the product of the all the row sequences multiplied by the pixel values for the corresponding rows. Previous methods of active-addressing of
LCD drive signals have limited the performance of the display because of the time required for computing the active addressing column drive signal. Walsh functions are a set of orthonormal functions that are considered of particular  practical importance because they can easily be generated by digital logic circuitry and because multiplication of these functions may easily be generated by a polarity-reversing switch.



   The present invention incorporates an architecture that utilizes Walsh functions to facilitate active-addressing for a
LCD. The device of the present invention implements real time determination of active-addressing drive signals for one-half of a 240 row by 640 column sized LCD. Thus, two of the devices of the present invention may be utilized to provide a system for real time active-addressing for drive signals for a typical Video Graphics Array (VGA) LCD.



   FIG. 1, numeral 100, sets forth a block diagram of a device for determining real time active-addressing of drive signals for a plurality of preselected portions of digital image data (PPDIDs) in accordance with the present invention. The device comprises a fast Walsh transform circuit (FWTC)(102), a plurality of memory units (104, 106, 108, 110, ...), and an address unit (112). The FWTC (102) is operably coupled to each of the memory units (104, 106, 108, 110, ...) and performs a preselected fast Walsh transform on each PPDID to provide
FWT data for the   PPDlDs.    Typically, PPDIDs are digital image column or row data and the device outputs active-addressing drive signal data that is utilized to provide drive signals for columns/rows of a liquid crystal display. Typically, the addressing unit includes a clock for synchronous operation.



   Drive signal computation is typically determined by the matrix multiplication:    G=RI    where R is a matrix of r columns of orthogonal pseudorandom maximum length shift register sequences of binary sequences   (+1 and -1) of 255 elements, I is an r row by 640 column matrix of an image to be displayed on the half of the LCD, and
G is a 255 row by 640 column matrix of drive signal waveforms.

  In the present invention an architecture is provided in which the matrix multiplication has been simplified by:
 writing matrix R as a transformed Walsh matrix,
 R =   T1 W    T2, where   Tland    T2 are permutation matrices having only one nonzero entry per column equal to one of:

   +1 and -1, and W is a
Walsh matrix of orthogonal Walsh sequences, and
 substituting the transformed Walsh matrix R into the drive signal addressing matrix multiplication:
 G =   Ti    [W    [T2      I]]   
Thus, a column is read from the image matrix I in a permuted order (in accordance with T2   I    ) and then is multiplied by W to provide a result (W (T2   I)).    The result (W   (T2 I))    is permuted with   T1    to provide a resulting column of the matrix G, which is written to an output buffer to provide column drive signals. In the present invention W is factored utilizing a Fast Walsh Transform (FWT) technique in correspondence with a complex exponential matrix Fast Fourier
Transform factoring technique. 

  The value r is selected to be either 240, i.e., where there is no gray scale correction, or 241, i.e., where there is gray scale correction. Walsh functions are described more fully in "Appiications of Walsh and Related Functions", by K.G. Beauchamp, Academic Press, 1984.



   The fast Walsh transform circuit (FWTC) (102) is operably coupled to each of the memory units (104, 106, 108, 110, ...) and is utilized for performing a preselected fast Walsh transform (FWT) on each respective PPDID to provide FWT data for the respective   PPDlDs.    In one embodiment (see FIG. 2), the plurality of memory units (104, 106, 108, 110, ...) includes a  first memory unit (104) that includes a holding random access memory (RAM) (R, 220) (that is coupled for receiving FWT data in accordance with the pipeline described below. Each of the remaining memory units (106, 108, 110, ...), i.e., dual purpose memory units, typically has a multiplexer (224, 228, 232, ...) operably coupled to a RAM (A, 222; B, 226; C,   230; ...) for    determining whether that memory receives PPDID input or FWT data.

  Each dual purpose memory unit RAM is coupled to receive, at separate times, at least one of: a PPDID and FWT data. The address unit (112) is operably coupled to each of the
RAMs of the memory units and to the FWTC and is utilized for determining random access memory (RAM) addresses for the data and for controlling parallel input/output of data to/from the RAMs and the FWTC such that active addressing drive signal data is provided in real time. Thus, the RAMs include a holding RAM (i.e., in the first memory unit) for storing intermediate FWT data for each PPDID and a plurality of dual purpose memory RAMs, each of which is utilized alternately for storing a PPDID and for storing the completed FWT data of the PPDID.



   In one implementation, an output buffer is also included for storing the active addressing drive signal data until the drive signals addressed are accumulated for driving one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD). Here the clock typically operates at 4x9.792 MHz.



   The address unit (112) simultaneously provides for controlling parallel (pipeline) operations of determining FWT data for a first PPDID from a first RAM (A, 222), reading of a second PPDID into a second RAM (B, 226), and writing of previously completed FWT data from a third RAM (C, 230) for a third PPDID to the output buffer (234), wherein the previously completed FWT data of the output buffer is a portion of active  addressing drive signal data for the digital image data. The set of simultaneous operations above are repeated until the active addressing drive signal data for drive signals for driving one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) have been output to the output buffer.



   Thus, where an input digital image data buffer is utilized in a 256 butterfly operation system, the address unit (112) determines all addresses needed by the input buffer, the RAMs of the memory units, and the output buffer. In addition the address unit (112) determines four addresses in a last innermost loop for the internal memories for the FWT, written in pseudocode as:
 for (k=1; k < 256; k=k*4)
 for (I=0; 1 < 256; I=1+4*k)
 for (m=0; m < k; m=m+1)
 for (n=0; n < 4*k; n=n+k)
 address=l+m+n;
These four addresses are used to access iocations of the RAM source memories to obtain the four inputs needed for the butterfly operation and are also used as the addressed needed to store the result of the butterfly alternately into the holding
RAM of the first memory unit and the RAMs of the dual purpose memory units.

  Also, the address unit (112) schedules all internal operations of the device, including controlling sources and destinations of digital image data, clocking the FWT butterfly registers, controlling gray scale and direct current correction circuits (where selected), and generating control signals needed for external input buffer and output buffer
RAMs.



   FIG. 2, numeral 200, is a block diagram showing more detail of one embodiment of a device in accordance with the present invention. The FWTC typically includes a radix-4  butterfly determining unit (214, 216, 218). Each PPDID contains n bits of data, n being an integer. Where n is not a multiple of four, zeros are added such that n becomes a multiple of four. In one implementation, n equals 256. Here, each of the dual purpose memory units (106, 108, 110) contains a RAM (222, 226, 230) that is 256 by 12. Thus, the radix-4 butterfly determining unit performs the Fast Walsh
Transform technique for further factoring W and includes four butterfly input registers (a, b, c, and d) (214), eight addsubtract units (a+b, a-b, c+d, c-d) and   {[(a+b)+(c+d)],    [(a-b)+(cd)], [(a+b)-(c+d)], and [(a-b)-(c-d)]} (216), and four butterfly output registers (e, f, g, and h) (218).



   FIG. 3, numeral 300, is a block diagram of of a radix-4 butterfly unit (214, 216, 218) in accordance with the present invention. Where n = 256, the four butterfly input registers (a, b, c, and d) (302, 310, 318, 326) are each operably coupled to receive 64 bits of data of the first PPDID, in a parallel pipeline fashion, as set forth above. A first unit (304) of the four add-subtract units (a+b, a-b, c+d, c-d) is operably coupled to receive input from registers a (302) and b (310) for determining a value a+b that is stored in register e (308). A second unit (312) of the four add-subtract units is operably coupled to receive input from registers a (302) and b (310) for determining a value a-b that is stored in register f (316).

  A third unit (320) of the four add-subtract units is operably coupled to receive input from c (318) and d (326) for determining a value a-b that is stored in register g (324). A fourth unit (328) of the add-subtract units is operably coupled to receive input from c (318) and d (326), for determining a value c-d that is stored in register h (332). The add-subtract units are typically arithmetic logic units (ALUs) which operate as is known to those skilled in the art to determine the values set forth above. Thus, no further description of the addsubtract units utilized herein is provided.  



   Four further add-subtract units {[(a+b)+(c+d)], [(a-b)+(cd)], [(a+b)-(c+d)], and [(a-b)-(c-d)]}, typically arithmetic logic units, are utilized to determine the values a+b+c+d, a-b+c-d, a+b-c-d, and a-b-c+d, respectively. A fifth unit is operably coupled to receive and sum input from the first unit (a+b) and the third unit (c+d) to determine the value a+b+c+d. A sixth unit is operably coupled to receive and sum input from the second unit (a-b) and the fourth unit (c-d) to determine the value a-b+c-d. A seventh unit is operably coupled to receive input from the first unit (a+b) and the third unit (c+d) and to subtract to determine the value a+b-c-d. An eighth unit is operably coupled to receive input from the second unit (a-b) and the fourth unit (c-d) and to subtract to determine the value a-b-c+d.



   The techniques of discrete-time Fourier analysis are extremely useful in the study of discrete-time signals and systems. Specifically, the input and output of a discrete-time system may be expressed as linear combinations of complex exponentials, making the coefficients in the expression for the output expressible in terms of the coefficients of the linear combination representing the input. A discrete Fourier transform (DFT) is an algorithm used for determining the output coefficients. A Fast Fourier Transform (FFT) is an algorithm for computing the DFT with a very reduced number of multiplications. As is known in the art, the FFT utilizes a combining operation that requires N complex multiplications, which, when represented by a flow diagram, is commonly called the "butterfly" because of its appearance.

 

   In the present invention, for n=256, four butterfly output registers (e, f, g, and h) are operably coupled to receive the values a+b+c+d, a-b+c-d, a+b-c-d, and a-b-c+d, respectively, for, in determining FWT data for a first PPDID from a first  
RAM, determining a butterfly on the data from the first RAM 64 times to provide 64 output values. Each output value is then read out one at a time to the memory of the holding RAM (in the first memory unit) wherein, for determination of 64 next FWT butterflies, the holding RAM becomes a source of the next 64
FWT butterflies, the data in the holding RAM is read to the FWT circuitry in an altered order, and the first RAM becomes a destination of said butterflies for the completed FWT data.



  The altered order corresponds to an order obtained by permutation of the 64 values with matrix T1.



   Data must be read into the real time FWTC at the rate of at least 240*640*72 or 11.1 million memory reads per second.



  In an implementation where there are four memory reads/writes per butterfly and 256 butterflies per FWT, the rate at which data is read from and written to internal memory by a FWT processor is 4*256*640*72 or 47.2 million reads per second. These speeds are realizable for modern IC technology.



   Thus, for example, in the RAM activity pipeline in the implementation illustrated in FIG. 2, where A represents a first column of digital image data, B represents a second column of digital image data, C represents a third column of digital image data, and R represents utilization of the holding memory RAM (as described above for the butterfly computations), the operations of reading digital image data into a dual purpose memory RAM, fast Walsh transforming the data, and writing out the data from a dual purpose memory
RAM, are described by the table below:

  :
 RAM ACTIVITY PIPELINE
EMI10.1     


<tb>   READ <SEP> IN <SEP> DATA <SEP> A <SEP> B <SEP> C <SEP> A <SEP> B <SEP> C <SEP> A <SEP> B <SEP> C    <SEP> 
<tb>   Fwr    <SEP>    O,R <SEP>     <SEP> A,R <SEP> B,R <SEP> C,R <SEP> A,R <SEP> B,R <SEP> C,R <SEP> A,R <SEP> B,R
<tb> WRITE <SEP> OUT <SEP> DATA <SEP> B <SEP> C <SEP> A <SEP> B <SEP> C <SEP> A <SEP> B <SEP> C <SEP> A
<tb>   
Each column of digital image data requires 256 radix-4 butterfly computations.



   Where selected, a correction factor unit (204) is operably coupled to at least the plurality of memory units (106, 108, 110, ...) that receive input digital image data and the FWT circuitry (213), for, in parallel with inputting digital image data to the RAMs (222, 226, 230, ...) of the memory units (106, 108, 110, ...), determining a gray scale correction factor
V and appending the factor to the digital image data that is subsequently stored as PPDIDs in preselected RAMs (222, 226, 230, ...). That is, where each column of image data consists of 240 words of up to eight bits, the correction factor, if used, is then appended to the column of image data as the 241st word.



   The correction factor unit (204) determines
EMI11.1     
 where V equals the correction factor and where I represents each of n words, n an integer. Thus, the correction factor unit (204) includes a squaring unit (206), a correction factor add-subtract unit (208), a feedback register (210), and a square root unit (212). Typically, while the PPDID is being read into the dual purpose memory units (106, 108, 110, ...), the correction factor unit (204) determines the correction factor and appends the correction factor to the
PPDID. The squaring unit (206), typically a read-only memory (ROM) look-up table, is operably coupled to receive preselected digital image data and provides a squared value for each of the n digital image data, 12n. Typically,   2402    n   21,    n being an integer.

  The correction factor add-subtract unit (208) is operably coupled to receive each squared value (12n) and a feedback value, for subtracting the squared value from the feedback value. Thus, for a PPDID having 240 words, the  subtraction is
EMI12.1     
 for 240 iterations, to provide iterative correction outputs that are utilized as feedback values. For a 240 PPDID input the feedback register (210) is preloaded with a value 240. In addition, the feedback register (210) is operably coupled to receive the correction outputs (feedback values) of the correction factor add-subtract unit (208) and to the square root unit (212) and iteratively provides a feedback value for each of 240 iterative subtractions of the correction factor add-subtract unit.

  The square root unit (212), typically a ROM look-up table, is operably coupled to the feedback register (210), for providing a square root value of a 240th feedback value after 240 subtractions,
EMI12.2     

V is the gray scale correction factor for appending to the digital image data that is subsequently stored as PPDIDs in preselected RAMs.



   Where pseudorandom sequences for column drive signals for the digital image data input are 255 bits long (i.e., have 128 +1 entries and 127 -1 entries), direct current (DC) correction is needed such that zero DC values are obtained for column signals. To provide DC corrections an inversion unit is operably coupled to receive columns of image data, for randomly inverting the values of rows of each column of image data and appending -1 to every column of an original matrix of columns of orthogonal pseudorandom binary sequences for digital image data.



   FIG. 4, numeral 400, is a block diagram of one embodiment of a system in accordance with the present invention. In the system a display processor (402) is utilized  for determining real time active addressing of drive signals for raster video data for at least a 240 row by 640 column liquid crystal display (LCD). The data has been apportioned into a plurality of portions of digital image data (PPDIDs). The display processor includes two active-addressing signal devices (404, 406).

  Each active-addressing signal device includes at least three first dual-ported dynamic random access memory units (FIRST VRAMs) (408, 410, 412; 414, 416, 418), a first permuted inversion unit (FIRST PERM INV UNIT) (420; 422), a fast Walsh transform circuit (FWT Circuit) (424; 426), a second permuted inversion unit (SECOND PERM INV
UNIT) (428; 430), at least three second dual-ported dynamic random access memory units (SECOND VRAMS) (432, 434, 436; 438, 440, 442), a multiplexer (444; 446), and a video digital to analog converter (VIDEO DAC) (448; 450).



   Each VRAM of the at least three first dual-ported dynamic random access memory units (FIRST VRAMs) (408, 410, 412; 414, 416, 418) is operably coupled to receive, in parallel, preselected   PPDlDs.    Typically, VRAMs are dualported variations of dynamic RAM (DRAM) memory chips that are made specifically for video display purposes. The first permuted inversion unit (FIRST PERM INV UNIT) (420; 422) is operably coupled to each of the plurality of FIRST VRAMs (408, 410, 412; 414, 416, 418), for mapping addresses of the preselected PPDIDs to first permuted addresses as described above. 

  The fast Walsh transform circuit (FWT Circuit, or alternately, FWTC) (424; 426) is operably coupled to the FIRST
PERM INV UNIT (420; 422), for providing control signals to at least the 240 LCD rows and for performing fast Walsh transforms on the first permuted addresses to provide fast
Walsh transform (FWT) data. The second permuted inversion unit (SECOND PERM INV UNIT) (428; 430) is operably coupled to the FWTC (424; 426), for mapping the FWT data to second permuted addresses as described above.

  The at least three  second dual-ported dynamic random access memory units (SECOND VRAMS) (432, 434, 436; 438, 440, 442) are each operably coupled to receive (separately), in parallel, the second permuted addresses for selected   PPDlDs,    for providing buffer memory for storing the second permuted addresses until signal addressing data for at least the 640 columns has been accumulated in the buffer memory. The multiplexer (444; 446) is operably coupled for receiving and combining the accumulated signal addressing data. The video digital to analog converter (448; 450) is operably coupled for receiving the combined accumulated signal addressing data and converts the combined accumulated signal addressing (digital) data to analog active-addressing drive signals for at least the 640
LCD columns of 240 rows of a 480 row by 640 column LCD panel.

  Clearly, the operation of the two devices of the display processor is in accordance with the above description.



   FIG. 5, numeral 500, is a flow chart of a method for determining real time active addressing of drive signals in a liquid crystal display for a plurality of preselected portions of digital image data (PPDIDs) in accordance with the present invention. The method includes the steps of determining RAM addresses (502) for sending the PPDIDs to a plurality of RAMs and controlling simultaneous parallel input/output of data (504) to/from the RAMs and a fast Walsh transform circuit (FWTC) such that fast Walsh transforms (FWTs) are performed on the PPDIDs using the FWTC and FWT data are provided for active addressing drive signal in real time.



   In addition, the active addressingdrive signal data is typically stored in an output buffer. Generally, the method steps are implemented for each of two halves of digital image data, drive signal data is provided for each half, and the drive signal data for each half is utilized to drive one-half (240 rows by 640 columns) of a video graphics array (VGA) sized  liquid crystal display (LCD). The underlying basis for the determination of the drive signal is described above.

  The step of controlling parallel input/output of data to/from the RAMs and the FWTC such that active addressing drive signal data is provided in real time typically includes controlling simultaneous parallel (pipeline) operations of: (1) determining
FWT data for a first PPDID from a first RAM, (2) reading of a second PPDID into a second RAM, and (3) writing of previously completed FWT data from a third PPDID to an output buffer, wherein the previously completed FWT data of the output buffer is a portion of active addressing drive signal data for the digital image data. The operations are repeated until until the active addressing drive signal data for drive signals for driving one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) have been output to the output buffer.



   Thus, the method may be selected to include the steps of addressing a holding RAM for storing intermediate FWT data for each PPDID, addressing a plurality of RAMs for alternately storing a PPDID and storing the completed FWT data of the
PPDID, and addressing a drive signal buffer for storing the completed FWT data for the PPDIDs for the digital image data, where the operations controlled by the steps are accomplished according to a pipeline technique as described above. Again, typically the PPDIDs are digital image column data.



   The step of determining FWT data for a first PPDID from a first RAM by the FWTC generally includes the step of determining a radix-4 butterfly. Thus, each PPDID comprises n (n an integer, zeros being added where n is other than a multiple of 4 such that n plus added zeros is a multiple of 4) bits of data.  



   Where n plus any added zeros equals 256, the step of determining a radix-4 butterfly includes: (1) utilizing four butterfly input registers (a, b, c, and d) to receive 64 bits of data of the first PPDID, (2) determining values for a+b, a-b, c+d, and c-d, respectively utilizing four add-subtract units (a+b, a-b, c+d, c-d), where a first unit receives input from registers a and b, a second unit receives input from registers a and b, a third unit receives input from c and d, and a fourth unit receives input from c and d, respectively, (3) determining values for (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, utilizing four further add-subtract units   ([(a+b)+(c+d)],    [(a-b)+(c-d)], [(a+b)-(c+d)], and [(a-b)-(c-d)]}, where a fifth unit receives input from the first unit and the third unit,

   a sixth unit receives input from the second unit and the fourth unit, a seventh unit receives input from the first unit and the third unit, and an eighth unit receives input from the second unit and the fourth unit, and (4) utilizing four butterfly output registers (e, f, g, and h) that receive the values (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, for, in determining FWT data for a first PPDID from a first RAM, determining a butterfly on the 4 words of data from the first RAM 64 times to provide 64 sets of 4 words of output values, each output value being read out one at a time to memory of a holding RAM wherein, for determination of 64 next FWT butterflies, the holding RAM becomes a source of the next 64 FWT butterflies, the data in the holding RAM is read to the FWT circuitry in an altered order,

   and the memory of the first RAM becomes a destination of said butterflies for the completed FWT data.



  The altered order corresponds to an order obtained by permutation with matrix T1, as described above.



   In correspondence with the operation of the device, the method may be selected to include a step of determining a gray scale correction factor and appending the factor to the digital  image data that is subsequently stored as PPDIDs in preselected RAMs. Determining a gray scale correction factor includes the steps of:

   (1) providing a squared value for the digital image data,   12n,      1S    n  < 240, n being an integer, (2) subtracting the squared value from a feedback value (a first feedback value being 240), i.e.,
EMI17.1     
 to provide a correction output, (3) providing a feedback value, being the correction output
EMI17.2     
 for the subtraction in step (2), (4) repeating steps (1)-(3) until 240 iterations of steps 28A-28C have been completed, and (5) providing a square root value of the 240th feedback   value   
EMI17.3     
 being the gray scale correction factor for appending to the digital image data that is input into preselected RAMs.

 

   In addition, where rows of the matrix W are all ones, for a row position providing for direct current (DC) correction for a digital image column drive signal, the method may be selected to include the step of: (1) dividing completed FWT data at the row position by a bit length of the pseudorandom binary sequences utilized to provide a quotient, (2) subtracting the quotient from all other FWT data for the column to provide DC-corrected column drive signal data, and (3) storing the DC-corrected column drive signal drive signal data in the output buffer. Alternatively, for DC correction, the method may be selected to include the steps of randomly inverting the values of rows of each column of image data and appending -1 to every column of an original matrix of columns of orthogonal pseudorandom binary sequences for digital image data.  

 

   Although various embodiments are described above, it will be obvious to those skilled in the art that many alterations and modifications may be made without departing from the invention. Accordingly, it is intended that all such alterations and modifications be included within the spirit and scope of the invention as defined in the appended claims.



   I claim: 

Claims

1. A device for real time determination of active addressing drive signals for a plurality of preselected portions of digital image data (PPDIDs), comprising: 1 A) a fast Walsh transform circuit (FWTC), operably coupled to each of a plurality of memory means, for performing a preselected fast Walsh transform (FWT) on each respective PPDID to provide FWT data for the PPDID, 1B) the plurality of memory means, a first memory means comprising a random access memory (RAM) and the remaining memory means each having a multiplexer operably coupled to a RAM, such that every RAM receives at least one of:

a PPDID and FWT data, and 1C) an address unit, operably coupled to each of the RAMs of the plurality of memory means and to the FWTC, for determining random access memory (RAM) addresses for the data and for controlling parallel input/output of data to/from the RAMs and the FWTC such that active addressing drive signal data is provided in real time.

2. The device of claim 1 further including an output buffer for storing the active addressing drive signal data wherein the drive signals are utilized to drive one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) and wherein the drive signals are determined by the following matrix multiplications: G = R I where: R is a matrix of r columns of orthogonal pseudorandom maximum length shift register sequences of binary sequences (+1 and -1) of 255 elements, I is an r row by 640 column matrix of an image to be displayed on the half of the LCD, and G is a 255 row by 640 column matrix of drive signal waveforms, and the matrix multiplication has been simplified by: 2A) writing matrix R as a transformed Walsh matrix, R = Ti W T2, where:

: Tland T2 are permutation matrices having only one nonzero entry per column equal to one of: + 1 and -1, and W is a Walsh matrix of orthogonal Walsh sequences, and 2B) substituting the transformed Walsh matrix R into the drive signal addressing matrix multiplication: G = Ti [W [T2 I]] where:

: a column is read from the image matrix I in a permuted order (in accordance with T2 I) and then is multiplied by a column of W to provide a result (W (T2 .1)), and the result (W (T2 I)) is permuted with Ti to provide a resulting matrix G, which is written to the output buffer to provide column drive signals, and wherein W is factored utilizing a Fast Walsh Transform (FWT) technique in correspondence with a complex exponential matrix Fast Fourier Transform factoring technique.

3. The device of claim 2 wherein at least one of 3A-3D: 3A) further including a correction factor unit, operably coupled to at least the first RAM, the second RAM, the third RAM, a holding RAM, and the FWT circuitry, for, in parallel with inputting digital image data to the plurality of RAMs, determining a gray scale correction factor and appending the factor to the digital image data that is subsequently stored as PPDIDs in preselected RAMs; 3B) the address unit provides for simultaneously:

: 3B1) controlling parallel (pipeline) operations of determining FWT data for a first PPDID from a first RAM, 3B2) reading of a second PPDID into a second RAM, and 3B3) writing of previously completed FWT data from a from a third RAM for a third PPDID to the output buffer, wherein the previously completed FWT data of the output buffer is a portion of active addressing drive signal data for the digital image data, and continuing the set of simultaneous operations 3B13B3 until the active addressing drive signal data for drive signals for driving one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) have been output to the output buffer; 3C) r equals one of:

: 240 (without gray scale correction) and 241 (with gray scale correction), and, where selected, further including an inversion means, operably coupled to receive columns of image data, for randomly inverting the values of rows of each column of image data and appending -1 to every column of an original matrix of columns of orthogonal pseudorandom binary sequences for digital image data;

and 3D) wherein the FWTC comprises a radix-4 butterfly determining means, and, where selected, wherein each PPDID comprises n (n an integer, zeros being added where n is other than a multiple of 4 such that n plus added zeros is a multiple of 4) bits of data, and, where selected, wherein n plus added zeros, if any, equals 256 and the radix-4 butterfly determining means performs the Fast Walsh Transform technique for further factoring W and comprises:

: 3D1) four butterfly input registers (a, b, c, and d) each operably coupled to receive 64 bits of data of the first PPDID, 3D2) four add-subtract units (a+b, a-b, c+d, c-d), a first unit being operably coupled to receive input from registers a and b, a second unit being operably coupled to receive input from registers a and b, a third unit being operably coupled to receive input from c and d, and a fourth unit being operably coupled to receive input from c and d, respectively, for determining values for a+b, a-b, c+d, and c-d, respectively, 3D3) four further add-subtract units {[(a+b)+(c+d)], [(a-b)+(c-d)), [(a+b)-(c+d)], and [(a-b)-(c-d)]}, a fifth unit being operably coupled to receive input from the first unit and the third unit, a sixth unit being operabiy coupled to receive input from the second unit and the fourth unit,

a seventh unit being operably coupled to receive input from the first unit and the third unit, an eighth unit being operably coupled to receive input from the second unit and the fourth unit, for determining values for (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, 3D4) four butterfly output registers (e, f, g, and h), operably coupled to receive the values (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, for, in determining FWT data for a first PPDID from a first RAM, determining a butterfly on the data from the first RAM 64 times to provide 256 output values, each output value being read out one at a time to memory of a holding RAM wherein, for determination of 64 next FWT butterflies, the holding RAM becomes a source of the next 64 FWT butterflies, the data in the holding RAM is read to the FWT circuitry in an altered order,

and the memory of the first RAM becomes a destination of said butterflies for the completed FWT data, and, where selected, wherein the altered order corresponds to an order obtained by permutation with matrix T1.

4. The device of claim 1 wherein at least one of 4A-4D: 4A) the plurality of RAMs includes a holding RAM for storing intermediate FWT data for each PPDID and a plurality of RAMs each of which is utilized alternately for storing a PPDID and for storing the completed FWT. data of the PPDID; 4B) wherein the PPDIDs are digital image column data; 4C) wherein the PPDIDs are digital image row data; and 4D) wherein the active addressing drive signal data is utilized to provide drive signals for one of: columns and rows of a liquid crystal display.

5. A method for real time determination of active addressing drive signals in a liquid crystal display for a plurality of preselected portions of digital image data (PPDIDs), comprising the steps of: 5A) determining random access memory (RAM) addresses for sending the PPDIDs to a plurality of RAMs, and 5B) controlling simultaneous parallel input/output of data to/from the RAMs and a fast Walsh transform circuit (FWTC) such that fast Walsh transforms (FWTs) are performed on the PPDIDs using the FWTC and FWT data are provided for active addressing drive signal addressing in real time.

6. The method of claim 16 wherein at least one of 6A-6G: 6A) further including storing the active addressing drive signal data in an output buffer, then utilizing the drive signal data to drive one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) and determining the drive signals by the following matrix multiplications: G= R-I where: R is a matrix of r columns of orthogonal pseudorandom maximum length shift register sequences of binary sequences (+1 and -1) of 255 elements, I is an r row by 640 column matrix of an image to be displayed on the half of the LCD, and G is a 255 row by 640 column matrix of drive signal waveforms, and the matrix multiplication has been simplified by: 6awl) writing matrix R as a transformed Walsh matrix, R = Ti W T2, where:

: Tland T2 are permutation matrices having only one nonzero entry per column equal to one of: + 1 and - 1, and W is a Walsh matrix of orthogonal Walsh sequences, and 6A2) substituting the transformed Walsh matrix R into the drive signal matrix multiplication: G = Ti [W [T2 I]] where:

: a column is read from the image matrix I in a permuted order (in accordance with T2 I ) and then is multiplied by a column of W to provide a result (W (T2 I)), and the result (W (T2 I)) is permuted with Tl to provide a resulting matrix G, which is written to an output buffer to provide column drive signals, and wherein W is factored utilizing a Fast Walsh Transform (FWT) technique in correspondence with a complex exponential matrix Fast Fourier Transform factoring technique, and, where selected, wherein r equals one of:

: 240 (without gray scale correction) and 241 (with gray scale correction); 6B) including the steps of addressing a holding RAM for storing intermediate FWT data for each PPDID, addressing a plurality of RAMs for alternately storing a PPDID and storing the completed FWT data of the PPDID, and addressing a drive signal buffer for storing the completed FWT data for the PPDIDs for the digital image data such that the operations controlled by the steps are performed by a pipeline technique; 6C) wherein the step of controlling parallel input/output of data to/from the RAMs and the FWTC such that active addressing drive signal data is provided in real time includes 6C1) controlling simultaneous parallel (pipeline) operations of:

: 6C1a) determining of FWT data for a first PPDID from a first RAM, 6C1b) reading of a second PPDID into a second RAM, 6C1c) writing of previously completed FWT data from a from a third RAM for a third PPDID to an output buffer, wherein the previously completed FWT data of the output buffer is a portion of active addressing drive signal data for the digital image data, and 6C2) repeating operations until until the active addressing drive signal data for drive signals for driving onehalf (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) have been output to the output buffer; 6D) wherein the PPDIDs are digital image column data; 6E) wherein the PPDIDs are digital image row data;

; 6F) further including determining a gray scale correction factor and appending the factor to the digital image data that is subsequently stored as PPDIDs in preselected RAMs, and, where selected, wherein determining a gray scale correction factor includes the steps of: 6F1) providing a squared value for the digital image data, 12n, 2401n 21, n being an integer, 6F2) subtracting the squared value from a feedback value (a first feedback value being 240), i.e., EMI27.1 to provide a correction output, 6F3) providing a feedback value,

being the correction output EMI27.2 for the subtraction in step 28B, 6F4) repeating steps 6F1-6F3 until 240 iterations of steps 6F1-6F3 have been completed, 6F5) providing a square root value of the 240th feedback value EMI27.3 being the gray scale correction factor for appending to the digital image data that is input into preselected RAMs; and 6G) further including the steps of randomly inverting the values of rows of each column of image data and appending -1 to every column of an original matrix of columns of orthogonal pseudorandom binary sequences for digital image data.

7. The method of claim 5 wherein the determining of FWT data for a first PPDID from a first RAM by the FWTC includes the step of determining a radix-4 butterfly, and where selected, wherein each PPDID comprises n (n an integer, zeros being added where n is other than a multiple of 4 such that n plus added zeros is a multiple of 4) bits of data, and, where selected, wherein n plus any added zeros equals 256 and the step of determining a radix-4 butterfly includes:

: 7A) utilizing four butterfly input registers (a, b, c, and d) to receive 64 bits of data of the first PPDID, 7B) determining values for a+b, a-b, c+d, and c-d, respectively utilizing four add-subtract units (a+b, a-b, c+d, c-d), where a first unit receives input from registers a and b, a second unit receives input from registers a and b, a third unit receives input from c and d, and a fourth unit receives input from c and d, respectively, 7C) determining values for (a+b)+(c+d), (a-b)+(cd), (a+b)-(c+d), and (a-b)-(c-d), respectively, utilizing four further add-subtract units {[(a+b)+(c+d)], [(a-b)+(c-d)], [(a+b) (c+d)], and [(a-b)-(c-d)]}, where a fifth unit receives input from the first unit and the third unit, a sixth unit receives input from the second unit and the fourth unit, a seventh unit receives input from the first unit and the third unit,

and an eighth unit receives input from the second unit and the fourth unit, 7D) utilizing four butterfly output registers (e, f, g, and h) that receive the values (a+b)+(c+d), (a-b)+(c-d), (a+b) (c+d), and (a-b)-(c-d), respectively, for, in determining FWT data for a first PPDID from a first RAM, determining a butterfly on the data from the first RAM 64 times to provide 64 output values, each output value being read out one at a time to memory of a holding RAM wherein, for determination of 64 next FWT butterflies, the holding RAM becomes a source of the next 64 FWT butterflies, the data in the holding RAM is read to the FWT circuitry in an altered order, and the memory

of the first RAM becomes a destination of said butterflies for the completed FWT data, and, where selected, wherein the altered order corresponds to an order obtained by permutation with matrix T1.

8. A display processor for at least a 240 row by 640 column liquid crystal display (LCD) for determining real time active addressing of drive signals for raster video data that has been apportioned into a plurality of portions of digital image data (PPDIDs), comprising two active-addressing signal devices, each comprising:

: 8A) at least three first dual-ported dynamic random access memory units (FIRST VRAMs), each VRAM being operably coupled to receive, in parallel, preselected PPDIDs, 8B) a first permuted inversion unit (FIRST PERM INV UNIT), operably coupled to each of the plurality of FIRST VRAMs, for mapping addresses of the preselected PPDIDs to first permuted addresses, 8C) a fast Walsh transform circuit (FWTC), operably coupled to the FIRST PERM INV UNIT, for providing control signals to at least the 240 LCD rows and for performing fast Walsh transforms on the first permuted addresses to provide fast Walsh transform (FWT) data, 8D) a second permuted inversion unit (SECOND PERM INV UNIT), operably coupled to the FWTC, for mapping the FWT data to second permuted addresses, 8E) at least three second dual-ported dynamic random access memory units (SECOND VRAMS), each operably coupled to receive,

in parallel, the second permuted addresses for selected PPDIDs, for providing buffer memory for storing the second permuted addresses until signal addressing data for at least the 640 columns has been accumulated in the buffer memory, 8F) a multiplexer, operably coupled for receiving and combining the accumulated signal addressing data, and 8G) a video digital to analog converter (video DAC), operably coupled for receiving the combined accumulated signal addressing data, for converting the combined accumulated signal addressing (digital) data to analog active addressing drive signals for at least the 640 LCD columns of 240 rows of a 480 row by 640 column LCD panel. 9.

The display processor of claim 8 wherein each of two halves of the raster video data is utilized to drive one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) and wherein the drive signal addressing is determined by the following matrix multiplications: G = R I where: R is a matrix of r columns of orthogonal pseudorandom maximum length shift register sequences of binary sequences (+1 and -1) of 255 elements, I is an r row by 640 column matrix of an image to be displayed on the half of the LCD, and G is a 255 row by 640 column matrix of drive signal waveforms, and the matrix multiplication has been simplified by: 9 A 1) writing matrix R as a transformed Walsh matrix, R = Ti W T2, where:

: Tland T2 are permutation matrices having only one nonzero entry per column equal to one of: + 1 and - 1, and W is a Walsh matrix of orthogonal Walsh sequences, and 9A2) substituting the transformed Walsh matrix R into the drive signal addressing matrix multiplication: G = T1 [W . [T2 .

I]], where: a column is read from the image matrix I in a permuted order (in accordance with T2 I ) and then is multiplied by a column of W to provide a result (W (T2 I)), and the result (W (T2 I)) is permuted with Tl to provide a resulting matrix G, which is written to the output buffer to provide column drive signals, and wherein W is factored utilizing a Fast Walsh Transform (FWT) technique in correspondence with a complex exponential matrix Fast Fourier Transform factoring technique.

1 0. The display processor of claim 9 wherein at least one of: 10A) r equals one of 10A1-10A2: lOAl) 240 (without gray scale correction) and 1 0A2) 241 (with gray scale correction); 10B) wherein the digital processor is arranged such that, for each active-addressing signal device, simultaneously (in parallel):

: 10B1) the FWTC determines FWT data for first permuted addresses determined for a second PPDID from a second FIRST VRAM, 10B2) a third PPDID is read into the FIRST PERM INV UNIT from a third FIRST VRAM, and 1 0B3) second permuted addresses for a first PPDID from a FIRST VRAM are written from the SECOND PERM INV UNIT to a first SECOND VRAM, wherein the second permuted addresses for the first PPDID are a portion of active addressing drive signal data for the digital image data, and such that the simultaneous operations of 10B1-10B3 are repeated until, for each active-addressing signal device, the active addresing drive signal data for drive signals for driving one-half (240 rows by 640 columns) of a video graphics array (VGA) sized liquid crystal display (LCD) have been output to the SECOND VRAMS;

; 10C) wherein the PPDIDs are digital image column data; 10D) wherein the PPDIDs are digital image row data; 1 0E) wherein the FWTC comprises a radix-4 butterfly determining means, and, where selected, wherein each PPDID comprises n (n an integer, zeros being added where n is other than a multiple of 4 such that n plus added zeros is a multiple of 4) bits of data, and, where selected, wherein n plus added zeros, if any, equals 256 and the radix-4 butterfly determining means performs the Fast Walsh Transform technique for further factoring W and comprises:

: 10E1) four butterfly input registers (a, b, c, and d) each operably coupled to receive 64 bits of data of the first PPDID, 10E2) four add-subtract units (a+b, ab, c+d, c-d), a first unit being operably coupled to receive input from registers a and b, a second unit being operably coupled to receive input from registers a and b, a third unit being operably coupled to receive input from c and d, and a fourth unit being operably coupled to receive input from c and d, respectively, for determining values for a+b, a-b, c+d, and c-d, respectively, 1 0E3) four further add-subtract units {[(a+b)+(c+d)], [(a-b)+(c-d)], [(a+b)-(c+d)], and [(a-b)-(c-d)]}, a fifth unit being operably coupled to receive input from the first unit and the third unit, a sixth unit being operably coupled to receive input from the second unit and the fourth unit,

a seventh unit being operably coupled to receive input from the first unit and the third unit, an eighth unit being operably coupled to receive input from the second unit and the fourth unit, for determining values for (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, 1 0E4) four butterfly output registers (e, f, g, and h), operably coupled to receive the values (a+b)+(c+d), (a-b)+(c-d), (a+b)-(c+d), and (a-b)-(c-d), respectively, for, in determining FWT data for a first PPDID from a first RAM, determining a butterfly on the data from the first RAM 64 times to provide 64 output values, each output value being read out one at a time to memory of a holding RAM wherein, for determination of 64 next FWT butterflies, the holding RAM becomes a source of the next 64 FWT butterflies,

the data in the holding RAM is read to the FWT circuitry in an

altered order, and the memory of the first RAM becomes a destination of said butterflies for the completed FWT data, and, where selected, wherein the altered order corresponds to an order obtained by permutation with matrix T1; 10F) further including a correction factor unit, operably coupled to at least a first FIRST VRAM, a second FIRST VRAM, a third FIRST VRAM, the FIRST PERM INV UNIT, and the FWTC, for, in parallel with inputting digital image data to the plurality of VRAMs, determining a gray scale correction factor and appending the factor to the digital image data that is subsequently stored as PPDIDs in preselected VRAMs, and, where selected, wherein the correction factor unit comprises:

: 10F1) a squaring unit, operably coupled to receive preselected digital image data, for providing a squared value for each of the digital image data, 12n, 2402 n 21, n being an integer, 1 0F2) a correction factor add-subtract unit, operably coupled to receive each squared value (12n) and a feedback value, for subtracting the squared value from the feedback value EMI35.1 for 240 iterations, to provide iterative correction outputs, 10F3) a feedback register, preloaded with a value 240, operably coupled to receive the correction outputs of the correction factor add-subtract unit and to the square root unit, for iteratively providing a feedback value for each of 240 iterative subtractions of the correction factor add-subtract unit, 10F4) a square root unit, operably coupled to the feedback register,

for providing a square root value of a 240th feedback value after 240 subtractions, EMI36.1 V being the gray scale correction factor for appending to the digital image data that is subsequently stored as PPDIDs in preselected RAMs; and 1 0G) further including an inversion means, operably coupled to receive columns of image data, for randomly inverting the values of rows of each column of image data and appending -1 to every column of an original matrix of columns of orthogonal pseudorandom binary sequences for digital image data.