WO1995002901A1

WO1995002901A1 - Top level via structure for programming prefabricated multi-level interconnect

Info

Publication number: WO1995002901A1
Application number: PCT/US1994/007097
Authority: WO
Inventors: Mark D. Kellam; Gershon Kedem
Original assignee: Astarix, Inc.
Priority date: 1993-07-15
Filing date: 1994-06-23
Publication date: 1995-01-26

Abstract

Two prefabricated conductors (114 and 152) are connected with a via-like structure comprising a conducting strap (116) passing through a hole in a dielectric (115). Unlike the commonly used traditional via structures requiring that connecting holes be made before fabrication of the upper level of the conducting wires, the disclosed structure can be completed by making said hole and strap after both conductors are already fabricated. This delays connecting the wires in an integrated circuit until late in the fabrication process, thereby reducing the time and cost required to customize the interconnections in a prefabricated general-purpose mask-programmable circuit resembling a gate array. Several variants of the basic method are possible, differing in the exact configurations of the via-like structure and in the exact process used to fabricate the conducting strap.

Description

Top Level Via Structure For Programming Prefabricated Multi-Level

Interconnect

Field of the Invention

This invention relates to semiconductor devices, and more particularly to a device and method for connecting two pre—fabricated layers of conductive interconnect.

Background of the Invention

Vias are structures commonly used in the manufacture of integrated circuits to connect two layers of conductive interconnect separated by one or more insulating layers.

Integrated circuits (ICs) are increasingly being used in a large variety of products. In particular, a type of ICs called Application Specific Integrated Circuits (ASICs), which are designed to perform special-purpose logical or algorithmic functions, has received wide acceptance in the electronics industry. However, there are barriers that limit the use of ASICs. Typically, the developmental costs associated with ASIC manufacturing are quite high because an ASIC is custom designed and manufactured for one user. For those products which do not have a high volume of sales, it may not be economically feasible to use ASICs, because the high developmental costs are shared by only a small number of integrated circuits. Further, the turn-around time for designing and manufacturing ASICs is long because custom tools, such as reticles, need to be built. As a result, there is a need for a process that can reduce the developmental costs and shorten the turn-around time of manufacturing ASICs.

The developmental costs associated with an ASIC are derived from several sources, including the enormous investment in capital equipment required to manufacture the integrated circuit, the engineering efforts required to design and ascertain the correctness of a new ASIC, the cost of design- specific masks or reticles needed to produce the circuit, and the design-specific setup costs incurred during the fabrication. For products that achieve large sales volumes, the developmental costs of the ASIC production may be spread across the many units produced. Further, the production cost is typically low because semiconductor production is oriented toward batch manufacturing (i.e., large numbers of ICs are processed simultaneously) where the fabrication costs of one IC and 1000 ICs are roughly identical. Thus, for sufficiently large volume productions, the low production costs combined with the small distributed developmental costs cause the total cost of an ASIC to be lower than the cost of manufacturing the equivalent circuit from combining a larger number of standard, general-purpose electronic sub-units. This feature makes the ASIC very competitive, and ASICs are responsible for making available a wide range of low cost and technically sophisticated consumer electronics products.

The most expensive and technically sophisticated form of ASICs is full-custom design. The production of such an ASIC begins with a detailed design of transistor switches and conductive interconnects that will be fabricated. These electronic devices are constructed on a semiconductor substrate by using multiple thin film depositions followed by photolithographic patterning and etching. While the full-custom design method enables the user to achieve the highest circuit density and performance by efficiently using all available area on the IC, the developmental costs associated with its use are very high. First, the costs of design, layout, and verification of the IC are quite high. In addition, the ASIC producer must pay for all of the photo masks (reticles) used to fabricate the IC. These reticles are typically fabricated using an electron-beam lithography system to pattern a thin chromium film on a quartz or glass substrate, and they are expensive. Typically, a full-custom CMOS implementation of a desired function requires between 15 and 18 of these reticles for the fabrication. Further, the semiconductor foundries charge their customers setup costs and capital depreciation for the fabrication equipment. These developmental costs are passed along by the ASIC producers to the ASIC end users and are often referred to as Non-Recurring Engineering (NRE) expenses.

There are two common approaches that reduce the developmental costs associated with full- custom ASIC design and production: the gate array and the standard cell design styles. Gate array technology involves the fabrication of a large number of base wafers containing identical integrated circuit elements (gates) up to the first level of conductive interconnect. The ASIC designer customizes the gate array by specifying only the conductive wiring patterns to be used to interconnect the prefabricated gates. The developmental costs of the reticles and setup charges associated with the prefabrication of the gates are shared among many different users, thereby reducing the NRE expense that each must incur. The number of reticles specific to a particular project are only those required to define from one to three levels of discretionary interconnect and the locations of the contacts (via holes or vias) between the different levels of conductive wiring. Each discretionary interconnect level requires two high-resolution reticles, one for patterning the metal wires and one for patterning of via holes in the dielectric thin film underlying these wires. The standard cell approach to ASIC production is adopted to reduce the NRE expenses associated with the design and layout of the full-custom IC. A number of carefully made designs of commonly used logical function blocks are stored in a library, from which they can be retrieved by an IC designer who interconnects them to provide the desired function. Both the standard cell and gate array technologies make extensive use of Computer Aided Design (CAD) software to automatically place the functional blocks and route the interconnect wiring defining the overall functionality of the

ASIC.

An alternative approach to NRE expense reduction has been made possible by the introduction of Field Programmable Gate Arrays (FPGAs). FPGAs contain logical cells, each of which can perform a number of different functions, and a reconfigurable interconnect grid. The cells are programmable, i.e., the particular function performed by each cell can be set after the FPGA is manufactured. The interconnect grid is programmable as well: it can be rearranged to connect the programmed cells in an appropriate manner so that the FPGA performs the desired function. One method of programming the interconnect network is to use pass-transistors as switches transferring signals between the various interconnect lines. These transistors are connected to memory cells whose contents determine whether each transistor acts as an open or a closed switch. The designer programs the FPGA by setting the values of memory cells and can change the function of the FPGA by entering new values into that memory.

Another FPGA technology involves the use of antifuses, which are onetime programmable switches. Each antifuse is nominally unconnected but can form a permanent conductive link after the application of a programming voltage across that antifuse. The first method has the advantage of being reprogrammable; however, the pass-transistors introduce considerable series resistance into the interconnect wires and severely limit the speed at which such ICs can operate. The antifuses exhibit somewhat lower series resistance than the pass-transistors, but the resistance-limited performance still falls well below that available from the metallic interconnects used in traditional gate array ICs. Both the pass-transistors, and to a somewhat lesser degree, antifuse technology suffer a considerable density penalty because of the area required to fabricate the actual switch and because of the area required by the control circuitry that programs the switches.

The low gate densities achievable in FPGA technologies have a dramatic impact on the economics of using VLSI products. Gate density is a direct factor in the computation of the production costs of IC production, so the FPGA technologies have, in effect, transferred the NRE developmental costs of the gate arrays to the production costs of obtaining large quantities of parts. The impact of this fact is that if an electronic system has to be manufactured in large quantities, its FPGA implementation is considerably more expensive that the gate array implementation. On the other hand, FPGAs are more economical to use for low-volume products, and their use considerably reduces the time between completing the design and delivering the product to the market.

Procedures have been developed to lower the NRE costs and reduce the turn-around time by reducing the number of processing steps required to accomplish the discretionary part of the process for fabricating gate arrays. One method of such programming involves patterning a single top level of discretionary wiring using a single high resolution reticle, one lithographic patterning and one reactive ion etch (RIE) process. Another method uses a discretionary via reticle followed by a non- discretionary metal reticle to provide the programming function. While these methods reduce NRE expenses in comparison with the traditional gate array, they produce lower density usable circuitry because of the area taken by the programming wires, and all such methods require at least one application specific high resolution reticle to be made before the ICs can be programmed. Thus, there is a need for a new kind of via-like structure and new processing steps which can lower costs and decrease production turn-around time.

Summary of the Invention

Broadly stated, the present invention is a via structure (top level via) for connecting pre¬ fabricated conducting layers of a semiconductor device, and methods for making such a via structure. The structure is formed on a substrate that may contain a variety of semiconducting devices and interconnect structures. A first layer of conducting interconnect wiring is patterned on the top surface of the substrate, and then covered by an inter-conductor dielectric material. A second layer of conducting interconnect wiring is patterned over the dielectric material. A top level via structure is created by lithographically defining a region that overlaps two wires that are initially unconnected. The inter-conductor dielectric exposed within the region is removed by anisotropic etching, thereby exposing the top surface of the two wires within the region. A conducting strap material is isotropically deposited within the defined region, making contact with the exposed surfaces of the wires, and covering the vertical walls formed by the etching of the dielectric. As a result, the first conducting wire is in electrical contact with the second conducting wire.

Two general forms of the top level via structure will be disclosed. The first is a "nested" top level via forming a connection between an upper level wire and a lower level wire at a location where the upper wire overlaps a portion of the lower level wire. A "nested" top level via is restricted so that the region exposed to anisotropic dielectric etching, and covered by the conducting strap, is completely contained within an area that is covered by either the upper conductor or the lower conductor. A second form, the "non-nested" top level via, allows the exposure of areas not covered by either conducting layer to the anisotropic etch, and strap deposition. Thus the "non-nested" top level via can be used to connect two upper level wires or two lower level wires. One way to reduce the developmental cost of fabrication of integrated circuits, such as ASICs, is to use a structure which serves to program the functionality of a circuit that contains at least two or more levels of prefabricated, but non-dedicated conductive wiring. The top level via structure allows the programmed interconnection of such prefabricated wiring and avoids the developmental costs and delays associated with the fabrication of a non-discretionary wiring layer over the top of a discretionary via layer. The top level via thus achieves a very high efficiency for prototyping because the developmental costs for processing of all of the wiring levels is shared among many users.

In addition, it is desirable that the resistance added to the interconnect wiring due to the presence of the programming structures be as low as possible. The top level via structure provides a programmable metallic conductive path between the wiring levels and avoids the resistive delays associated with pass-transistors and antifuse programming switches used in the prior art connection means.

Further, the programmable interconnect structure should occupy a minimal area on the integrated circuit so as to maximize the density of available circuit elements for use by the IC designer. In IC technology the size of the programmable top level via feature is no larger than the minimum feature available in the technology, and requires no additional programming circuits. Pass-transistor switching technology imposes a considerable density penalty for the area taken up by the programming switch, and both pass-transistor and antifuse technologies require large area overheads associated with the circuitry that performs the programming.

The programming technology should provide a simple, low risk migration path for re- implementing the IC in more traditional gate array technologies. Many prototyping technologies, including the FPGA approaches, trade the high developmental costs of gate array production for higher production costs of the prototyping technology. Users of prototyping technologies often wish to change technologies when the production volumes are large enough that the production costs begin to dominate the overall cost of the product. The migration from prototype quantities to high volume production should be possible without changes in the design or performance of the IC. A low risk migration path to high volume production has been a major stumbling block for FPGA users that wish to use large quantities of parts. The inherent series resistances associated with the FPGA programming elements must be inserted into the gate array versions of the design to insure that the design will function in the new embodiment. Unfortunately, these resistances carry with them the.same performance penalties that they cause in the FPGA version of the IC. If the resistances are not used in the gate array version of the design, a significant re-engineering effort is required to insure that IC functionality is maintained after the migration.

Because the top level via structure uses a metallic conductor to perform the functional programming, migration to a traditional gate array can be made without concerns about modifications of the interconnect performance changes. One embodiment of the top level via can be replaced by a traditional via placed in the same location by an automated layout CAD system. The strategy would involve the fabrication of identical substrates for production and prototyping up to the interconductor dielectric deposition. The upper conductor pattern would be fabricated on some of the wafers and used in conjunction with the top level via for prototyping purposes. Production quantities of a particular design would begin with the fabrication of a traditional via in the locations previously used to make a top level via connection. This approach allows a smooth transition between the low NRE prototype phase of a new design and the low production cost, high volume production phase of manufacturing.

Therefore, it is an object of the present invention to provide a method and a structure for connecting layers of a semiconductor device.

It is another object of the present invention to reduce the costs and turn-around time for fabricating integrated circuits.

It is a further object of the present invention to provide a via structure for programming two or more layers of pre-fabricated, but non-dedicated, conductive wiring. It is yet another object of the present invention to provide a low resistance metallic connection between two or more conducting layers of a semiconductor device.

It is also an object of the present invention to reduce the area of the programming via structure, thereby maximizing the density of the available circuit elements in a semiconductor device.

It is a further object of the present invention to provide a simple, low risk migration path from prototyping design to high volume production of semiconductor devices.

The advantageous features of the present invention will be readily understood from a description of the preferred exemplary embodiment when taken together with the attached drawings.

Brief Description of the Drawings

Figs. 1A-1C illustrate the use of prior art interconductor vias to program the function of an integrated circuit. Fig. 1A shows the components of the not yet programmed IC. Fig. IB and Fig. IC show the selective placement of interconductor vias to provide different programming functions.

Fig.2A shows a conventional interconductor via structure. Fig.2B shows a cross-section view of the conventional via structure shown in Fig.2A. Fig. 3 shows a prior art structure comprising a butting contact.

Fig.4 shows a prior art inter-connect structure.

Fig.5 shows a top view of a section of a structure on a substrate including a top level via in accordance with the present invention. Fig. 6 shows a top view of a nested top level via structure according to the present invention.

Fig. 7 shows a top view of a single top level via interconnection between upper and lower conductive wires and two prior art means of connection.

Fig.8 is a cross-sectional view of the structure illustrated in Fig. 7.

Fig.9 is an enlarged view of the top level via cross-section of Fig.8, showing in more detail the important elements of the top level via structure of the present invention.

Fig. 10 shows a cross-section view of a structure just before the application of the processing steps specific to the top level via according to the present invention.

Fig. 11 shows the structure of Fig. 10 after application of the tri-layer masking films, exposure of the top level via masking pattern and development of the photoresist. Fig. 12 shows the structure of Fig. 11 after the reactive ion etch of the inorganic etch template using the patterned photoresist as the etch mask.

Fig. 13 shows the structure of Fig. 11 after reactive ion etching of the organic release layer in an oxygen reactive ion etch. The inorganic template serves as a mask for this etch, and the photoresist is completely removed. Fig. 14 shows the structure of Fig. 13 after reactive ion etching of the top and interconductor dielectrics.

Fig. 15A shows the self-aligned coating of the interior of the top level via of the present invention with a catalyst thin film that is deposited by evaporation and then lifted off by dissolving the organic release layer. Fig. 15B shows the detailed structure of the catalyst film stack, including a catalyst layer and an adhesion layer.

Fig. 16 shows the final top level via structure formed by self-aligned electroless deposition of a metal onto the catalyst surface in the top level via of the present invention.

Fig. 17 shows another embodiment of a top level via according to the present invention. Fig. 18 shows an alternative top level via structure of the present invention that has no top dielectric layer.

Fig. 19 shows a top level via of the present invention fabricated using a blanket metal deposition.

Fig. 20 shows the patterned resist after re-masking of the top level via of Fig. 19. Fig.21 shows one of the steps in fabricating an embodiment of a top level via having a hidden conducting strap according to the present invention.

Fig.22 shows the structure from Fig. 21 after conformal conducting strap deposition.

Fig.23 shows the hidden conducting strap after fabricating the structure shown in Fig.22.

Fig.24 shows a method to connect two upper conductors with a single nested top level via. Fig.25 shows examples of non-nested top level vias according to the present invention. Fig.26 shows a single non-nested top level via of the present invention which is used to connect two upper conductors.

Fig.27 shows a single non-nested top level via of the present invention which is used to connect two lower conductors.

Detailed Description of the Invention

The via structure according to the present invention, namely, the top level via, provides a means of electrical connection between two levels of prefabricated interconnect. Various structures for providing electrical connection are known in the prior art. One of these structures is the conventional interconductor via. In order to provide a basis for comparison to the top level via structure, the construction of the conventional via and its application to programming an integrated circuit will be described in detail.

Figs. 1A to IC show a method for programming an integrated circuit function using conventional inter-connect vias. Figs. 1 A to IC show an integrated circuit (IC) consisting of a substrate

10 upon which is fabricated two circuit elements A and B, an upper layer of conductors 12, and a lower layer of conductors 14. Circuit elements A and B can perform different functions on an input electrical input signal, labeled as reference x, and provide the output signals A(x) and B(x) respectively. Layers 12 and 14 of conductive interconnect are used for communication of electrical signals between circuit elements A and B and for external interface.

Layers 12 and 14 are separated by an insulating dielectric film (not shown) that allows a wire on the upper layer of conductors 12 to cross over a wire on the lower layer of conductors 14 without making physical or electrical contact. If electrical connection between the layers is desired, it can be achieved by creating a hole in the dielectric at the location where the upper conductor crosses the lower one. This hole is normally made before fabrication of the upper layer of conductors. When the upper conductive wire is fabricated, its material will enter the hole and make physical and electrical contact to the surface of the lower conductor exposed inside the via.

Fig. 1 A symbolically depicts a simple programmable integrated circuit before it is programmed. Figs. IB and IC show that selective placement of the vias can be used to choose between the two possible output functions A(x) and B(x) that the programmable chip is capable of producing.

In the prior art, the placement choices of the vias are defined by making a high resolution mask (reticle) that contains a pattem etched in a thin layer of opaque chrome patterned on a transparent substrate. This pattern represents the vias desired on the IC. A photosensitive resist material is coated onto the IC substrate after the deposition of the interconductor dielectric and exposed to the pattern of light created by the reticle. In a most common process, the resist is rendered soluble in areas where a via is desired by exposing them to light. The resist is then removed from the via locations by immersing the substrate in a liquid developer. The substrate is then subjected to a process that etches the dielectric exposed in the areas where the protective resist has been dissolved. The dielectric is etched until the lower conductor surface is exposed, and then the resist is removed. Following the formation of the via hole, the upper conductor is deposited and patterned by a similar process. As explained below, the top level vias of the present invention are fabricated after the fabrication of both the upper and the lower layers of conductors, i.e., the fabrication of the top level vias can be the last step in the manufacturing of an ASIC. This approach is different from that used with conventional vias which have to be fabricated prior to the deposition of the upper layer of conductors. One application of this ordering of fabrication steps is that batches of ICs having different functions can be manufactured from a large number of pre-fabricated identical ICs comprising various circuit elements, such as elements A and B of Fig. 1 A. Top level vias can be used to program these pre¬ fabricated ICs to give each batch a different functionality. As a result, the processing time and the developmental costs incurred in the fabrication of the IC can be reduced. The most commonly used conventional via structure is subject to a set of restrictions that govern the placement of the via pattern edges relative to the edges of the upper and lower conducting wires to be connected. Figs.2A and 2B illustrate the restrictions required by a structure known as a nested via 18. Elements in Figs.2A and 2B which are similar to elements in Figs. 1 A to IC have the same reference numerals. Via 18 is formed on a structure including a substrate 10 which supports a lower dielectric 13, and a inter-conductor dielectric 15. The lower conductor layer 14 is deposited on the lower dielectric 13 and the upper conductor layer 12 is deposited on the inter-conductor dielectric 15. The inter-conductor dielectric 15 provides insulation between the lower conductor layer 14 and the upper conductor layer 12 except at the location of via 18.

In order to prevent the via etchant from attacking the dielectric underneath the lower conductor, the edges of the via pattern 18A, 18B, 18C, and 18D must fall within the boundaries of the lower conductor 14A, 14B, 14C, and 14D, respectively. The distance between the edges of the via and the lower conductor, for instance 18A to 14A, must be large enough to insure that the via falls entirely within the lower conductor area despite the possible inaccuracies in the patterning process. Such inaccuracies can be caused, e.g., by pattern misalignments or by the photolithographical process variations that affect the final sizes of the patterns transferred from the reticle onto the substrate. The distance between the edges of the via and the lower conductor must ensure that even the worst possible combinations of these factors expected to occur under normal processing conditions do not cause the patterned via hole to fall off the lower conductor area. Similar restrictions are commonly placed on the edges of the upper conductor 12A, 12B, 12C, and 12D. If the dielectric materials deposited underneath and above the lower layer of interconnect are different and if the etchant for the interconductor dielectric can be chosen so that it cannot damage the lower dielectric layer, these restrictions may be relaxed to allow the via edges to fall outside the boundaries of the metal patterns, creating a non-nested via.

Nested and non-nested conventional vias share two common attributes that differentiate them from the top level via structure according to the present invention. Both conventional via structures require that there must be some region of the structure that contains an overlap of the upper conductor, the lower conductor and the via. This requirement arises because the role of the via is to expose the lower conductor so that it can come into contact with the upper one. As discussed below, this restriction applies to the nested form of the top level via; however, for the upper and lower conductors to be connected in a non-nested top level via, it is sufficient that they both overlap the same region of the top level via pattern but not necessarily each other. In addition, the conventional structure requires that the via hole be etched before the fabrication of the upper conductor. The top level via structure is specifically designed to connect the upper and lower conductors after the fabrication of the upper conductor. This property significantly reduces the processing time and developmental costs incurred during the programming of the IC and provides an economic benefit compared to the traditional via. Finally, the top level via structure achieves the contact between the upper and lower conductors by strapping them with an additional conducting layer, which is not present in the traditional via.

The second prior art structure that will be discussed is the butting contact shown in Fig.3. The butting contact was used in older VLSI technologies to connect a polysilicon gate 47 directly to an adjacent diffusion region 45 by opening a contact window 49 in an oxide film 48, and strapping the polysilicon and diffusion regions with a deposited metal strap 50 that covered the contact window. The strap metal was required to cover the side surface 42 of the gate insulator 46.

One significant difference between the butting contact in Fig.3 and the top level via, shown in Fig. 9, is that the strap metal film 116 in the top level via structure is self-aligned to the contact hole etched into the dielectric, as explained below, and does not exhibit the large overlaps 43 present in the butting contact structure. These overlaps of the metal extending over the contact hole boundaries were required to ensure the proper contact between polysilicon gate 47 and diffusion region 45. The self- alignment of the top level via metal strap 116, shown in Fig.9, permits the fabrication of top level vias in much closer proximity, relative to the horizontal dimensions of the top level via structure, than would be possible for structures with overlaps 43 in the butting contact.

The second significant difference between the butting contact and the top level via structures is the step coverage requirement represented by the ratio of the gate insulator thickness to the strapping metal thickness. The typical use of the butting contact involved metal thickness of metal 50 greater than 1000 nm, which was more than enough to cover the typically 70 nm thick gate insulator step 42. The top level via must meet a much more difficult step coverage criterion because the inter- dielectric material 15 thickness may range from 500 to 1000 nm while metal thickness is approximately 500 nm.

The third significant difference between the butting contact and the top level via embodied in the invention is the ratio of the horizontal dimensions of the contact hole to its depth in both structures. In the butting contact, the horizontal and depth dimensions were typically 3.0 micrometers and under 1.0 micrometer, respectively - thereby producing an aspect ratio width/depth on the order of 3 or greater. The top level via structure can be produced at horizontal dimensions below 0.5 micrometers, with depths on the order of 1.0 to 1.5 micrometers, resulting in the aspect ratio width/depth as low as 1/3, well out of the range of a feasibility for the methods used to fabricate butting contacts. Finally, a fourth significant difference is that unlike the top level via structure, the butting contacts could be manufactured only in the nested form.

' A third structure that will be discussed was disclosed in U.S. Patent No.4,872,050, issued to Okamoto et. al. This patent teaches a method of connecting two pairs of layered interconnects through a single via hole as illustrated in Fig 4. In Fig.4, two conductive layers 55 and 57, included in a multi- layer structure 65, are electrically connected through a conductive sidewall connection 60 provided in a contact hole 66. Note that the sidewall connection 60 comes into contact with the side surfaces 63 and 64 of layers 55 and 57 in the multi-layer structure 65. The upper conductive layer 59 existing on the multi-layer structure 65 and a conductive layer 53 existing under the multi-layer structure 65 are electrically connected at the surface 62 provided in the contact hole 66. These two interconnections are insulated from each other by an insulating film 61 provided on the connection wall 60. Note that the second interconnection of the conductive layer 53 via the surface 62 to the conductive layer 59 is just a traditional via described earlier.

A comparison of the structure disclosed by Okamoto et al. (shown in Fig.4) with the top level via structure illustrated in Fig.9 will show the similarities and differences between these two structures. Both structures use a conductive sidewall material to bridge a dielectric gap between an upper and lower conductor. The mode of connection between the sidewall conductor and the upper and lower conductors is quite different, however, and that difference has a significant impact upon the yield and performance of the interconnect. The structure disclosed in Okamoto et al. (shown in Fig.4) relies on connection of the conductive sidewall 60 to the side surface 63 of the upper conductor 57 and the side surface 64 of the lower conductor 55. In order to form the conductive sidewall spacer material, the surfaces of the conducting films 63 and 64 must be perpendicular to the plane of the substrate. The anisotropic reactive ion etch of the metal films 57 and 55 that leads to such high side surface angles can also produce contamination on the surface that leads to high electrical resistance and poor yield. During the anisotropic reactive ion etch of the metal wires, ions bombard the surface in a preferred direction, which is defined by an electric field set up in the plasma. The rate of ion bombardment on a sidewall is much less than that on a planar surface, giving rise to the anisotropic nature of the etch. A second contribution to the anisotropy is made by gaseous etch products that combine with organic molecules from the photoresist and re-deposit over the entire surface. Because the sidewall receives less activated ion bombardment, a polymeric film tends to grow selectively along the sidewall, coating the metal surface. This further reduces the etch rate of the metal on the sidewall, improving the anisotropy of the etch. Such polymers, when deposited between two conductors, can increase contact resistance and reduce the yield of the connections.

While the top level via conducting strap 116 makes a physical connection to the side surface of the upper conductor 16B as shown in Fig 9, this common surface is not required to make a low resistance electrical contact. Unlike the structure disclosed in Okamoto et al., the principal design in the top level via is to have the conducting strap 116 make a physical and electrical connection to the upper surface 16A of the upper conductor 112 and a physical and electrical connection to the upper surface 16D of the lower conductor 114. This structural difference avoids problems associated with making electrical connection to the vertical metal side surface 16B and, by relying on contacts made on horizontal surfaces 16A and 16D, provides lower a connection with lower series resistance and higher reliability.

Contacts can also be used in packaging technology. For example, U.S. Patent No.5,055,907 issued to Jacobs discloses a method of attaching a thin film multi-layer wiring decal to an integrated circuit. This method is intended to provide a low cost and high performance multi-chip packaging technique. It uses a structure called a reach-through via, which is defined as a thin film connection between the wiring in the decal and a pad on the integrated circuit. Because these connections are constructed to make connections to pads, which are typically larger than 50 microns in width, they cannot be used to connect multiple levels of wiring at the small dimensions found in modern integrated circuits. The top level via structure disclosed herein contains several significant structural and process differences that enable it to connect the dense, high resolution interconnections on an advanced integrated circuit.

Jacobs discloses that the sidewalls of the "reach-through" via must be sloped, as seen in Fig 6A of that reference. This restriction is consistently applied to insure that metal deposited across the edge of the via wall has good "step" coverage. The reasons for such restriction is that the deposition techniques disclosed in Jacobs, sputtering and evaporation, involve directional transmission of the deposited species from a distant source. The thickness of the metal deposited on a via sidewall will depend on the angle of the sidewall and the angular distribution of the deposited particles relative to a vector that is perpendicular to the substrate surface. While the angular distributions of particles deposited by sputtering are broader than those created by evaporation, neither technique can achieve adequate step coverage when the via wall angle is nearly perpendicular. The sloped via sidewall restriction introduces two distances that adversely impact the overall density of the interconnect. The minimum distance between two conducting wires that are to be connected is composed of the sum of the width of the sloped via sidewall, and the distance from the top edge of the via to the upper conductor edge. This second length must be large enough to insure that under the worst case misalignment of the via and upper conductor patterns, that the isotropic etch of the sloped via does not cause undercut of the upper conductor. The current invention eliminates the density reduction associated with the sloped via sidewall. The sidewall of the via is self-aligned to the upper conductor, which masks the anisotropic etch of the inter-conductor dielectric. The electroless plating process is extremely conformal and will deposit an equal thickness on the top surface and on a side surface, regardless of it's angle. This property enables significantly denser placement of potential programming vias when used with the top level via structure.

Figs.5-9 illustrate the use of top level vias to connect photolithographically patterned wires to each other. Figure 5 shows a top view of a section of a substrate 110 upon which wires have been fabricated by any of the well known thin film deposition techniques followed by photolithographic patterning and etching. The structure is built upon a solid substrate 110 that may contain other circuit structures. Fig.5 shows the crossing of two horizontal wires, #5 and #6, on the lower level of conductive interconnect 114 by four vertical wires, #1, #2, #3 and #4, on the upper level of interconnect 112. A thin film dielectric deposited on the top surface of the substrate 110 isolates electrically the lower level of conductive interconnect 114 from the substrate 110. A conventional electrical contact 118 between the lower level of conductor 114 and the substrate 110 can be made by opening a hole in a lower dielectric that allows physical contact between the bottom of the lower conductor and the top surface of the substrate 1 0. A thin film dielectric material deposited over the top surface of the lower conductive layer allows the upper conductive wires to pass over the lower ones without forming an electrical contact. A conventional via connection 19 between the upper level of conductor 112 and the lower level of conductor 114 can be made by opening a hole in this interconductor dielectric to allow physical contact between the bottom surface of the upper conductor and the top surface of the lower conductor.

Fig. 5 also shows the same substrate 110 after fabrication of top level vias 156 and 157 that electrically connect wires #1 and #2, respectively, to wire #5 and top level via 120, that electrically connects wire #3 to wire #6. After the processing of the top level via, wire #3 is also connected to the substrate through the substrate contact 118 and to wire #4 through the conventional via. These two sets of connected wires remain electrically isolated from each other and could be used to transmit an electrical signal from one location on the substrate to another. Fig.6 shows a top view of the details of a nested top level via showing the areas and edges of the structure that will be used in the specification that follows. The figure shows an upper level conductor 112 and a lower level conductor 114 that have been prefabricated on a substrate with an isolating interconductor dielectric (not shown) deposited between them. The edge 112C of the upper conductor extends over the lower conductor beyond its edge 114A so that the lower conductors top surface appears in the area just to the right of the edge 112C of the upper conductor. The top level via

120 is defined as a closed area placed straddling the edge 112C of the upper conductor where it overlaps the lower conductor 114. Part 120E of the top level via area overlaps with the upper conductor, and part 120F of the top level via area overlaps the lower conductor. The first structure to be discussed is restricted to be nested. For this purpose, nested shall mean that the part 120F of the top level via area that extends beyond the upper conductors boundary falls entirely within the lower conductors area and is not intersected by the lower conductors boundary. In the example shown in Fig.6, the edges 120D, 120A and 120B of the top level via fall on the conductor side of the edges 112D, 112A, and 112B, respectively, of the upper conductor, and the edges 120B, 120C, and 120D of the top level via fall on the conductor side of edges 114B, 114C, and 114D, respectively, of the lower conductor. Edge 112C of the upper conductor is restricted to fall within the area 120 of the top level via. Edge

114A of the lower conductor is restricted to fall on the conductor side of edge 112C of the upper conductor but is not restricted to remain under the upper conductor area 112 or to remain within the area of the top level via 120.

Fig. 7 shows the top view of single top level via interconnection 120 between a upper conductive wire 152 and lower conductive wire 114 in comparison to the traditional substrate contact

118 and interconductor via 119. The interconductor via 119 provides electrical contact between the upper conductor 154 and the lower conductor 114. Fig.8 is a cross-sectional perspective view of the structure illustrated in Fig. 7 with the cross-sectional cut aligned along line 8-8. The structure is built upon substrate 110. Other semiconductor structures (not shown) are connected to the upper level conductive wiring 152 and 154 and the lower level conductive wiring 114. The formation of the top level vias conductive strap 116 may thus be used to electrically connect two or more of these semiconductor structures.

The formation of the prior art means of connection is first described. Referring to Fig. 8, the top surface of the substrate 1 0 is coated with a dielectric material 113 that serves as electrical isolation between the lower level of conductive wiring 1 4 and the substrate devices 110. The most commonly used dielectric is a silicon dioxide film deposited by one of several well known methods including low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). A lower level of conductive wiring 114 is fabricated on top of the lower dielectric 110 by well known photolithographic patterning processes. This level of conductor may make electrical connections to devices on the substrate level through contact holes 119 opened in the lower dielectric material. An interconductor dielectric layer 115 is deposited on the top surface of the lower interconnect level for the purpose of electrical isolation between the lower conductive wires 114 and the upper conductive wires 112. This layer is usually composed of silicon dioxide and is planarized by one of a number of well known methods, such as simultaneous deposition and etching or electrochemical polishing. Connections between the upper and lower conductive layers may be arranged prior to the fabrication of the upper conductor by opening via windows 118 in the interconductor dielectric. A upper layer of conductive interconnect 154 lies on top of the interconductor dielectric layer 115. This upper conductive film 154 is deposited and patterned by well known photolithographic processes. The top level via 120 according to the present invention is now described. A thin conformal dielectric film 111 is deposited on top of the upper conductors 152 and 154 in the regions where the upper conductors have not been removed by its patterning process and lies on top of the interconductor dielectric 115 in the regions where the upper conductor has been removed. The deposition of the top dielectric 111 is conformal so that the sidewalls of the interconductor dielectric and upper conductor are coated by a thickness that is approximately equal to the thickness of the deposited top dielectric on the top surfaces of the upper conductor and the interconductor dielectric. The top dielectric material deposited on this sidewall is designed to be anisotropically etched in the same reactive ion etch (RIE) chemistry as the interconductor dielectric. The anisotropic etching of the top dielectric 111 that rests on the sidewall of the upper conductor 152 will lead to the formation of the sidewall spacer 122. This step ends the description of the methods of preparing the substrate for the top level via process.

The cross-sectional view in Fig. 8 allows comparison of the top level via structure 120 to the conventional substrate contact 118 and interconductor via 119. While the patterning of the conventional structure must take place before the patterning of the uppermost conductor, the top level via structure 120 (top level via) is designed to connect the upper and lower conductive wires after both are constructed. The top level via structure is formed along an edge of the upper conductor 152A that intersects an area covered by the lower conductor. The edge of the lower conductor 114A must extend under the upper conductor edge 152A for a sufficient distance 121 to insure that this overlap is always positive regardless of process variations. The top level via pattem is defined as a continuous area along the edge 152A such that a portion of the top level via area 120E (shown in Fig. 7) overlaps the upper conductor 152 and a portion of the top level via area 120F (shown in Fig. 7) overlaps the lower conductor 114. This area is converted by lithographic patterning and etching processes into a hole in the interconductor dielectric 115. The etching process is chosen in such a way that the interconductor dielectric 115 exposed within the top level via area will be etched unless that dielectric 115 is protected by the presence of the upper conductor. Thus the area over which the interconductor dielectric 115 is removed during the etch is defined on three sides 117B by the top level via area definition and on one side by the upper conductor edge 117A. A dielectric sidewall spacer 122 is formed on the edge of the via hole 117A defined by the edge of the upper conductor 152. The top of the spacer 122 begins a short distance down along the sidewall of the upper conductor 152 and continues to cover the edge of the via to the bottom of the via hole 120. Because the etch of the dielectric does not remove the upper and lower conductor materials, the removal of the interconductor dielectric 115 stops on the lower conductor 114, exposing its top surface within the area where it overlaps with the top level via area 120F (shown in Fig. 7). A conducting strap material 116 is then deposited conformally within the area defined by the top level via masking 120, using a self-aligning deposition method described later. Because of the conformal deposition, the thickness of the strap metal 116 is the same on the vertical surfaces 117A and 117B of the via hole formed in the interconductor dielectric as the thickness on the horizontal surfaces of the upper and lower conductor.

Fig.9 is an enlarged view of the cross-sectional view of the top level via illustrated in Figs.7 and 8. Fig.9 illustrates the important components of the conducting strap 116 and serves to describe the method by which it electrically connects the upper conductor 152 to the lower conductor 114. The conducting strap 116 forms a low resistance electrical connection to the upper conductor 152 at its intersection with the top surface of the upper conductor 116A. The strap conductor 116 also makes physical contact with the upper conductor 152 along the sidewall of the upper conductor 116B; however, because the top surface contact 116A has been made, this region on the sidewall of the upper conductor is not required to make good electrical contact. The strap conductor then forms a continuous electrical bridge 116C across the sidewall spacer 122 of the interconductor dielectric 117A defined during the etching process by the edge of the upper conductor 152A. The strap metal 116 then makes electrical contact 116D to the top surface of the lower conductor 114 the area of the top level via that overlaps the lower conductor and not the upper conductor. These connections allow a continuous electrical current to flow between the upper conductor 152 and the lower conductor 114. The strap conductor 116 then continues up the vertical walls of the top level via 116E that were defined by the edge 117B of the resist pattern of the top level via. Because of the self-alignment of the strap conductor to the etched pattern in the top and interconductor dielectrics, the strap ends at or near the top of this vertical wall.

Description of the Process Flow

A detailed process flow, shown in Figs. 10 to 16, is now given for fabricating the top level via connections on a substrate 210 that contains at least two levels of prefabricated conductive wiring, i.e., an upper level conductive wiring 212 and a lower level conductive wiring 214. The substrate 210 may also contain electronic switching devices that have been fabricated below the interconnect levels, with electrical connections to the conductive wiring at various points. Although the process flow for making the top level via does not depend on the details of the prefabrication and is compatible with almost any modern process for making integrated circuits, a short description of one possible prefabrication sequence will be included as background for the invention. Fig. 10 shows a cross-section of the substrate 210 in a location where upper and lower conductors are to be connected by a top level via. Figure 10 does not show other electronic structures fabricated in the substrate 210, but it is understood that this fabrication may have been done. The top level via process is not restrictive as to the types of materials used as a substrate, the types of devices fabricated on the substrate, or the process used to create the substrate. The top level via invention may be used to make electrical connections to all classes of electronic devices.

After fabricating the device structures into the substrate 210, a dielectric film, called here the lower dielectric 213, is deposited over the devices and the substrate. A lower conductive layer 214 is deposited on the top surface of the lower dielectric 213. A wide range of metallic elements or alloys including aluminum, copper, and gold may be used for this purpose, and a large number of deposition techniques for these materials are known. Because of its wide use in modern CMOS processes, an aluminum-copper-silicon alloy is preferably used for the lower conductive films 214. A positive- acting photoresist material (not shown) is coated over the conductive film 214 and exposed to a radiation pattern that corresponds to the inverse of the wiring features that will be created on the wafer. The resist is then immersed in a developer solution that washes away the exposed resist, leaving intact the unexposed resist over the areas where the metal wires will be formed. The patterned wafer is then exposed to a wet etchant or a reactive ion etch chemistry that removes the conductive layer from the areas not protected by the patterned resist remaining on the wafer. In this manner, the exposed pattern is transferred onto the conductive layer. The resist is then removed with a solvent. An interconductor dielectric 215 is deposited conformally on the top and side surfaces of the lower metal pattern 214 and on the top surface of the lower dielectric 213 in areas where the lower conductor 214 has been removed. The most common choice of material for the interconductor dielectric 215 is silicon dioxide deposited by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). Other materials such as polyimides or doped glasses may also be used. Dielectric film 215 is usually planarized to reduce the large steps caused by the topography of the substrate and the lower conductor. A wide range of planarization techniques have been reported, but one simple method that illustrates the concept will be described. An organic film (not shown) is spin-coated on the substrate, planarizing the topographic features. The organic film and the dielectric film 215 are anisotropically etched in a reactive ion etch chemistry that etches both at the same rate. The remaining resist is removed, and a second dielectric film (not shown) is deposited. This process, or several repetitions of it will reduce the step height of the top surface of the interconductor dielectric 215 as it passes over the lower conductor wires. A photoresist mask (not shown) may be used at this point to etch the dielectric away from over the lower conductor 214 in regions where electrical contact between the conductive layers is desired. Such vias will be formed when an upper conductor is deposited over the exposed lower conductor 214.

An upper conductor 212 is then deposited on the top surface of the interconductor dielectric 215. Because of its wide use in modern CMOS processes, an aluminum copper silicon alloy is preferably used for the upper conductive films 212. This film 212 is patterned and etched in a similar fashion to the lower conductor 214, producing the upper level of wiring 212. After removal of the resist used to pattern the upper wiring 212, the top dielectric film 211 is conformally deposited by LPCVD or PECVD. This film 211 is approximately 100 nm thick and is chosen to be silicon dioxide for the preferred embodiment. The film 211 serves several functions during the top level via process. It protects the prefabricated wafer while it is waiting for the top level via process. It also serves as an undercutting material to enable the liftoff of a catalyst film and creates a sidewall spacer along the edge of the top level via defined by the upper conductor 212.

The next step in the top level via process involves the photolithographic patterning of the top level via area. While common single layer resists can be used to process the top level via, the preferred embodiment uses a tri-layer resist stack that reduces the enlargement of the top level via during etching of the dielectrics and reduces lithographic problems associated with the topography and reflectance of the edge of the upper conductor. The structure of the preferred embodiment is shown in

Fig. 11. The tri-layer stack is created by spin-coating of an organic release layer 224 on the top surface of the top dielectric 211. The material requirements for this coating are that it must assist in planarizing the upper conductor step, it must be processed at temperatures below 400 degrees C to avoid metal hillock formation, and it must remain soluble in a solvent in order to enable the liftoff step that follows. In addition, the coating must provide about 0.5 micrometers of material thickness over the upper metal conductor 212 in order to adequately mask the etching steps that follow. One material that meets these requirement is a preimidized polyimide available from Ciba Geigy: Probamide 285™. This material may be spin-coated on a substrate treated with an adhesion promoter, and it remains soluble after a 2 minute hot plate bake at 250 degrees C to remove the solvents. The degree of planarization of this material is good and the thickness requirements over the upper metal conductor

212 are satisfied. Next, an inorganic etch template 226 is deposited on the top surface of the organic release layer 224. This film 226 must be resistant to reactive ion etching in oxygen, but it must be etchable in some other medium. These requirements are met by films of metals such as aluminum, dielectrics such as silicon dioxide and silicon nitride, coatable dielectrics such as spin-on glasses, and thin semiconducting films. The preferred embodiment, chosen because of simplicity and cost, is an evaporated film of silicon 60 nm thick. It is clear to those skilled in the art that a wide range of other materials and deposition processes is available for the application of this film 226. The tri-layer stack, shown in Fig. 11, is completed by the spin-coating of a photoresist material 228 that is exposed in the areas defined by the top level via mask. The resist is then developed in a solution that removes the exposed regions of the photoresist, thereby uncovering the surface of the inorganic etch template 226 in these regions.

The substrate as prepared by the above steps is then subjected to a reactive ion etch (RIE) chemistry to remove the inorganic etch template 226 in the regions not protected by the patterned photoresist 228. A wide range of RIE gases can be used to etch the inorganic etch template; e.g., for silicon, one can use HC1, CI2, and SFg. CF4 has been chosen as the preferred etch gas for this process step.

Fig. 12 shows the appearance of the top level via following the etching of the inorganic etch template 226. The template material has been removed from the region where the resist was exposed and developed, thereby uncovering the top surface of the underlying inorganic release layer 224. Fig. 13 shows the top level via structure after the completion of the next process step, a anisotropic reactive ion etch (RIE) in oxygen. The oxygen RIE process attacks both the organic release layer material 224 and the photoresist 228 on top of the inorganic etch template 226. If the cathode bias during the etch is low enough to prevent physical sputtering of the etch template 226, the etch in oxygen will not etch the silicon template 226, which therefore acts as a mask for the etching of the organic release layer 224.60 nm of silicon in this application is sufficient to mask more than 2 micrometers of polyimide etching in the oxygen RIE process. Because the upper conductor wires 212 are nominally about 1.0 micrometers thick and the thickness of polyimide over the upper conductor is about 0.5 micrometers thick, the total amount of etching required to remove the organic release layer 224 from the top level via hole is about 1.5 micrometers. The process specifications include about 25% overetching past endpoint to account for thickness and etch rate variations and to insure that the polyimide is completely removed. If the pressure of the etching chamber is low enough, the etch will be very anisotropic, leading to sidewalls in the organic film which are nearly perpendicular to the plane of the substrate 210 and are positioned closely to the silicon edges formed by the hole etched into the silicon etch template 226. A small amount of isotropic etching is observed during the RIE of the polyimide and leads to a small amount of undercut of the etch template 226 by the organic material 224A. The process described here leads to less than 0.2 micrometers of undercut during 2.0 micrometers etching of the organic release layer 224.

The next process step involves reactive ion etching of the top dielectric 211 and interconductor dielectric 215 films using the inorganic etch template 226 and organic release layers 224 as etch masks

(see Fig. 14 and Fig. 15). It is possible to etch the dielectrics using only a thick inorganic etch template 226 as a mask. It is necessary in this case to remove the inorganic etch template 226 before proceeding to the subsequent catalyst evaporation and liftoff steps. The presence of the etch template 226 during the evaporation of the catalyst film 232 may indirectly cause contamination of the deposited catalyst due to water vapor or other contaminants trapped within the organic release layer emanating from the sidewalls of the organic release layer during the catalyst evaporation and modifying the deposited film. Any such contaminants may be released quickly through the top surface of the release layer 224 under low pressure if there is no vapor barrier to impede their release. This effect is not fully understood, but the preferred process removes the template before the catalyst deposition. One method of avoiding the extra etching step associated with removing the template was developed for a

CHF3 O2 RIE process commonly used to etch contact holes in silicon dioxide for VLSI devices. This process etches the silicon dioxide dielectric 5 times faster than the silicon etch template 226. The 60 nm thickness of the silicon etch template 226 was chosen so that when the combination of the top and interconductor dielectric were completely etched, and an overetch added to account for thickness and etch rate variation, some of the organic release layer material remains over the upper conductor, yet the template material is completely removed. Because the CHF3 O2 RIE process may leave a fluorocarbon polymer residue on the surfaces of the conductors exposed to the process, a short cleanup step in oxygen RIE is performed after the oxide etch. This is followed by a short immersion of the wafers in a dilute, buffered HF solution, timed to remove about 3 nm of silicon dioxide. The purpose of this etch is to slightly undercut the top dielectric beneath the remaining organic release layer and to produce the undercut 230, enabling the liftoff of the deposited catalyst in the subsequent step when the substrate is immersed in a solvent.

Fig. 14 also illustrates the formation of a sidewall spacer 222 along the edge of the upper conductor. This spacer 222 extends from the top surface of the lower conductor 214 to about half way up the sidewall of the upper metal 212. The purpose of the spacer is to prevent the interconductor dielectric 215, from being etched underneath the upper conductor during the dilute HF dip. Such an undercut would prevent a continuous catalyst film coverage of the vertical wall formed by the sidewall of the upper metal 212 and the dielectric sidewall below it. If the thickness of the upper metal 212 is greater than the thickness of the interconductor dielectric 215 then the spacer will always cover this edge and prevent incomplete catalyst coverage. Experiments with electroless plating solutions indicate that a continuous film can be deposited even if the catalyst film is not fully continuous over this edge. The preferred embodiment includes this structure, however, since the top dielectric 2 1 is needed to perform the liftoff and the spacer 222 is a consequence of its presence.

Just before the deposition of the catalyst, the native and plasma-grown oxides on the top conductor need to be removed or minimized in order to achieve the best contact resistance and yield.

This step may depend on the details of the material choice for the top conductor 212 since the chemistry of removal will depend on the properties of the specific metal oxide found at the conductor surface. Physical removal with sputter or ion gun cleaning have been reported, but such approaches encounter some difficulty with high aspect ratio structures such as the ones described in this invention. For the aluminum based metallurgy used by most IC manufacturers, various wet chemical etches are commonly used. Phosphoric acid or HF based etches, performed just before the wafers are loaded into the vacuum of the deposition system, are commonly reported in the interconnect literature. Some processes, for example, the zincate process, chemically modify the top surface of the aluminum to prevent or slow down its re-oxidation. A short dip in an aluminum etch bath composed of phosphoric, acetic and nitric acid has been demonstrated to yield low-resistance top level vias within the preferred embodiment process.

Fig. 15A shows the structure after evaporative deposition and liftoff of the catalyst film stack 232. Several metals are known to act as catalysts for the subsequent electroless deposition of the strapping metal 216. Of these, a palladium-aluminum alloy was chosen for its low cost, good adhesion and high rate of catalytic activity. The use of the alloy for initiating the electroless plating is disclosed in a co-pending patent application Serial Number 08/091,972, entitled "Aluminum-Palladium Alloy for Initiation of Electroless Plating", the specification of which is incorporated by reference herein. To enhance adhesion of the palladium to the aluminum pads, first a 20 nm film of titanium is deposited by evaporation from a resistive source in vacuum. This step is immediately followed by a similar depositions of 20 nm palladium film and a 20 nm aluminum film without exposing the titanium film to the atmosphere. The combined thicknesses of the deposited metals should be roughly less than the thickness of the top dielectric 211 to achieve a high yield liftoff process. The lower limit of palladium alloy thickness to catalyze the electroless process is approximately 5 nm; however, 20 nm was chosen because of the difficulty in reproducibly controlling thinner depositions. The substrates are mounted on a fixture that undergoes a planetary motion which has at its central radius the evaporation source. While the evaporant flux is not fully directional and will coat the sidewalls of the via hole, the undercut 230 of the top dielectric under the organic release layer 224 insures that the metal film continuity will be broken on the lower surface of the undercut. The organic material exposed in this region will not be coated with the catalyst metal and will be attacked by the solvent during the liftoff step.

Following the catalyst deposition; the liftoff is achieved by immersion of the semiconductor stmcture in a solvent for the organic release layer. The polyimide chosen as the preferred embodiment of the release layer is highly soluble in most N-Methly-Pyrolidone (NMP) based solvents. Ultrasonic agitation is applied during the immersion in the solvent to hasten the liftoff process. The wafers are then annealed for several minutes at 200 degrees C to cause inter-diffusion of the aluminum and palladium. Immediately prior to plating,, the substrates are exposed to a dilute aluminum etchant to remove the un-reacted aluminum from the alloy surface. Reference number 235 in Figure 15A shows the location of an enlarged view (Fig 15B) of the catalyst stack stmcture cross section. This detailed view shows the placement of the adhesion layer 234, and the catalyst layer 233. Fig. 16 illustrates the completed top level via stmcture after the catalyst-coated sidewalls are exposed to an electroless plating solution. An electroless plating bath is generally composed of an aqueous source of metal ions, a reducing agent, complexing agents, and stabilizers or inhibitor. The plating of metal from the solution is caused by an oxidation reaction of the reducing agent that liberates electrons: Red > Ox + n e

Metal ions consume the electrons in a reduction reaction that produces the metallic deposit: m*M⁺ⁱ + πvre > πvM", πvi = n

In general, electroless plating is characterized by the selective reduction of metal ions on a catalytic surface. Since the deposited metal catalyses the reduction reaction, the process is autocatalytic, and deposits of metal are formed that are self-aligned to an initial pattem of a catalyst material.

The conducting strap 216 formed in the above described process is self aligned to the catalyst metal 232 in the via hole and does not grow in areas not covered by the catalyst. A variety of metals may be deposited by electroless deposition, including gold, palladium, copper, cobalt, nickel, and nickel alloys. The choice of a material and process for fabricating the conducting strap must be based on a variety of factors including cost, safety, reliability, resistivity, compatibility with the substrate materials, and overall yield. No electroless plating chemistry achieves excellent performance in all of these areas, but a plating bath for a nickel boron alloy exhibits many positive features. A commercially available solution (Allied Kelite 752) uses DiMethyl Amine Borane (DMAB) as a reducing agent and yields a nickel-boron alloy plating rate of about 100 nm per minute at 65 degrees C and an operating pH of 6.0. The films deposited on the catalyst are very conformal and appear to have no voids or cusps at comers or gaps in the via structure. Cross-sectional scanning electron microscopy (SEM) shows that the plated films tend to fill in small gaps in the catalyst metal and therefore are not very sensitive to step coverage of the catalyst. After the plating solution is thoroughly rinsed off in distilled water, the substrates are annealed in an inert ambient to sinter the vias. This step is commonly performed using hydrogen or a hydrogen inert gas mixture to assist in the reduction of native oxides that can have a deleterious effect on the contact resistance between two metal films.

Following the anneal, the substrates may be coated with a passivating film patterned to allow wire bonding or electrical connection to the contact pads on the substrate. A variety of processes is commonly practiced and will not be discussed further.

Alternative Structures And Processes

It is also possible to make a top level via compatible with a conventional via. A second structure, shown in Fig. 17, is defined by a restriction on the placements and dimensions of the structure shown in Fig. 8. Elements which are the same in Figs. 8 and 17 use the same reference numerals. In the preferred embodiment shown in Fig.8, the edge of the lower conductor 114 A that extends under the edge of the upper conductor 152A only needs to extend under the upper metal for a distance that insures that the top level via etching will not extend beyond the edge of the lower conductor 114 A, given the worst case misalignment and biases of the conductor levels. Given a typical 1.0 micrometer process, with an metal etch bias of 0.2 micrometers and a worst case misalignment of 0.3 microns, the minimum distance between these edges (152A to 114A) must be greater than roughly 0.7 micrometers. A second structure of the preferred embodiment, shown in Fig. 17, further restricts this distance to allow the placement of a conventional via in the overlap region of the upper and lower conductors. Comparison of Fig.8 and Fig. 17 shows that if the distance 121, shown in Fig.8, is wide enough and becomes as large as the distance 136 in Fig.17, a conventional via can be substituted for the top level via. This option is beneficial for several reasons. First, while the developmental costs of the top level via process are smaller than a conventional process, the production costs of the conventional process may be smaller. If this comparison is true, then there is a production volume large enough to make the conventional process less expensive. Restricting the distance 136 to be sufficiently large to handle this possibility allows the use of common base wafers for both processes. The patterning for the conventional via involves only shifting of the top level via pattern in the direction of the lower metal edge 114 A. The second advantage of making the distance 136 compatible with a conventional via is that users of the design may choose to manufacture the IC at a conventional foundry. This flexibility is often desired by ASIC customers.

The third alternative stmcture to be discussed is almost identical to the preferred stmcture shown in Figs.6 Fig. 16, and is modified by the removal of the top dielectric film 211 shown in those diagrams. As discussed above, dielectric film 211 provides a means for accomplishing the liftoff of the thin catalyst film and provides a spacer 122 that reduces the severity of the sidewall angle of the dielectric below the edge of the upper conductor 212. As mentioned previously, the full continuity of the catalyst over this sidewall does not appear to be required to achieve continuity of the metal strap 216 deposited by electroless plating; therefore, the sidewall spacer 222 is not an essential part of a successful stmcture. With modifications and restrictions on the process, the tri-layer resist may be used instead of the top dielectric to provide the undercut angle required to break the continuity of the deposited metal at the pattem edge and enable the liftoff to occur. Fig 18 illustrates the construction of a top level via without using a top dielectric film. In this case, the inorganic etch template 226 must be thick enough to fully withstand the etching of both the organic release layer 224 and the interconductor dielectric 215. The undercut of the organic release layer 224 directly below the etch template 226 provides the retrograde angle for the liftoff. This undercut should be large enough to prevent the deposition of the catalyst on the sidewall of the release layer 224 and can be accomplished by oxygen reactive ion etching of the organic release layer at high pressure and temperature.

The contamination of the deposited metal, discussed above, must be addressed in order to use this method successfully. This problem is caused by the outgassing from the release layer sidewall of water vapor or other contaminants trapped within the release layer by the vapor-impermeable inorganic etch template. One solution applicable with an impermeable etch template is to bake the wafers for several hours in the evaporation chamber vacuum to exhaust the supply of contamination. Another solution is to replace the impermeable etch template with a gas-permeable etch template that allows the rapid removal of the contamination during the first stages of the vacuum chamber pumpdown. Spin-on glasses and chemically modified resists have been shown to work in this application but do not have the high resistance to oxygen RIE etching of the hard etch templates. This deficiency leads to higher etch biases and reduced interconnect density. Fig. 18 illustrates the use of a thicker gas-permeable etch template 226 to pattem the catalyst metal without the top dielectric film. The elements in Fig. 18 which are similar to that in Figs.6-16 have the same reference numerals.

Although the process is viable, the increased process times and costs and reduced interconnect density make this process less attractive than the one discussed in the previous section. However, the structure described in this section could be used to directly lift off the strap metal, which could be deposited in place of the catalyst film. It is well known that thick directionally evaporated films can be lifted off, but suffer from thinning of the metal deposited on vertical structures. This poor step coverage can lead to yield reduction and long term reliability problems due to electromigration. Therefore, this process could be used but is not as attractive as the preferred embodiment described in the previously.

Alternative processes that can be used to implement the top level via stmcture mentioned above in connection with Fig. 18 is now described. These processes are illustrated in Figs. 19 and 20. Elements in Figs. 19 and 20 which are similar to those in Figs. 10 to 16 have the same reference numerals. The common element of this implementation is that a blanket coating of the conductive 216 strap material is performed after making the via hole, e.g., after etching of the interconductor 215 and top dielectrics as shown in Fig. 14. The organic release layer 224 is removed by immersion in a solvent, and the conductive strap material 216 is deposited over the entire surface as in Fig. 19. The metal deposition can be performed in this case by any of the well known thin film deposition techniques including vacuum evaporation, sputtering, chemical vapor deposition, electroless plating, or electroplating. The main requirement of the deposition process chosen is that it must cover the steep edge composed of the sidewall of the upper conductor 212 and the interconductor dielectric 215 below it. All of the techniques mentioned above are capable of covering this step; however, some, in particular the evaporation technique, may lead to thinning of the deposited film along the sidewall. This deficiency could lead to long term electromigration failures if the current through the link is not adequately limited. Fig.20 illustrates a method of patterning the top level via, which involves repeating the top level via pattern in a photoresist 238 that is then used as a mask for the wet or RIE etch used to remove the strap conductor material 216 from the areas surrounding the top level via.

A Top Level Via With A Hidden Conductive Strap

Figs.21 to 23 show yet another structure which can be fabricated based on the high degree of conformality available in chemical vapor deposition of tungsten. Elements in Figs.21 to 23 which are similar to those in Figs. 10 to 16 have the same reference numerals. The initial part of the process used is similar to the one described by the first section and by Figs. 10 to Fig. 14. The alternative process begins with a wet etch of the interconductor oxide with the organic release layer in place, leading to the configuration shown in Fig.21. The purpose of this etch is to create a large undercut 238 of the upper conductor 212, thereby exposing the bottom surface of the upper conductor directly above the exposed surface of the lower conductor 214. Fig.22 shows a fully conformal coating of a conductive strap material that coats even the retrograde surfaces of the structure. CVD and PECVD deposition of tungsten and silicon at high pressure can lead to conformance of high degree.

Fig.23 shows the final stmcture after anisotropic etching of the blanket film. A metal strap 240 formed by the protecting overhang of the upper conductor 212 makes the electrical connection between the upper 212 and lower 214 connector. The metal strap 240 forms a physical contact to the upper conductor in the form of a sidewall metal along the sidewall 240A of the upper conductor. This surface is not required to make a low resistance electrical connection since a low resistance connection has already been made by the strap conductor contacting the exposed bottom surface 240B of the upper conductor. The strap conductor 240 then forms a bridge that crosses the sidewall 240C of the interconductor dielectric 240C and makes contact to the upper surface 240D of the lower conductor.

The edges of the top level via that were defined by resist will also have a spacer-like deposit 240B of the strap conductor that remains after the etching. It should be noted that the strap metal along surface 240A is not restricted to the top level via region but will be found on all edges of the upper conducting wires. This design causes no problem beyond a slight increase in wiring capacitance; however, it is clear that shorting between multiple upper conductor wires can occur if dielectric ridges reflecting the any topography from the lower conductor is present during this process. Because the electrical connection does not depend on the existence of the sidewall metal or sidewall contact, and because the connection point is fully protected by the upper conductor, the strap conductor may be overetched to the extent that the sidewall metals 240A and 240E are completely removed. This long overetch may remove a significant amount of the exposed interconductor dielectric 215. In order to completely solve this problem, it is better to restrict this process to substrates that have a very high degree of planarization of the lower conductor level. The process-related costs of this requirement make this alternative less attractive than the one described in the first section. Connections Between Two Upper Conductors Using A Single Nested Top Level Via

Fig.24 shows a method of connecting two upper conducting wires with a single nested top level via. Elements in Fig.24 which are similar to that in Figs. 10-16 have the same reference numerals. As defined above, the nested top level via must have conductor filling its entire area to prevent shorting to the substrate 210. Therefore, a lower metal conductor bridge 214 must be placed between the two upper conductor wires, shown as 212 A and 212B, to facilitate the crossing of the strap metal 216 without shorting it to the substrate 210. The rules for overlap of the lower conducting edge with the upper conductors are the same as presented above. It should be noted that even though Fig.24 only shows two upper conductor wires 212A and

212B, the invention can be extended to the case of more than two upper conductor wires.

A Non-Nested Top Level Via

The specification of the nested top level via as mentioned previously was made in such a way that the top level via pattern contained no area within its boundaries that was not covered by either the upper or lower conducting films. As is shown in Figs. 10 to 16, this design feature was established in order to prevent the reactive ion etch of the interconductor dielectric 215 from removing any portion of the lower dielectric 213. If the lower dielectric 213 is removed during this etch, the strap conductor 216 could come in physical and electrical contact with the substrate 210, thereby causing an undesired electrical connection between the conducting wires 212 and 214 and the substrate 210. This concern is not present if the interconductor dielectric 215 can be etched in a reactive ion chemistry that will not etch the lower dielectric 213. If, for example, the interconductor dielectric is a polymer material, it can be etched in oxygen RIE, which will not etch a silicon dioxide film used as the lower dielectric. The lower bound of the nested top level via size is limited by the requirement that metal borders exist on all sides of the via (see Fig.6). The non-nested via presents no such requirement, permitting narrower wires to be connected and decreasing the minimum spacing between unrelated vias (via pitch).

Fig.25 illustrates several of the many ways to arrange a non-nested top level via 320 used for connecting a upper conductor 312 and a lower conductor 314. Since the overall design density is a critical function of the top level via pitch, the non-nested top level via enables more logical function and interconnect per unit area of the integrated circuit. In addition to this benefit the non-nested via enables several other useful structures such as the top level via connection for two lower conductors. These will be described in later paragraphs. The vertical design and process for a non-nested via is very similar to the process described for the nested top level via except that because the interconductor dielectric is polymeric, it must be etched using an oxygen RIE process. As described above, the inorganic etch template must be removed before the liftoff process. Rather than etching it simultaneously with the interconductor dielectric, the non-nested top level via process flow should remove it by application of a CF4 or SFg RIE after the dielectric has been removed.

Fig.26 shows a method of connecting two upper conducting wires 412A and 412B with a single non-nested top level via 420. Via 420 is surrounded by a top dielectric 411, two upper metal wires 412A and 412B, a substrate 410, and two insulating layers 413 and 415. Because excursions of the strap metal 416 across areas not covered by conductor are allowed in the non-nested top level via process, the lower conductor bridge illustrated in Fig.24 is not required in this case. The etch of the top level via will stop on the lower dielectric and the strap may cross between the wires without the danger of shorting to the substrate.

Fig. 27 shows a method of connecting two lower conducting wires 414A and 414B with a single non-nested top level via 420. Elements which are similar in Figs.26 and 27 have the same reference numerals. The etching of the top level via stops on the lower dielectric 413, and the strap 416 may cross between the wires without the danger of shorting. It should be understood that while the present invention has been specifically set forth and described with reference to the preferred embodiments, it will be readily appreciated by those skilled in the art that many changes in form and detail may be made without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

What Is Claimed Is:

1. A semiconductor device having a plurality of layers comprising: a first layer; an insulating layer disposed on said first layer; a first conductive wire disposed on said insulating layer, said first conductive wire having a surface substantially parallel to and located away from said insulating layer; a second conductive wire disposed on one of said plurality of layers, said second conductive wire having a surface substantially parallel to said insulating layer; a through hole having a first opening, sidewalls substantially perpendicular to said first opening, and a second opening bounded by said sidewalls and contacting said first layer; a portion of said first and said second conductive wires being positioned at the periphery of said through hole; and a conductive strap covering a portion of said surfaces of said first and said second conductive wires, at least a portion of said sidewalls, and at least a portion of said second opening of said through hole for providing electrical communication between said first conductive wire and said second conductive wire.

2. The device of Claim 1 further comprising a dielectric sidewall spacer having a first portion contacting a portion of said sidewalls of said through hole, a second portion contacting a portion of said first conductive wire, and a third portion contacting a portion of said second conductive wire.

3. The device of Claim 1 wherein said insulating layer comprises a material that can be removed by an etchant and wherein said first layer comprises an insulating material that is not substantially etched by said etchant.

4. The device of Claim 1 wherein said insulating layer comprises a material that can be removed by an etchant and wherein said first layer comprises a conducting material that is not substantially etched by said etchant.

5. The device of Claim 1 wherein said conductive strap comprises: a catalyst layer disposed on a portion of said surfaces of said first and said second conductive wires, said portion of said sidewalls, and said portion of said second opening; and a metal film disposed by electroless plating onto said catalyst layer.

6. The device of Claim 1 wherein said conductive strap comprises: an adhesion layer disposed on a portion of said surfaces of said first and said second conductive wires, said portion of said sidewalls, and said portion of said second opening; a catalyst material layer disposed on said adhesion layer; and a metal film disposed by electroless plating onto said catalyst layer.

7. A semiconductor device having a plurality of layers comprising: a first dielectric film having a surface; at least one lower conductive wire having a first surface contacting said surface of said first dielectric film and a second surface located away from said first surface; a second dielectric film disposed on said surface of said first dielectric film, said second dielectric film having a first surface contacting a portion of said lower conductive wire and a second surface separated from said first surface; a through hole having a first opening located at said second surface of said lower conductive wire, sidewalls substantially perpendicular to said first opening, and a second opening bounded by said sidewalls and located at said second surface of said second dielectric film; at least one upper conductive wire disposed on said second surface of said second dielectric film and having a portion located at the periphery of said through hole, said upper conductive wire having a surface substantially parallel to said second surface of second dielectric film; and a conductive strap covering at least a portion of said first opening, at least a portion of said sidewalls, and at least a portion of said surface of said upper conductive wire, thereby providing electrical communication between said lower conductive wire and said upper conductive wire.

8. The device of Claim 7 further comprising a dielectric sidewall spacer having a first portion contacting a portion of said sidewalls of said through hole and a second portion contacting a portion of second surface of said upper conductive wire.

9. The device of Claim 7 wherein said second dielectric film comprises a material that can be removed by an etchant and wherein said first dielectric film comprises a material that is not substantially etched by said etchant.

10. The stmcture of Claim 8 wherein said second dielectric film and said dielectric sidewall comprise materials that can be removed with an etchant and wherein said first dielectric film comprises a material that is not substantially etched by said etchant.

11. The device of Claim 7 wherein said conductive strap comprises: a catalyst layer disposed on a portion of said surfaces of said first and said second conductive wires, said portion of said sidewalls, and said portion of said second opening; and a metal film disposed by electroless plating onto said catalyst layer.

12. The device of Claim 7 wherein said conductive strap comprises: an adhesion layer disposed on a portion of said surfaces of said first and said second conductive wires, said portion of said sidewalls, and said portion of said second opening; a catalyst material layer disposed on said adhesion layer; and a metal film disposed by electroless plating onto said catalyst layer.

13. A method for fabricating a via-like stmcture in a semiconductor device having a middle layer disposed on top of a bottom layer, said middle layer having a first region on which a top layer is disposed and a second region, said top layer having a top surface which is substantially parallel to and located away from said middle layer, said method comprising the steps of: forming an insulating layer on said top surface of said top layer and on said second region of said middle layer; forming a first mask layer having a first surface in contact with said insulating layer and a second surface which is substantially parallel to and located away from said top surface; forming a second mask layer on said second surface of said first mask layer, said second mask layer having a portion removed for defining the boundary of said via-like stmcture, said removed portion located above a portion of said top surface of said top layer and a portion of said second region of said middle layer ; etching said semiconductor device using said removed portion of said second mask layer as a mask for creating a hole having interior surfaces comprising surfaces of said bottom, said middle and said top layers, said etching step further exposing a portion of said top surface of said top layer; depositing a catalyst film on said semiconductor device for covering said first mask layer, said interior surfaces of said hole, and said exposed portion of said top surface of said top layer; lifting off said first mask layer; and exposing said semiconductor device to an electroless plating solution, said solution forming a conducting strap on said catalyst film.

14. The method of Claim 13 wherein said first mask layer comprises an organic release layer.

15. The method of Claim 13 wherein said second mask layer comprises a photoresist deposited on top of an inorganic etch template.

16. The method of Claim 13 wherein said etching step comprises the steps of: etching said first mask layers using said removed portion of said second mask layer as a mask; etching said insulating layer using said etched first mask layer as a mask; and etching said middle layer using said etched first mask layer as a mask.

17. The method of Claim 16 wherein said step of etching said insulating layer includes the step of creating a sidewall spacer on a portion of said interior surfaces of said hole.

18. The method of Claim 16 wherein said step of etching said first mask layer comprises an anisotropic reactive ion etching in oxygen.

19. The method of Claim 16 wherein said step of etching said middle layer comprises a reactive ion etching.

20. The method of Claim 13 further comprising the step of removing said second mask layer, said removing step being performed before said step of depositing said catalyst film.

21. The method of Claim 13 further comprising the step of removing native and plasma grown oxide from said exposed portion of said top surface of said top layer, said removing step being performed before said step of depositing said catalyst film.

22. The method of Claim 13 wherein said catalyst film comprises a palladium film.

23. The method of Claim 13 wherein said depositing step comprises evaporative deposition.

24. The method of Claim 13 wherein said step of lifting off said first mask layer comprises the step of immersing said semiconductor device in a solvent for removing said first mask layer.

25. The method of Claim 24 wherein said first surface of said first mask layer has an undercut portion which is located above said exposed portion of said top surface of said top layer.

26. The method of Claim 13 wherein said electroless plating solution selectively reduces metal ions in said solution onto said catalyst film.

27. The method of Claim 26 wherein said electroless plating solution comprises an aqueous source of metal ions, a reducing agent, a complexing agent, and a stabilizer.

28. A method for fabricating a via-like structure in a semiconductor device having a middle layer disposed on top of a bottom layer, said middle layer having a first region on which a top layer is disposed and a second region, said top layer having a top surface which is substantially parallel to and located away from said middle layer, said method comprising the steps of: forming a mask layer having a portion removed for defining the boundary of said via-like stmcture, said removed portion located above a portion of said top surface of said top layer and a portion of said second region of said middle layer; etching said semiconductor device using said removed portion of said mask layer as a mask for creating a hole and for exposing a portion of said top surface of said top layer, said hole having interior surfaces including surfaces of said bottom, said middle and said top layers; depositing a catalyst film on said semiconductor device for covering said interior surfaces of said hole and said exposed portion of said top surface of said top layer; removing said mask layer; and exposing semiconductor device to an electroless plating solution, said solution forming a conducting strap on said catalyst film.

29. The method of Claim 28 wherein said etching step comprises the steps of: etching said first mask layers using said removed portion of said second mask layer as a mask; and etching said top and said middle layer using said etched first mask layer as a mask.

30. The method of Claim 28 further comprising the step of removing native and plasma grown oxide from said exposed portion of said top surface of said top layer, said removing step being performed before said step of depositing said catalyst film

31. The method of Claim 28 wherein said catalyst film comprises a palladium film.

32. The method of Claim 28 wherein said depositing step comprises evaporative deposition.

33. The method of Claim 28 wherein said lifting step comprises the step of immersing said semiconductor device in a solvent for removing said first mask layer.

34. The method of Claim 28 wherein said electroless plating solution selectively reduces metal ions in said solution onto said catalyst film.

35. The method of Claim 28 wherein said electroless plating solution comprises an aqueous source of metal ions, a reducing agent, a complexing agent, and a stabilizer.

36. A method for fabricating a via-like stmcture in a semiconductor device having a middle layer disposed on top of a bottom layer, said middle layer having a first region on which a top layer is disposed and a second region, said top layer having a top surface which is substantially parallel to and located away from said middle layer, said method comprising the steps of: forming an insulating layer having a first surface in contact with said top surface of said top layer and with said second region of said middle layer and having a second surface which is substantially parallel to and located away from said top surface of said top layer; forming a mask layer on said second surface of said insulating layer, said mask layer having a portion removed for defining the boundary of said via-like structure, said removed portion located above a portion of said top surface of said top layer and a portion of said second region of said middle layer; etching said semiconductor device using said removed portion of said second mask layer as a mask for creating a hole and for exposing a portion of said top surface of said top layer which is adjacent to said hole, said hole having interior surfaces including surfaces of said bottom, said middle and said top layers; removing said mask layer; depositing a strap metal on said second surface of said insulating layer and said interior surfaces of said hole; and removing a portion of said strap metal on said second surface of said insulating layer surrounding said hole.

37. The method of Claim 36 wherein said step of removing said portion of said strap metal surrounding said hole comprises the steps of: depositing a photoresist on said deposited strap metal; patterning said photoresist such that said surrounding portion of said strap metal is not covered by said photoresist; and etching said photoresist and said strap metal for removing said surrounding portion of said strap metal.

38. A method for fabricating a via-like structure in a semiconductor device having a middle layer disposed on top of a bottom layer, said middle layer having a first region on which a top layer is disposed and a second region, said top layer having a bottom surface in contact with said first region of said middle layer and a top surface which is substantially parallel to and located away from said first region of said middle layer, said method comprising the steps of: forming a mask layer on said top surface of said top layer and on said second region of said middle layer, said mask layer having a portion removed for defining the boundary of said via-like structure; said removed portion located above a portion of said top surface of said top layer and a portion of said second region of said middle layer; etching said semiconductor device using said removed portion of said mask layer as a mask for creating a hole, said hole having interior surfaces including surfaces of said bottom and said middle layers; removing said mask layer; depositing a strap metal on said top surface of said top layer, said second region of said middle layer and said interior surfaces of said hole; and removing said strap metal from said top surface of said top layer and said second region of said middle layer.

39. The method of Claim 38 wherein said removing step comprises an anisotropic reactive ion etching.

40. The method of Claim 38 wherein said etching step including the step of etching away a portion of said middle layer below a portion of said bottom surface of said top layer for creating an undercut region.