WO1995002903A1

WO1995002903A1 - Contact programmable wiring and cell array architecture

Info

Publication number: WO1995002903A1
Application number: PCT/US1994/007096
Authority: WO
Inventors: Mark D. Kellam; Gershon Kedem; Krzysztof A. Kozminski
Original assignee: Astarix, Inc.
Priority date: 1993-07-15
Filing date: 1994-06-23
Publication date: 1995-01-26

Abstract

Intergreated circuits with architecture resembling a row-based array are prefabricated up to, and including, the metallic interconnection, and stocked. To fabricate a prototype of an Application-Specefic IC, a single application-specific mask is used to connect wires existing on a prefabricated IC with Top Level Vias (via-like connecting structures, TLV), upon which the prototype may be passivated, bonded, packaged, and tested. For mass-production of an Application-Specific IC, a typical IC fabrication process is employed, using the same masks are used as for the prefabricated ICs, with the exception of the mask of vias for connecting the metal interconnection layers, which is modified to produce the same connections as those introduced by the TLVs added during the prototyping. The single-mask-programmable aspect of the invention is facilitated by the general-purpose wiring channels (220) adjacent to rows of programmable cells (211). Channels (220) comprise wiring patterns (222A and 222B), each containing a grid of two levels of initially unconnected wires, positioned so as to facilitate using either conventional vias or the TLVs for connecting wires within each pattern, wires in a pattern to wires in an adjacent pattern, and wires in a pattern to wires in an adjacent programmable cell (211). Programmable cells (211) are designed so as to facilitate implementing a set of different logical functions with appropriately positioned conventional vias or TLVs. As a result, the cost and time required for fabrication of a prototype are reduced, and the conversion to mass-production is simplified over typical methods uses in prior art.

Description

Contact Programmable Wiring And Cell Array Architecture

Field of the Invention

The present invention relates generally to integrated circuits. More particularly, this invention relates to integrated circuits containing programmable portions and methods for selectively programming the same.

Background of the Invention

Continuing technological advances in the degree of integration of electronic circuitry allow semiconductor designers to increase the function capacity, reliability, and performance (e.g., speed) of integrated circuits, while simultaneously reducing their power consumption, size, and unit cost. Consequently, application opportunities for integrated circuits have grown at an astounding rate. Integrated circuits (ICs) consist of many circuit elements (e.g., transistors) and interconnecting wires fabricated at the surface of a semiconductor substrate. ICs can be broadly divided into two categories: General-Purpose ICs and Application-Specific Integrated Circuits (ASICs). General- purpose ICs, such as microprocessors or memories, are usually designed by IC manufacturers and mass-produced in millions of units. These general-purpose ICs are intended to be used in a large variety of electronic systems. On the other hand, ASICs are designed to perform specialized logical or algorithmic functions and are intended to be used only in certain types of electronic equipment. Typically, ASICs are designed by the developers of electronic equipment rather than by semiconductor manufacturers.

Frequently, ASICs are designed to replace a number of separate ICs (e.g., gates, counters, and flip flops) by integrating them as a single integrated circuit. This reduces the size and power consumption of the resulting electronic equipment. Furthermore, use of ASICs increases the equipment reliability by reducing the number of ICs and interconnections among them, each of which contributes to the overall probability of failure. Consequently, the overall cost of the system, which includes the costs of the ASIC and circuit board, assembly cost, and maintenance cost, may decrease even if the cost of the ASIC itself is higher than the costs of the replaced ICs. In summary, the application-specific nature of each ASIC and the associated opportunity to fine-tune the ASIC's design result in the improved performance (e.g., speed), reliability, and, usually, lower cost of electronic equipment employing ASICs as compared to that using general-purpose ICs.

Electronic system manufacturers must consider several tradeoffs in deciding whether to use an ASIC in a particular product. These tradeoffs involve: (1) the cost and time required to design, produce, and test one or more prototypes of the ASIC, (2) the cost and time required to manufacture the desired quantities of the ASIC, and (3) the expected reliability, performance, and cost of the product employing the ASIC as compared to that employing alternative ICs. Recent advances in ASIC design include major efforts to increase ASIC performance and reliability and to decrease ASIC prototyping costs, volume production costs, and development time. Frequently, tradeoffs involving these factors are necessary; e.g., reducing the development and turnaround time may increase the cost of an ASIC prototype or worsen the performance. The ASIC development time includes the time needed to produce the initial design and, usually, one or more design iterations which are necessitated by design errors and/or changes in design specification. The time needed for a single design iteration is called the "turnaround time". The turnaround time includes the time it takes to test a prototype ASIC, locate errors and/or introduce design changes in the prototype, and fabricate a new version of the ASIC. The development and turnaround times are important factors in the decision to implement an ASIC. This is because of the economical pressure to introduce new products as quickly as possible, since early product introduction often results in significant gains in sales and market share.

The IC manufacturing costs are generally classified as Non-Recurring Engineering (NRE) costs (also referred to as "fixed" costs) and "variable" (also referred to as "production") costs. The NRE costs include (1) the engineering effort required to design and ascertain the correctness of a new

ASIC product, (2) the cost of masks needed to produce the circuit, (3) the design-specific set-up costs incurred during the ASIC fabrication, and (4) the cost of fabricating the prototypes. The variable costs include (1) the cost of materials needed for fabricating the ICs, and (2) amortization of the enormous investment in capital equipment required to manufacture ICs. The NRE costs are one-time-only costs and are usually negligible for general-purpose ICs, since they can be amortized over the millions of manufactured IC units and are paid for by all users of these ICs. ASICs, on the other hand, are usually fabricated in relatively small quantities (e.g., from a few hundred to as many as a few hundred thousand parts per year) and, therefore, the NRE costs contribute significantly to the total cost of each ASIC unit. This frequently creates a barrier preventing the use of ASICs in electronic products that may not have a high volume of sales or have an unknown market appeal.

For some types of ASICs (such as the Full Custom type described below), the NRE cost of each design iteration may be of the same order of magnitude as the NRE cost of the initial design development. This is an additional deterrent preventing many small electronic equipment manufacturers from using ASICs, because the risk of unexpected design iterations may not be acceptable.

In view of the above considerations, there is a need for a new method for designing and producing high-performance ASICs which has low NRE costs and short development time.

There are at least four types of ASICs: (1) Full Custom, (2) Standard Cell, (3) Gate Array, and (4) Field Programmable Gate Arrays (FPGA). The characteristics of these types of ASICs differ significantly from each other. The first three types can be grouped together into the class of mask- programmable devices, because they require the use of design-specific and expensive masks at the semiconductor factory. These masks (also called device-dependent, batch-dependent, or discretionary), contain circuit patterns that are transferred, by means of photolithographic processes, onto dielectric, conducting, and semiconductor layers disposed on the IC substrate. The patterns on these layers form transistors and interconnections which comprise an IC. The last type of ASICs, FPGAs, do not require the use of discretionary masks. The relative merits of these four types of ASICs are discussed below.

Full Custom ICs are hand-crafted, frequently requiring many man-years of engineering effort for the initial design and up to several man-months per design iteration. These ICs have the highest NRE costs of all ASIC types: each design iteration requires a full set of expensive discretionary masks, the number of which usually ranges from about ten to twenty. In addition, it is difficult to use computer-aided design (CAD) software tools in Full Custom design, although CAD software tools are typically used to perform design verification tasks. As a result, the design and production of these ICs are expensive and time-consuming. On the other hand, Full Custom ASICs exhibit the highest transistor density and best performance due to the hand-crafted design, as well as the lowest variable costs. Full Custom ASICs are usually the best choice for ASICs that are manufactured in hundreds of thousands or more units and /or for which the performance is of the utmost importance.

Standard Cell ICs are assembled from libraries of hand-crafted components. These components have standardized shapes and interfaces; hence, CAD software can be extensively used in circuit synthesis as well as in mask generation (for placement and routing of the ICs components), thereby reducing the design time and engineering effort. As an example, the initial design may take as little as several man-months (as compared to several man-years for Full Custom ICs). Thus, the portions of the NRE costs related to the design engineering are reduced. Nevertheless, each design iteration requires a full set of discretionary masks, at costs comparable to those of the Full Custom ASICs. Furthermore, as each design iteration involves a full IC manufacturing process, the turnaround time may be as long as two to four months. The transistor density of Standard Cell ASICs is lower, the performance is not as high, and the variable costs are higher than those of the Full

Custom ASICs. At the present time, Standard Cell ASICs are usually economical to produce in quantities of several dozen thousands or more.

Gate Array ASICs involve fabrication of pre-designed "base wafers" that contain identical integrated circuit elements (gates or transistors). An ASIC user "customizes" the gate array by specifying only the additional conductive wiring patterns and contacts used to interconnect gates that have been prefabricated on the base wafer. The cost of design and layout, design-independent masks, and the fabrication set-up and overhead costs of the base wafer are shared among all subsequent "customizing" users.

CAD software is used extensively in the design of Gate Array ASICs. As a result, the engineering efforts in the initial design of Gate Array and Standard Cell ASICs are comparable. On the other hand, the NRE costs associated with each design iteration of Gate Array ASICs are lower than those of Standard Cells because Gate Arrays require fewer customizing masks per iteration. Furthermore, the turnaround time is reduced to as little as two to four weeks because only the final part (i.e., customizing) of the IC manufacturing process needs to be performed. One type of Gate Array ASICs with a special architecture required only the upper layer of metal interconnections to be fabricated, with further reduction in the turnaround time and cost. Generally, the transistor densities of Gate Array ASICs are lower, the performance is worse, and the variable costs are higher than those of the Standard Cell ASICs. At the present time, Gate Array ASICs are usually economical to produce in quantities of several thousand units or more.

While some semiconductor factories offer reduced turnaround times for all of the above mentioned ASIC types that use discretionary masks, the premiums charged for such services are considerable. As a result, such services are not routinely used. Field Programmable Gate Arrays (FPGAs) contain logic cells, each of which can perform a number of different functions. These cells are connected using a reconfigurable interconnecting grid. The cells are user-programmable, i.e., the particular function performed by each cell can be set after the FPGA is manufactured. In addition, the interconnecting grid is programmable as well, i.e., it can be arranged to connect the programmed cells in an appropriate manner, so that the FPGA performs the desired function.

One method of programming FPGAs is to use memory-based lookup tables for implementing various functions, and use pass-transistors as switches for transferring signals between various interconnecting lines. These transistors are connected to memory cells whose contents determine whether each transistor acts as an open or a closed switch. A user programs the FPGA by setting the values of the memory cells. The FPGA function can be changed by entering new values into the appropriate memory cells. Another method of programming FPGAs involves the use of anti-fuses, which are one-time programmable switches. Each anti-fuse is nominally unconnected but can form a permanent conductive link after the application of a programming voltage across that anti-fuse. The first method (i.e., using memory elements and pass-transistors) has the advantage of being reprogrammable by changing the values of the associated memory cells. However, the pass- transistors introduce considerable series resistance into the interconnecting wires and severely limit the speed at which such ICs can operate correctly. Even though the anti-fuses used in the second method exhibit somewhat lower series resistance than the pass-transistors, the resistance is still higher (and the performance is worse) than that available from the metallic interconnects used in the Gate Array ICs. Both the first method (i.e., using memory elements and pass-transistors), and, to a somewhat lesser degree, the second method (i.e., using anti-fuses) suffer a considerable density penalty because of the need to use additional areas to fabricate the actual switch and the control circuitry that programs the switching.

CAD software tools are also used extensively by FPGA users to program the desired functions. However, as pointed out above, FPGAs have lower circuit density and poorer performance when compared with Gate Arrays and Standard Cell ICs. Thus, it may take several FPGAs (and, possibly, other general-purpose ICs for interfacing among these FPGAs) to accomplish the function of a single Gate Array or Standard Cell IC. As a result, the initial engineering effort to design a FPGA implementation (including interface circuits to connect the FPGAs), may be higher than that of the Gate Array and Standard Cell ICs because additional effort may be needed to consider interactions among the multiple FPGA chips. There would be no such need if the design could fit in a single IC. The FPGA turnaround time is practically reduced to the time it takes to identify and introduce a required change in the design. The time required by CAD software tools to implement a change does not normally exceed several hours and may be as short as several minutes. The actual programming of an FPGA normally takes less than a minute. As a result, one to two design iterations per day may be feasible. Furthermore, the NRE costs associated with each iteration are very low, typically including the cost of several hours of engineering time and, possibly, the cost of a one-time programmable FPGA device.

In addition to poor performance and low circuit density, FPGAs do not exhibit the economy of scale. The cost of FPGAs decreases only slowly with volume. As mentioned earlier, the low capacity of FPGAs may require that several FPGA units be used to implement a circuit which could fit in a single Gate Array or Standard Cell ASIC. As a result, FPGAs are economical to use in quantities of several hundred to a few thousand. Frequently, they are used to build prototype products for gaining early entry into a market and acquiring the high visibility resulting from such entry. The FPGAs often are replaced with Standard Cell or Gate Array ASICs once the product has found acceptance in the marketplace. In the migration from FPGAs to Standard Cells or Gate Arrays, there is little savings in the NRE costs compared to the case in which FPGAs are not initially used, except that there may be a reduction in the number of design iterations.

In summary, Full Custom and Standard Cell ASICs require months or even years to design and prototype. Minimum NRE costs start at $50,000 and may exceed $1,000,000 per design (in today's dollars). The production costs are typically low. Gate Array ASICs trade off transistor density and performance to achieve significant advantages in prototype turnaround time (two to four weeks) and NRE costs (starting at approximately $20,000 in today's dollars). The production costs are higher than those of the Full Custom and Standard Cell ASICs. Nevertheless, Gate Array ASICs make a relatively low volume production viable. FPGAs provide costs and turnaround time advantages for prototype production, but the high unit cost often eliminates them as an alternative to gate arrays for mass- production quantity. Consequently, in the semiconductor market, there is a need for an ASIC methodology that would exhibit low cost and rapid turnaround times approximating those of FPGA prototyping and, at the same time, provide increased transistor density, higher circuit speed, easy migration path from prototype to production, and economical mass-production costs.

Summary of the Invention

The present invention combines the desirable characteristics of FPGAs and Gate Array ICs through, in part, architectural and programming innovations. The objects and advantages of this invention are the reductions of cost, risk, and production time of manufacturing Application Specific Integrated Circuits.

Broadly stated, the invention is a new architecture for a semiconductor device and a method for programming the same. In accordance with this invention, a plurality of substantially identical semiconductor devices is fabricated. Each of the substantially identical semiconductor devices comprises mask- programmable (i.e., mask-configurable) cells, mask-programmable wiring patterns, mask- programmable input/output (I/O) pads, and mask-programmable coupling sites for electrically connecting conducting wires. These coupling sites can be selectively programmed into either a "connected" ("closed") or a "disconnected" ("open") state by using a single discretionary programming mask to produce connection means at the selected coupling sites. T e normal state of the coupling sites is "disconnected", and a programming mask is used to select those coupling sites that should become "connected". Each of the substantially identical semiconductor devices can be mask-configured to perform any one of a number of potentially available electrical functions. A batch of semiconductor devices is selected from the substantially identical semiconductor devices. Each member of the batch is programmed by using the same batch-dependent (design-specific) mask to induce a "connected" state in an appropriately selected subset of coupling sites. As a result, the semiconductor devices in the batch have electrical connections appropriate for performing one of the potentially available electrical functions. Similarly, other batches can be selected with each batch being programmed by a single batch-dependent mask to perform a desired electrical function.

The term "mask", as used in the present invention, is not limited to a physical mask. It refers to a pattern transferred to a layer (comprising an integrated circuit) in a single patterning operation (step) during IC fabrication. Examples of patterning operations are (1) exposure of a photoresist by radiation passed through a mask patterned with appropriately located opaque and transparent areas, or (2) exposure of a photoresist by an electron-beam pattern generator.

One of the novel aspects of the present invention is that it enables IC device customization in a fabrication process using just one discretionary technological step, where this discretionary step selectively defines batch-dependent contacts (or vias) among non-discretionary (i.e., identical for all designs) conducting layers. A process using just one discretionary technological step is also referred to as "single-step customization". Note that single—step customization may comprise any number of non-discretionary steps.

This invention also relates to a method of manufacturing coupling sites that can be programmed into the "connected" state by using, as the connection means, either a conventional contact between two conducting areas (frequently called a "via" when referring to a contact between two layers of metal) or a new Top Level Via. Furthermore, a change from using the conventional contact to the Top Level Via as a structure for programming the coupling sites requires only a change of the discretionary mask, and does not require any changes in the other masks used to manufacture the semiconductor devices. In summary, it is an object of the present invention to provide an improved architecture and an improved method for programming semiconductor devices.

It is another object of the present invention to provide means for fabricating flexible and high performance semiconductor devices with lower NRE costs and shorter turnaround time than Gate Arrays.

It is also an object of the present invention to reduce the resistance and capacitance of the programmable interconnections in programmable semiconductor devices as compared to Field Programmable Gate Arrays, thereby increasing their speed.

It is a further object of the present invention to reduce the area of programmable interconnections of programmable semiconductor devices as compared to Field Programmable Gate

Arrays, thereby increasing the density of the devices.

It is yet another object of the present invention to facilitate IC customization using a single discretionary mask specifying the contacts among design-independent interconnection patterns.

It is yet another object of the present invention to increase the interconnection density of ICs customized with a single discretionary mask.

It is yet another object of the present invention to facilitate low-risk migration from a novel integrated circuit prototyping method to an industry-standard method of integrated circuit manufacturing.

The advantageous features of the present invention will be readily understood when taken in conjunction with the following description and drawings.

Brief Description of the Drawings

Fig. 1 is a block diagram of an exemplary Uncommitted Logic Array (ULA) device in accordance with the present invention.

Fig. 2 is a block diagram of the core area of the exemplary ULA device of Fig. 1.

Figs. 3A and 3B illustrate principles of signal routing in a programmable interconnect environment in accordance with the present invention.

Fig.4A illustrates a simple programmable wiring pattern in accordance with the present invention.

Fig.4B shows another simple programmable wiring pattern in accordance with the present invention.

Fig.4C shows the block diagram of a wiring channel which comprises the wiring patterns shown in Figs.4A and 4B in accordance with the present invention. Figs.5A-D show a conventional contact (via) and a Top Level Via which can be used in the wiring patterns of Figs.4A and 4B.

Fig.5E shows Top Level Via variations which can be used to connect non-overlapping metal wires. Figs.6A, 6B, and 6C show a wiring quilt, composed of wiring patterns of Figs. 4A and 4B, which can be used to implement wiring channels in a ULA device in accordance with the present invention.

Fig 6D shows alternative wiring patterns that can be used to compose the wiring quilt of Fig. 6B in accordance with the present invention.

Fig. 7 A shows a schematic diagram of a simple cell that can be used in a ULA device in accordance with the present invention.

Fig. 7B shows a composite drawing of the principal masks defining the simple cell of Fig. 7A.

Figs. 7C-E show drawings of the principal masks defining the simple cell of Fig. 7k, separated for better readability.

Fig. 7F shows a schematic diagram of another simple cell that can be used in a ULA device in accordance with the present invention.

Figs. 8 A and 8B show composite drawings of possible interfaces between logic cells and wiring channels comprising a ULA device in accordance with the present invention. Fig. 9A shows a schematic diagram of a portion of a ULA device in accordance with the present invention, utilizing programmable cells similar to those in Figs. 7A and 7E.

Figs. 9B and 9C show examples of accomplishing different logical functions by programming connections in the wiring channels of the ULA device shown in Fig. 9A.

Fig. 10A shows another embodiment of a simple programmable cell that can be used in a ULA device in accordance with the present invention.

Figs. 10B and IOC show examples of programming connections in the cell of Fig. 10A that accomplish different logical functions.

Fig. 11 shows a composite drawing of principal masks defining the simple cell of Fig. 7A using alternative mask-programmable connection means for wire connections. Figs. 12A and 12B show additional wiring patterns that can be used in the wiring channels and core of a ULA device in accordance with the present invention.

Fig. 13A shows the top view of a portion of a preferred wiring channel in accordance with the present invention.

Fig. 13B shows an example of programming connections of the wiring channel of Fig. 13A. Fig. 14 shows the preferred embodiment of an interface between a logic cell and a portion of the adjacent wiring channels.

Figs. 15A-E show the logical structure of the preferred embodiment of a programmable logic cell, as well as some examples of useful gates that can be fabricated from this cell by programming the coupling sites contained within the cell in accordance with the present invention. Fig. 16 shows the structure of the preferred embodiment of an Input/Output wiring channel in accordance with the present invention.

Fig. 17 is a schematic diagram showing the structure of a programmable NOR gate in accordance with the present invention. Figs. 18A and 18B illustrate the geometry of various layers of a portion of the programmable NOR gate of Fig. 17.

Fig. 19 is a schematic diagram showing an array of programmable NOR gates that can be used to form a PLA or ROM structure in accordance with the present invention.

Detailed Description of Preferred Embodiments

The following is a detailed description of the best presently contemplated modes for carrying out the invention. The description is intended to be merely illustrative of the invention and should not be taken in a limiting sense. The flexibility of the integrated circuit architecture in accordance with the present invention permits a substantial degree of freedom in designing the component parts (such as programmable cells, programmable wiring channels, programmable I/O pads, and programmable coupling sites comprised therein), as well as freedom in programming of mask-programmable integrated circuits. To illustrate that flexibility, a number of embodiments is presented. The preferred embodiments described herein relate to integrated circuits with two layers

(levels) of metallic interconnections. Extending the present invention to integrated circuits having other numbers of interconnect layers made of any suitable materials should be immediately apparent to those skilled in the art.

General Structure of Uncommitted Logic Array

Fig. 1 shows a block diagram of a preferred Uncommitted Logic Array (ULA) device 100. ULA device 100 is a monolithic integrated circuit designed to be partially pre-fabricated and later customized (i.e., mask-configured or mask-programmed) to complete the fabrication for different end-user applications. ULA device 100 comprises a core area 110 of mask-programmable logic structures surrounded by mask-programmable I/O wiring channels 101 which connect core area 110 to mask-programmable I/O buffers 102 located on the periphery of ULA device 100. I/O buffers 102 preferably contain the necessary interface circuitry for allowing connection of ULA device 100 to other devices (not shown) such that a larger electronic circuit can be formed. Fig.2 shows a block diagram of an exemplary core area 110. Core area 110 comprises rows

210, 210A, and 210B of mask-programmable cells 211. In between rows 210, 210A, and 210B are mask- programmable wiring channels 220. There are also wiring channels 220A and 220B located before the first row 210A and after the last row 210B, respectively. Cells 211 in rows 210, 210A, and 210B can be customized (mask-configured) to implement a variety of Boolean functions, flip flops, registers, and memory storage elements. Wiring channels 220, 220A, and 220B can be customized (mask- configured) to connect I/O wiring channels 101 to core area 110 and to connect the outputs of cells 211 to the inputs of other cells 211 , thus forming a complete electronic circuit. In the preferred embodiment, programmable wiring channels 220, 220A, and 220B include a plurality of "checkerboard-like" arrays of wiring patterns 222A and 222B. As explained below, wiring patterns 222A and 222B preferably comprise two layers of insulated wire segments, one on top of another. The wire segments on one layer of a wiring pattern preferably are oriented in the same direction while the wire segments on a different layer of the same wiring pattern are oriented in a different direction. The wire segments on the same layer of adjacent wiring patterns preferably are oriented in different directions. As an example, Fig. 13A, which shows a preferred embodiment of wiring channels, shows four adjacent wiring patterns (two patterns designated as 221H and two patterns designated as 221J) having wire segments 310 and 312 located on one layer and wire segments 311 and 313 located on another layer. The two layers of wire segments are separated by an insulating layer (not shown in Fig. 13 A) so that these wire segments are electrically isolated, unless connected by mask-programmable connection means described later in Figs.5A-D. To simplify the drawing, Fig. 2 shows only the directions of the programmable wire segments on the upper layer. Thus, the upper wire segments in wiring patterns 222A are shown to have a horizontal direction and the upper wire segments in wiring pattern 222B are shown to have a vertical direction. Note that the structure and arrangement of the individual wiring patterns are a matter of design choice.

According to the preferred embodiment of the present invention, the wire segments are normally not connected. However, these wire segments may be connected (i.e., programmed) by a fabrication process involving a single discretionary mask. Suitable connection means will be discussed in connection with Figs. 5A-D. A connection means is a structure used to (potentially) connect, in a mask-programmable manner, two conducting regions (preferably shaped as wire segments) of layers comprising an IC. Preferably, portions of the conducting regions to be connected are in an overlapping or proximal relationship such that a contact, via, or Top Level Via between them can be (potentially) made. The meaning of the "mask-programmability" is that the presence or absence of the contacts or vias can be selectively determined for all connection means by using a single programming pattern or mask. Preferably, this programming mask is applied in a single patterning operation, but a person skilled in the art could devise a process where the same discretionary mask is used in more than one patterning operation. A connection means may also comprise auxiliary non¬ programmable layers, facilitating the fabrication of the mask-programmable portion of that connection means. A ULA device may contain a plurality of connection means having different shapes and (potentially) connecting wire segments located on different layers. Structures within an integrated circuit, where connection means can be fabricated are referred to as coupling sites. A coupling site may include portions of the conducting layers to be connected by the connection means that can be (possibly) fabricated at this site. Geometric positions, where connection means can be located, are referred to as coupling locations.

As explained below, it is possible to connect a wire segment on the upper layer to a wire segment on a lower layer by programming a connection means located in a coupling site proximal to both wires. By providing (potential) connections at the appropriate places, the "checkerboard-like" arrays of wiring patterns allow an ASIC designer to connect electrically any initial point to another point remote from the initial point.

Programmable I/O wiring channels 101 preferably include similar arrays of wiring patterns designed in the same way as the channels in core area 110. Thus, any one of the cells 211 in core area 110 can be connected to any one of the I/O buffers 102 through I/O wiring channels 101 and/or wiring channels 220, 220A, and 220B.

As explained below, the same discretionary mask, used for programming the wiring channels, can be used to program the cells 211 in the core area 110 and the I/O buffers 102.

As a result of the above described arrangement, two functionally different ULA devices can be made by connecting (programming) different wires in the wiring channels. Prior to the programming, these ULA devices contain the same I/O buffers 102, I/O wiring channels 101, programmable cells 211, and wiring channels 220. The programming method in accordance with the present invention allows a designer to use a single discretionary mask to customize a not-yet- programmed ULA device into a device performing a specific function. Thus, it is possible to fabricate a large number of not-yet-programmed ULA devices at low cost, and then customize individual batches of ASICs by programming a desired quantity of these ULA devices. The customization cost and turnaround time are reduced because only one discretionary mask is needed per batch.

Even though Fig. 1 shows that the preferred ULA device 100 comprises only one core area 110, it may contain several core areas which may either abut or be separated from each other by additional wiring channels. ULA device 100 may also comprise special-purpose (mask- programmable or non-programmable) functional blocks that may be connected to the core area(s) by wiring channels or by abutment.

Even though Fig. 2 shows that core area 110 contains three rows (210, 210A, and 210B) of cells 211, it should be apparent that the number of cell rows is a matter of design choice. Cells 211 of the preferred ULA device 100 may also be modified to include the following variations: (1) cells 211 need not be all identical, and (2) cells 211 need not be all mask-programmable.

I/O buffers 102 of the preferred ULA device 100 may also be modified to include the following variations: (1) some of the I/O buffers 102 may not be mask-programmable, and (2) some of the I/O buffers 102 may be located in the interior of the ULA device (e.g., when the ULA device is to be packaged using a flip-chip mounting method).

The I/O wiring channels 101 of the preferred ULA device 100 may be modified to include the following variations: (1) some of the I/O wiring channels 101 may comprise non-programmable connections, and (2) I/O wiring channels 101 may be designed to optimize the performance of the connections to I/O buffers 102, or they may be general-purpose wiring channels with structure similar to channels 220, 220A, and 220B.

The wiring channels of the preferred ULA device 100 may be modified to include the following variations: (1) the number of wiring patterns (e.g., 221 H and 221 J of Fig. 13A) used in the wiring channels need not be exactly two, (2) side wiring channels 220A and /or 220B may not be present in core area 110, (3) the boundaries separating wiring patterns 222 A and 222B need not coincide with the boundaries separating cells 211, and (4) some of the wiring channels may contain connections that are non-programmable or are optimized for high performance.

Simple Structures of Wiring Channels and Programmable Cells

The detailed structures of various components of wiring channel 220 are now described. Wiring channels 220A and 220B, as well as I/O wiring channels 101, have similar structures as wiring channel 220. It would be apparent to a person of ordinary skill in the art to build channels 220A, 220B, and 101 based on the following description.

Figs.3A and 3B show examples of the fundamental building blocks for connecting two wire segments. As explained above, the way to connect one point in a wiring channel to a remote point is by connecting a plurality of wire segments. Fig.3A shows the top view of a layout structure used to connect electrically two wire segments oriented in the same direction. Three elements are required: an initial wiring segment 254, an extension wire segment 256, and a mask-programmable coupling site

258, which could be programmed by using a connection means (details not shown). If coupling site 258 is left unconnected (open), wire segments 254 and 256 are not electrically connected. If the coupling site 258 is mask-programmed, by fabricating connection means therein, to be in the connected (closed) state, wire segments 254 and 256 are electrically connected. In one embodiment, segments 254 and 256 are located on different conducting layers with their endpoints partially overlapping, and coupling site 258 is located at or near the overlapping area. The connection means at coupling site 258 may comprise a conventional contact (via) structure, illustrated later in Figs.5A and 5B, or a novel Top Level Via structure, illustrated later in Figs.5C and 5D.

The not-yet-programmed coupling sites, which could be mask-programmed (if needed to connect appropriate wire segments) into a connected state, are shown symbolically as white squares in Figs.3A and 3B (and in all the subsequent drawings). For the purposes of illustration, an embodiment of the connection means comprising a conventional contact (via) between two metallic layers has been chosen.

Fig.3B illustrates a layout structure used to change the direction of a path connecting two points in the wiring channels. T ree elements are required: a wiring segment 264, an extension wiring segment 266 making an angle with respect to segment 264, and a mask-programmable coupling site 268 which could be programmed by using a connection means (details not shown). If coupling site 268 is left unconnected (open), wire segments 264 and 266 are not electrically connected. If coupling site 268 is mask-programmed, by fabricating connection means therein, to be in the connected (closed) state, wire segments 264 and 266 are electrically connected. In one embodiment, segments 264 and 266 are located on different semiconductor layers with their endpoints partially overlapping and coupling site 268 is located at or near the overlapping area. The connection means at coupling site 268 may comprise the conventional contact (via) structure, illustrated later in Figs. 5A and 5B, or the novel Top Level Via structure, illustrated later in Figs. 5C and 5D.

It should be noted that the conducting segments 254, 256, 264, and 266 may be made of different types of materials. Moreover, the angle between segments 264 and 266 does not have to be a right angle. Furthermore, the overlapping area between the conducting segments could be located at arbitrary points. Even though Figs.3A and 3B show that coupling sites 258 and 268 can be used to connect two conducting segments on different layers, it is possible to devise mask-programmable structures (connection means to be fabricated at coupling sites) for connecting two conducting segments on the same layer (see Figs. 5E, 8A and 8B). Fig.4A shows the top view of a first type of wiring pattern 221 A that could be used as wiring pattern 222A of Fig. 2. Wiring pattern 221 A comprises a vertical wire segment 272 and a horizontal wire segment 273 made of conductive materials and insulated from each other electrically by a layer of insulator (such as insulator 321, shown later in Figs.5B and 5D), sandwiched between them. In Fig.4A, wire segment 273 lies above wire segment 272 (separated by an insulator, not shown). Wiring pattern 221 A comprises five coupling locations 274 A, 274B, 274C, 274D, and 274E for accepting mask- programmable connection means. The coupling sites at these locations are normally open unless they are programmed (using mask-programmable connection means) to be in the "connected" state. The coupling site at centrally located coupling location 274C can be mask-programmed to introduce an electrical connection between wire segments 272 and 273. The remaining four locations are on the periphery of pattern 221 A: two (274A and 274D) are in the vicinities of the endpoints of segment 272 and two (274B and 274E) are in the vicinities of the endpoints of segment 273. Coupling sites may be formed at coupling locations 274A, 274B, 274D, and 274E for connecting to wire segments located in adjacent wiring patterns in a mask-programmable manner, as shown later in Fig. 6B.

Fig.4B shows the top view of a second type of wiring pattern 221B that could be used in the capacity of wiring pattern 222B of Fig.2. Wiring pattern 221B comprises a horizontal wire segment

276 and a vertical wire segment 278 made of conductive materials and insulated from each other electrically by a layer of insulator (not shown) in the same manner as that of wiring pattern 221 A (Fig.4A). In Fig.4B, wire segment 278 lies above wire segment 276. Wiring pattern 221B includes five coupling locations 282A, 282B, 282C, 282D, and 282E which may be used for the same purposes as previously discussed in connection with Fig.4A.

In the context of an IC technology with two metal layers, segments 272 of Fig.4A and 276 of Fig.4B can be made on the lower layer of metal, and segments 273 of Fig. 4A and 278 of Fig.4B can be made on the upper layer of metal.

It should be apparent to a person skilled in the art that the centrally located coupling site 274C of wiring pattern 22 A and the centrally located coupling site 282C of wiring pattern 221B can be used either to (1) change the direction of a conducting path from vertical to horizontal or vice versa, or (2) allow two paths to cross each other without creating an electrical connection. The first case occurs if the connection means located at the coupling site is mask-programmed to be in the "connected" state. Otherwise, the second case occurs. It should also be immediately apparent that pattern 221 B can be visualized as a rotation of pattern 221 A clockwise by 90 degrees. An implementation of a wiring channel 220 using a quilt consisting of wiring patterns 221 A and 221B is shown in Fig.4C.

Fig.4C is a drawing showing a block diagram of an embodiment wherein wiring patterns 221 A and 221 B are arranged to form a wiring channel between two rows of cells 211. Note that the vertical dimensions of each wiring pattern 221 A and 221B comprising the channel are smaller than the vertical dimension of each cell 211. This embodiment, together with the embodiment of Fig.2 where wiring patterns 222A and 222B are shown to have larger vertical dimensions than the vertical dimension of cells 211, serves to illustrate the flexibility of the wiring quilts created in accordance with the present invention. Further details of the wiring channel shown in Fig.4C will be discussed in

Figs.6A-C. Additional embodiments will be illustrated below.

While the simple wiring patterns 221 A and 221B of Figs.4A-B have been discussed for the case of two layers of metallic interconnection, many implementations of analogous wiring patterns in more than two interconnect layers should be apparent to a person skilled in the art. For example, in a semiconductor device having three such layers, wire segment 310 could be located on the first layer, wire segments 311 and 313 on the second layer, and wire segment 312 on the third layer. Selected connection means could be fabricated with the Top Levels Vias.

Figs.5A-E show two of the possible structures of the means for electrically connecting conductive materials, which can be used advantageously in the present invention. Structural elements that are common in Figs. 5A-E have the same reference numerals.

Fig. 5A shows a coupling site 315A which has been programmed (connected) using a conventional contact (via) structure, well known in the art, to connect two layers of metal wires. Coupling site 315 A could be used in any of the coupling locations in Figs.4A-B, even though the structure of coupling site 315A reflects most closely the structure at location 282C. Fig.5B shows a cross-section view of the conventional contact structure. Coupling site 315A is located at the intersection of wire segments 304 and 305 which correspond to segments 276 and 278 of Fig.4B, respectively. Wire segment 304 is covered by a layer of insulator 321. Coupling site 315A comprises the overlapping portions of wire segments 304 and 305 and insulator 321, and the connection means fabricated at this site comprises the portion of wire segment 305 contacting wire segment 304 through a (potential) hole 320. A programming mask having an appropriate pattern is used to fabricate hole 320 in the layer of insulator 321 (if it is desirable to program site 315A). An upper wire segment 305 is subsequently deposited on the layer of insulator 321 and a contact between wire segments 304 and 305 is made through hole 320. If it is desirable not to program (connect) coupling site 315A, hole 320 should not be etched, i.e., the pattern of the programming mask should be appropriately modified.

It is the intent of the present invention that, while coupling sites and connection means disposed in various places on the IC may differ from each other in details, they all comprise a potential element (e.g., a potential hole in one or more insulator layers) whose presence or absence in the programmed integrated circuit is determined by the same programming mask.

Figs. 5C and 5D show coupling site 315B which has been programmed using a novel structure called Top Level Via (TLV). The TLV structure is the subject of a co-pending patent application Serial Number 08/092,202 entitled "Top Level Via Structure for Programming Pre-fabricated Multi-Level

Interconnect," the specification of which is incorporated herein by reference. If it is desirable to program site 315B, a programming mask having an appropriate pattern is used to fabricate hole 320' in the layer of insulator 321 sandwiched between wire segments 304 and 305. Hole 320' also extends through an insulator layer 321', which is disposed on top of insulator 321 and covers a portion of wire segment 305. Note that, in contrast to the structure of the conventional contact, hole 32(X is not located

___. directly below upper wire segment 305. Furthermore, unlike hole 320 in the conventional contact of Fig.5A, hole 320' is etched after deposition of the upper wire segment 305. A conducting strap 322 is subsequently deposited to connect wire segments 304 and 305. If it is desirable not to program coupling site 315B, hole 320' should not be etched, i.e., the programming mask pattern should be appropriately modified.

Fig. 5E shows an application of the above-described TLV structure for connecting non- overlapping wire segments that are sufficiently proximal to each other. Only a cross-section of this structure is shown. Wire segments 304' and 304" are disposed on top of a layer of insulator 321", another layer of insulator 321 is disposed on top of wire segments 304' and 304" and on top of insulator 321", wire segment 305' is disposed on top of insulator 321, and insulator 321' is disposed on top of wire segment 305' and insulator 321. A programming mask having appropriate patterns is used to fabricate holes 320" and 320'" in the insulators 321' and 321. Conducting straps 322' and 322" are subsequently deposited to connect wire segment 305' to wire segment 304' and wire segment 304' to wire segment 304", respectively. If either of the above connections should not be made, the appropriate hole 321' and/or 321" should not be etched.

The TLV structure of Figs.5C-E provides substantial advantages over the conventional contact structure of Figs. 5A and 5B as a means for programming wire segments according to the present invention. One of the advantages is that both the upper and lower wire segments in the wiring patterns can be pre-fabricated. Selected coupling sites can then be programmed (when needed) using one discretionary mask. Note that the application of the TLV structure is not limited to a two-level structure. For example, appropriately located TLV structures can easily be fabricated, using one discretionary mask, to connect adjacent metal layers of a three metal layer structure. Furthermore, a connection between non-adjacent metal layers can be made with a TLV structure which is, perhaps, slightly larger than that used to connect adjacent layers. Ramifications and other applications of the TLV structure are further explained in the above mentioned TLV patent application.

Fig.6A depicts a block diagram 316A of a portion of the channel structure (called a "wiring quilt") shown in Fig.4C, comprising a plurality of wiring patterns 221 A (see Fig. 4A) and 221B (see Fig.4B) arranged in a "checkerboard-like" manner. This wiring quilt can be used to produce a general-purpose routable array of wiring segments. As explained in Fig. 6B below, portions of the wiring patterns 221 A and 221 B overlap each other. To maintain the clarity of Fig. 6 A, these overlapping portions of the wiring patterns are not shown. Fig. 6B shows a top view of a not-yet-programmed wiring quilt 316B, which corresponds to block diagram 316A of Fig. 6A, with the coupling sites indicated by white squares. The adjacent patterns 221 A and 221B are positioned such that a portion of an upper wire segment (such as wire segment 273A) of one pattern overlaps a portion of a lower wire segment (such as wire segment 276A) of another pattern, thus creating a coupling site (such as coupling site 258A) in the overlap area. Wire segments 273A and 276A are equivalent to wire segments 256 and 254, respectively, of

Fig. 3A. Similarly, coupling site 258A is equivalent to coupling site 258 of Fig. 3A. As explained previously, if it is desirable to connect wire segments 273A and 276A to extend the length of a conductive path, a conventional contact or a TLV can be used as the connection means at the coupling site 258A. Furthermore, it should be apparent that the location of coupling site 258A is analogous to any of the locations 274A, 274B, 274D, 274E, 282A, 282B, 282D, and 282E in Figs.4A-B (after the necessary wire segments are positioned at these locations to form coupling sites).

It can also be seen that wire segments 278A and 276A are equivalent to wire segments 266 and 264, respectively, of Fig.3B. Similarly, coupling site 268A is equivalent to coupling site 268 of Fig.3A. As explained previously, if it is desirable to connect wire segments 278A and 276A to change the direction of a conductive path, a conventional contact or a TLV can be used as the connection means in the coupling site 268A. Furthermore, it should be apparent that the location of coupling site 268A is analogous to any of the locations 274C and 282C in Figs.4A-B.

Fig. 6C shows a top view of one of the many ways to "program" the not-yet-programmed wiring quilt 316B of Fig. 6B to obtain a programmed wiring quilt 316C. Wiring quilt 316C is programmed to produce a connection extending from wire segment 305A, i.e., the first vertical segment at the upper left hand corner of quilt 316C, to wire segment 305C, i.e., the vertical wire segment located at the lower right hand corner of quilt 316C. The connection is accomplished by mask-programming (connecting) the connection means located at coupling sites 300G, 300J, 300K, 300L, 300M, 300N, 300P, 300Q, 300R, and 300S. The programming involves wire segments 305A, 302A, 303A, 304A, 303B, 302B, 305B, 302C, 303C, 304B, and 305C.

From the presented description, it should be immediately apparent that by mask- programming (i.e., connecting) appropriate coupling sites, it is possible to make connection between any two points of quilt 316C.

It should be noted that it is possible to assemble wiring quilt 316B of Fig. 6B using wiring patterns having shapes different from wiring patterns 221 A and 221 B of Figs.4A and 4B. Fig. 6D shows eight alternative wiring patterns, each containing just a single coupling site (instead of five sites shown in Figs.4A-B). It should be apparent to a person skilled in the art that it is possible to assemble wiring quilt 316B of Fig.6B by appropriately arranging the patterns of Fig. 6D. Figs. 7A-E show an exemplary structure of a simple mask-programmable cell. Fig. 7A shows a symbolic diagram of a cell 211 A comprising a N-type transistor 510A. Transistor 510A possesses three electrodes: a gate 511 A, a source 512A, and a drain 513A. Cell 211 A also comprises three terminals 501 A, 501 B, and 501 C and three coupling sites 300T, 300U, and 300V. Terminals 501 A, 501 B, and 501 C comprise wire segments which extend from (or are connected to, possibly in a mask-programmable manner) the wire segments of one or more wiring patterns (not shown) in the wiring channels adjacent to cell 211A into the vicinity of the coupling sites 300T, 300U, and 300V. Coupling site 300T can be mask-programmed to connect terminal 501 A to gate 511 A. Coupling site 300U can be mask-programmed to connect terminal 501B to source 512A. Coupling site 300V can be mask-programmed to connect terminal 501C to drain 513A.

In the embodiment shown in Fig. 7A, it should be noted that transistor 510A serves as an example of a semiconductor component in a programmable cell. Other types of components, such as diodes or resistors could be used, including combinations of semiconductor elements forming useful electronic circuits whose electrodes arc connected (possibly with mask-programmable connection means) to cell terminals. Some of these embodiments are described later in Figs. 10A and 15A, and many others should be immediately apparent to a person skilled in the art.

Fig. 7B shows a top view of a layout of cell 211 A of Fig. 7A. Terminals 501 A, 501B, and 501C are segments made of the upper layer of metal, shown in the drawing as vertical strips. Source 512A and drain 513A of transistor 510A are shown in the drawing as a stippled strip running across the cell. Gate 511 A is shown as a narrow vertical segment partially obscured by terminal 501 A. Coupling site

300T (comprising polysilicon contact 551 and a portion 531 of lower layer of metal) and a (potential) contact 541 (which acts as connection means if coupling site 300T is programmed) are partially obscured by other features of the cell and can be better viewed in the subsequent Fig.7D. Similarly, coupling site 300U, comprised of diffusion contact 552 and a L-shaped piece 532 of lower layer of metal, and (potentially) using a contact 542 as connection means, as well as coupling site 300V, comprised of diffusion contact 553 and a L-shaped piece 533 of lower layer of metal, and (potentially) using a contact 543 as connection means, can be better seen in Fig.7D.

In order to show the structure of transistor 510A more clearly, Fig. 7C shows gate 511A, source 512A and drain 513A of transistor 510A together with the outlines of the polysilicon contact 551 and diffusion contacts 552 and 553.

In order to show the structure of the coupling sites more clearly, Fig. 7D shows coupling sites 300T, 300U, and 300V. Coupling site 300T comprises polysilicon contact 551, portion 531 of lower layer of metal, and its connection means is (potential) contact 541. Coupling site 300U comprises diffusion contact 552, L-shaped piece 532 of lower layer of metal, and its connection means is (potential) contact 542. Coupling site 300V comprises diffusion contact 553, L-shaped piece 533 of lower layer of metal, and its connection means is (potential) contact 543.

In order to show the structure of the terminals more clearly, Fig. 7E shows terminals 501 A, 501B, and 501C of cell 211 A. Also shown arc: (potential) contact 541 located within terminal 501 A, (potential) contact 542 located within terminal 501 B, and (potential) contact 543 located within terminal 501 C.

Fig.7F shows a symbolic diagram of a cell 21 IB comprising a P-type transistor 51 OB. Other than for the difference in transistor type, cell 21 IB is constructed in a manner identical to cell 211 A. In the above embodiment, terminals 501 A-C in cell 211 A of Fig. 7A are upper-level wire segments connected, with mask-programmable connection means, to segments of the wire patterns located in the wiring channels adjacent to cell 211 A. It should be apparent to a person skilled in the art that one could devise cells with terminals utilizing several distinct conductive layers. Furthermore, the terminals may be connected to only one of the two channels adjacent to the cell. Figs.8 A and 8B show some of the possible configurations of the interfaces between cells 211 and wiring channels 220 (see Fig.2). It should be understood that a terminal of a cell may extend into a wiring channel or a wire segment of a wiring channel may extend into a cell.

The left portion of Fig. 8A shows a cell terminal 501 D disposed on the lower metal layer and a wire segment 306 disposed on the upper metal layer. A mask-programmable connection means disposed at a coupling site 600B can be used to connect cell terminal 501 D and wire segment 306.

The right portion of Fig. 8 A shows a cell terminal 501 E and a wire segment 302 which are located on a lower metal layer. An auxiliary wire stub 602 is disposed on the upper metal layer. Stub 602 is connected to cell terminal 501 E using a contact 601. Mask programmable connection means disposed at a coupling site 600A can be used to connect stub 602 to wire segment 302. The left portion of Fig. 8B shows auxiliary stub 604 disposed on lower metal layer, connected with a contact 603 to cell terminal 501 F disposed on upper metal layer. Mask-programmable connection means disposed at a coupling site 600D is placed in the common vicinity of stub 604 and a wire segment 306 disposed on upper metal layer.

The right portion of Fig. 8B shows a cell terminal 501 G disposed on the upper metal layer and a wire segment 302 disposed on the lower metal layer. A mask-programmable connection means disposed at a coupling site 600C can be used to connect cell terminal 501 G and wire segment 302.

It should be apparent to a person skilled in the art that contacts 601 of Fig.8A and 603 of

Fig.8B can be readily substituted by connection means similar to those disposed at coupling sites

600A and 600D, respectively. A person skilled in the art should be able to devise similar interfaces for technologies involving multiple layers of metal and for other combinations of layers used for cell terminals and for wire segments in the channels, e.g., the interfaces could be similar to the structures shown in Fig. 5E.

Figs.9A through 9C illustrate various ways to program mask-programmable structures constructed in accordance with the present invention. The purpose of these figures is to illustrate the flexibility of the ULA architecture, which permits a multitude of engineering choices. The flexibility of accomplishing the desired function by programming cells 211 and/or programming interconnections in the wiring channels 220 should be apparent to a person skilled in the art. Fig. 9A shows a symbolic diagram of a portion of a row of cells interfacing to two channels and portions of these channels. In Figs. 9A-C, wire segments disposed on the lower layer of metal are depicted as thin solid lines and wiring segments disposed on the upper layer of metal are depicted as wide stippled lines. Mask-programmable coupling sites are depicted as small white squares while permanent connections are depicted as small black circles. Two types of cells, 211C and 211D, are employed, similar to cells 211 A and 21 IB of Figs. 7A and 7F, respectively, with two differences. One difference is that electrodes of the transistors contained in cells 211C and 211D are permanently connected to the terminals of the respective cells. Another difference is that the portions of the terminals of cell 21 IC which are located on the lower layer of metal extend to the right side of the cell, and the portions of these terminals which are located on the upper layer of metal extend on the left side of the cell. Similarly, the terminals of cell 21 ID extend to the left side of the cell on the lower layer of metal and to the right side of the cell on the upper layer of metal.

Wiring channels comprise two types of wiring patterns, 221G and 221F. Wiring pattern 221G comprises two wire segments 302D on the lower layer of metal and three wire segments 303D on the upper layer of metal. Wiring pattern 221 F comprises three wire segments 304D of the lower layer of metal and two wire segments 305D on the upper layer of metal. Each of the wiring patterns 221G and 221F comprises six central coupling locations and ten peripheral coupling locations. The peripheral locations of adjacent wiring patterns coincide.

Fig. 9B indicates one way to program the architecture shown in Fig. 9A into a two-input NAND gate. The coupling sites having dark squares are programmed (i.e., connected), while the rest of the coupling sites are left open (i.e., not programmed). For clarity of the drawing, the open (not programmed) coupling sites are not shown. In Fig. 9B, electric connection starting at wire segment 900A is connected to the ground voltage, connection 999 A is connected to a positive voltage, connections 901 A and 902A are inputs to the NAND circuit, and connection 903 A is the output of the NAND circuit.

Fig. 9C indicates one way to program the architecture shown in Fig. 9A into a two-input NOR gate. The coupling sites having dark squares are programmed (i.e., connected) while the rest of the coupling sites are left open (not programmed). For clarity of the drawing, the open (not programmed) coupling sites are not shown. In Fig. 9C, connection 900B is coupled to a ground voltage, connection 999B is coupled to a positive voltage, connections 911B and 912B are inputs to the NOR circuit, and connection 913B is the output of the NOR circuit.

Fig. 10A depicts a more complicated but still relatively simple programmable cell 211E, comprising two P-type transistors, two N-type transistors, and five terminals. The terminals can be selectively connected (using mask-programmable means) to the transistor electrodes. The locations of the coupling sites are indicated in Fig. 10A with white squares.

Fig. 10B depicts one way to program cell 211E of Fig. 10A for implementing a two-input NAND circuit. In Fig. 10B, electric connection starting at wire segment 900C is coupled to a ground voltage, connection 999C is coupled to a positive power supply, connections 921 C and 922C are inputs to the NAND circuit, and connection 923C is the output of the NAND circuit. In Fig. 10B, programmed (connected) coupling sites are indicated with solid dark squares, and open (not programmed) coupling sites are omitted from the figure to improve its readability.

Fig. IOC depicts one way to program cell 211E of Fig. 10A for implementing a two-input NOR circuit. Connection 900D is coupled to a ground voltage, connection 999D is coupled to a positive voltage, connections 931 D and 932D are inputs to the NOR circuit, and connection 933D is the output of the NOR circuit. In Fig. IOC, programmed (connected) coupling sites are indicated with solid dark squares, while open (not programmed) coupling sites are omitted from the figure to improve its readability. Figs. 9A-C and 10A-C illustrate the flexibility of the integrated circuit architecture in accordance with the present invention. Depending on the engineering choice of the wiring patterns in the channels 220 of Fig. 2 and on the composition of the cells 211 of Fig.2, the functionality of the ULA device of Fig. 1 can be programmed in a vast number of ways. Figs.9A-C show that non¬ programmable cells can be configured into useful circuits by utilizing solely the mask-programmable channels. On the other hand, Figs. 10A-C show that increased complexity of the mask-programmable cells allows one to configure useful circuits without using the programmability features built into the wiring channels. The programming of the cells and the wiring channels can be accomplished in a single step, using a single discretionary mask.

It should be understood that cells 211 (see Fig.2) may comprise both permanent and programmable connections. Furthermore, cells 211 may contain build-in connections for connecting to standard circuits, such as clocks and power supplies.

The principles illustrated in Figs 1 through 10C teach constructing simple embodiments of ULA devices in accordance with the present invention. The remaining drawings, Figs. 11-19, explore variations of the basic principles and present alternative and preferred embodiments having additional engineering merits.

Fig. 11 shows an alternative composition of the coupling sites for cell 211A of Fig. 7A. Only the differences with respect to the exemplary cell layout of Fig. 7B are referenced in the alternative cell design shown in Fig. 11. Specifically, conventional contacts 541, 542, and 543 used as connection means in coupling sites 300T, 300U, and 300V of Fig.7A are replaced by Top Level Vias 561, 562, and 563, yielding new coupling sites 300T', 300U', and 300V, respectively. All the remaining shapes on all layers remain identical. This substitution is made possible by the extensions of metal pieces 531, 532, and 532, providing contact areas for TLV structures.

Fig. 11 illustrates an important feature of the present invention: TLV structures used for connecting the wire segments can be easily substituted with the conventional contacts and vice versa. This substitution can be made with only a minimal effort and involves a single discretionary mask, e.g., the discretionary mask of TLVs can be discarded, and a discretionary mask of contacts (vias) can be added. The result is a rapid migration path from a design using the novel TLV structure into a design that can be fabricated with commonly used semiconductor processes. This feature further facilitates a reduction of the product cost if it is desirable to mass produce the ASIC.

Figs. 12A and 12B show additional wiring patterns that can be used in the wiring channels 220 of Fig.2. Fig. 12A shows a top view of a third type of wiring pattern 221C that can be incorporated in wiring channels 220 of Fig. 2. Wiring pattern 221 C comprises two L-shaped wire segments 308 and 307 made of conductive materials and insulated from each other electrically by a layer of insulator sandwiched between them. In vertical direction, wire segment 307 lies above wire segment 308, Furthermore, wiring pattern 221C includes five coupling locations for electrically connecting conductive materials using mask-programmable connection means. The connection means located at a central coupling location 300C can be mask-programmed to introduce an electrical connection between wire segments 308 and 307. The remaining four coupling locations are on the periphery of pattern 221C: two coupling locations 300A are in the vicinities of the endpoints of segment 308, and two coupling locations 300B are in the vicinities of the endpoints of segment 307. Coupling locations 300A and 300B facilitate mask-programmable connections to wiring segments located in adjacent wiring patterns and cells.

It should be immediately apparent to a practitioner of the art that wiring pattern 221C illustrated in Fig. 12A, as well as patterns obtained by rotating pattern 221C by 90, 180, and 270 degrees, can be used, perhaps in conjunction with patterns 221 A and 221B of Figs.4A and 4B, to produce various generally routable wiring quilts.

Fig. 12B shows a top view of a fourth type of wiring pattern 221D that can be incorporated in wiring channels 220 of Fig. 2. Pattern 221D differs from the previously discussed patterns 221A to 221C by having two "bone-shaped" areas of conductive material instead of simple, straight or L- shaped segments. It also includes eight peripheral coupling locations and one central coupling location. It should be apparent to a person skilled in the art that, unlike wiring patterns 221 A to 221C which require at least two distinct types of wiring patterns arranged in a "checkerboard-like" manner to produce a generally routable wiring channel, pattern 221 D can be used alone to construct wiring channels by arranging multiple patterns 221 D in a matrix fashion.

Preferred Embodiment of Wiring Channels and Programmable Cells

Fig. 13A shows a top view of a wiring quilt that is considered by the inventors to be currently most advantageous for use in wiring channels 220 of Fig. 2. The quilt is composed of wiring patterns 221H and 221J, each of which can be considered a generalization of the basic wiring patterns 221 A of Fig.4A and 221B of Fig.4B, respectively. These two types of wiring patterns tile the channel area in alternating order, forming a "checkerboard-like" pattern. Each channel may have several rows of wiring patterns 221H and 221 J. Wiring pattern 221 H is made of a number of sufficiently long wiring segments 310 made of the first conducting material, overlapped with a number of sufficiently long wiring segments 311 made of the second conducting material and oriented perpendicular to segments 310, with an insulator layer (not shown) sandwiched between the layers of conductors. Coupling locations 300D are in the vicinities of endpoints of segments 310, and coupling locations 300E are in the vicinities of endpoints of segments 311. Coupling sites 300F are provided at each intersection of segments 310 with segments 311. Wiring pattern 221 J is made of a number of sufficiently long wiring segments 312 made of the first conducting material and oriented in the same direction as segments 311 of wiring pattern 221 H; segments 312 are overlapped by a number of sufficiently long wiring segments 313 made of the second conducting material and oriented in the same direction as segments 310 of wiring pattern 221H, and an insulator layer (not shown) is sandwiched between the layers of conductors. Coupling locations 300X are in the vicinities of endpoints of segments 312, and coupling locations 300Y are in the vicinities of endpoints of segments 313. Coupling sites 300Z are provided at each intersection of segments 312 with segments 313. Wiring patterns 221H and 221J are arranged in a "checkerboard-like" manner so that coupling locations 300D of patterns 221 H coincide with coupling locations 300Y of vertically adjacent patterns 221 J, and coupling locations 300E of patterns 221H coincide with coupling locations 300X of horizontally adjacent patterns 221J, thereby forming coupling sites.

Fig. 13B shows a exemplary programming of these alternating wiring patterns to form connecting paths. In Fig. 13B, connection means disposed at coupling sites 341, 342, 343, 344, 345, 346, 351, 352, 353, 354, 355, and 356 are mask-programmed to a "connected" state in selected positions where segments 311, 313, 310, and 312 intersect or overlap. By selectively connecting horizontal and vertical segments, it is possible to form a conducting path between two different points. For example, segments 313A and 313C are connected with a conductive path formed by mask-programming coupling site 341 to a "connected" state between the first (counting from the top) horizontal lower- level metal wire 312A and the third (counting from the left) vertical upper-level wire 313A, and performing analogous programming of the coupling site 342 between segments 313A and 311 A at the interface with the next wiring pattern to the right, coupling site 343 between segments 311 A and 310A, coupling site 344 between segments 310A and 313B, coupling site 345 between segments 313B and 312B, and coupling site 346 between segments 312B and 313C. In order to increase the readability of Fig. 13B, all wiring segments involved in this connection path are drawn with thicker outlines. Another conducting path is formed between segments 310D and 310F; this path comprises consecutively: segment 310D, coupling site 351, segment 311D, coupling site 352, segment 310E, coupling site 353, segment 313D, coupling site 354, segment 312D, coupling site 355, segment 311E, coupling site 356, and segment 31 OF.

By properly selecting which connection means to fabricate, one can form a large number of interconnecting paths within a channel.

In Figs. 13A and 13B, wiring patterns 221J and 221H are arranged in a two-by-two "checkerboard-like" array and each has five horizontal and five vertical wire segments. It should be apparent that the array dimensions and numbers of wire segments are exemplary, and the numbers of horizontal and vertical wire segments do not have to be the same. Furthermore, while Figs. 13A-B show a wiring quilt composed of two distinct wiring patterns, wiring channels 220 (Fig. 2) can be composed of any number of distinct, single-mask programmable wiring patterns, assembled and programmed in accordance with the principles disclosed above. A single wiring pattern, such as in the upper right quadrant of Fig. 13A, is similar to structures used in the prior art to form "crossbar-type" switches at intersections of wiring channels (e.g., see U.S. Pat.5,068,603 issued to Mahoney). However, one of the novelties of the present invention is the "checkerboard-like" arrangement of the wiring patterns. This arrangement yields wiring flexibility and facilitates the use of wiring quilts for generally routable wiring structures, including the wiring channels of the present invention. The following observation indicates one aspect of the wiring flexibility exhibited by wiring quilts built in accordance with the principles disclosed above. It should be noted that segments 313A and 310D of Fig. 13B have the same horizontal coordinate while belonging to two different conducting paths, electrically insulated from each other. Similarly, segments 313C and 31 OF also have the same horizontal coordinate while remaining electrically unconnected and belonging to two different conducting paths. If two rows of cells were positioned immediately adjacent to the wiring quilt of Fig. 13A and appropriately connected thereto (e.g., as shown in Fig. 14 below), it would be possible to connect, within a single channel, different signals to cell terminals sharing the same horizontal coordinate but located in different rows of cells. Such connections would not be possible if the channel consisted of a single wiring pattern. While a crossbar-type pattern (such as the one disclosed in Mahoney) could be used as a wiring channel, such pattern would suffer from a greatly reduced density of interconnections and/or increased spacing between cell terminals compared to the density and spacing made possible by using the wiring quilt in accordance with the present invention.

Fig. 14 describes the preferred embodiment of the structure and geometry of the connections between cells 211 and wiring channels 220 of Fig. 2. On top of each cell 211, there are upper-level metal wires 501, which are located at essentially the same level as wiring segments 311 and 313 of Fig. 13A. Wires 501 are used for three possible functions: (1) as cell terminals, i.e., to connect inputs and outputs of cells 211 to the wiring patterns 221H and 221J, (2) to program cells 211, and (3) to provide a routing connection for signals unrelated to cells 211, i.e., for connecting signals in one routing channel to another channel. As a part of the ULA customization, mask-programmable connection means (not shown) are used to connect upper-level metal wires 501 to lower-level metal wires (not shown) inside cells 211, thus connecting the components inside cells 211, forming different logic functions, and enabling connections to the inputs and outputs of cells 211. A description of the preferred embodiment of cell 211 is given below in Fig. 15A. In addition to participating in the programming of cells 211, upper-level metal wires 501 are used to connect the cells 211 to wiring patterns 221H and 221J through interfaces shown earlier in Fig. 8B. Connections to wiring pattern 221H are done by extending wires 501 to the peripheral coupling locations of pattern 221 H, thus forming coupling sites. Interface between patterns 221J and cells 211 is accomplished with lower-level metal stubs 604 as indicated earlier in Fig. 8B, said stubs connected to wires 501 with contacts 603. Note that wires 501 in Fig. 14 are analogous to wires 501G and 501F of Fig. 8B.

Figs. 15A-E illustrate the logical structure and the programming of yet another programmable logic cell 211 F that is considered by the inventors to be currently most advantageous for use as a programmable cell 211 of Fig. 2. Cell 211 F has increased functionality and flexibility compared to the earlier discussed cells 211A, 211B, 211C, 211D, and 211E. In Figs. 15A-E, only the circuit schematics are shown, because a layout implementing these schematics and having terminals located as shown in Fig. 14 can be readily designed by a person skilled in the art.

Fig. 15A is a schematic diagram describing the structure of programmable cell 21 IF. Cell 21 IF comprises a pair of tristate buffers 910 and 920, a pair of inverters 930 and 940, and five mask- configurable terminals 501 K, 501 L, 501M, 501N, and 501P. Cell terminals comprise wiring segments made in the upper level of metal in the same manner as cell terminals 501 indicated in Fig. 14. The first tristate buffer 910 has a data input 911, output 912, and a positive enable input 913. The second tristate buffer 920 has a data input 921, output 922, and a negative enable input 923. Both enable inputs 913 and 923 are tied together as a single electrical node. Inverters 930 and 940 have inputs 931 and 941, and outputs 932 and 942, respectively. All inputs 911, 921, 931, 941, 913, and 923, and outputs 912, 922, 932, and 942 are connected to mask-programmable coupling sites that can be configured to connect them to selected terminals of cell 211 F. Each of the coupling sites has structure similar to that of the coupling sites 300T, 300U, and 300V of Fig. 7B, and 300T', 300U', and 300V of Fig. 11, that is, the connection means (potentially) fabricated therein can comprise either a regular contact or a Top

Level Via structure. The coupling sites are indicated symbolically in Fig. 15A as white squares at the intersections of the terminals 501 K, 501 L, 501M, 501N, and 501P with electrical nodes 900, 999, 911, 921, 931, 41, 913, 923, 912, 922, 932, and 942. Since referencing each of the coupling sites by a number would render Fig. 15A unreadable, the coupling sites are listed below. There are coupling sites for connecting terminal 501 to node 913, terminal 501L to nodes 911, 913, 931, and 932, terminal 501M to nodes 912, 931, 941, 932, and 942, terminal 501N to nodes 922, 912, 931, 941, and 942, and terminal 501P to nodes 921, 941, and 942. Furthermore, cell 21 IF comprises coupling sites that serve to connect power supply line 999 (i.e., a logic constant "high") and the ground line 900 (i.e., a logic constant "low") to any desired mask-programmably selected terminals 501K, 501L, 501M, 501N, or 501P. The specific function implemented by cell 21 IF is determined by mask-programming an appropriately selected subset of the coupling sites listed above. The set of functions implementable with the circuit of Fig. 15A includes a variety of combinational Boolean functions and memory elements. The cell terminals 501 K, 501 L, 501 M, 501 N, or 501P can be connected to external signals, or to logic high 999, or to logic low 900, and pass on these values to the selected inputs of inverters and tristate inverters comprising cell 21 IF. It should be apparent to a person skilled in the art that by configuring appropriate coupling sites into the "connected" state, cell 211F can be programmed to implement any function of two variables, some functions of three variables, and several variants of tristate buffers, latches, or flip flops. Any terminals of cell 211 F that are not connected to the internal components of cell 21 IF can be used as "feed-through" wires for passing unrelated signals between the channels adjacent to the cell. It is important to note that before cell 21 IF is programmed, the inputs 911, 921, 931, 941, 913, and 923, outputs 912, 922, 932, and 942, and constant voltages 900 and 999 are not connected to any of the terminals 501K, 501L, 501M, 501N, and 501P. Figs. 15B-E show different ways to program 211 for achieving different electrical functions.

As a result, Figs. 15B-E contain many elements which are identical to the corresponding elements in Fig. 15A. In order to improve the clarity of Figs. 15B-E, the reference numerals of some of these identical elements will not be shown in Figs. 15B-E. These elements will be referred to by the same reference numerals as those in Fig. 15A. Fig. 15B shows one of the possible ways to of program cell 21 IF to produce a multiplexor with two outputs, one of which is inverting and the other non-inverting. The programming is done as follows. Connection means 330A connects the tristate enable signals 913 and 923 to terminal 501K of cell 211F. Connection means 330B connects the tristate input 911 to terminal 501L of cell 211F. Connection means 330C, 330D, 330E, and 330F connect outputs 922 and 912 and inputs 931 and 941 to terminal 501N. Connection means 330G and 330H connect the outputs 932 and 942 to terminal 501M.

Connection means 330J connects input 921 to terminal 501 P.

Fig. 15C shows an example of programming cell 211F to produce an AND gate. The AND gate is realized by using the multiplexor circuit of Fig. 15B and connecting terminal 501P to logical "low" 900 with the connection means 330K. The inputs to the AND gate are terminals 501 K and 501 L. The output of the AND gate is terminal 501M.

Fig. 15D shows an example of programming cell 21 IF to produce an a non-inverting tristate buffer. Connection means 330E connects input 931 to terminal 501N, which is the input to the resulting non-inverting buffer. Connection means 330L connects output 932 to terminal 501 L. Connection means 330B connects input 911 to terminal 501 L, connection means 330M connects the output 912 to terminal 501 M, which is the output of the resulting non-inverting tristate buffer. Note that terminal 501 P is not used in this cell and could be used as a "feed-through" wire to route an unrelated signal.

It is well known to people skilled in the art that one can realize any Boolean function by using multiplexors and inverters. Also, by connecting the output of a multiplexor to its input, a single-bit memory element is formed. For example, Fig. 15E shows an example of programming cell 211F to produce a single bit, transparent latch. This example is very similar to the multiplexor example shown in Fig. 15B except that connection means 330G is not used. Instead, connection means 330L connects the inverter output 932 to terminal 501 L, thereby forming a feedback path for the latch. The latch control is the terminal 501 K, the latch input is 501P, and the latch output is 501M. It is well known to one skilled in the art that by using memory elements and logic gate configurations, it is possible to form a wide variety of flip-flops, registers, other memory storage elements, state machines or any other digital function. Also, note that the present invention is independent of the type of connection means used to connect the metal wires. Fig. 16 illustrates the structure of the input/output wiring channels 101 that is considered by the inventors to be currently most advantageous for use in ULA device 100 of Fig. 1. The input/output wiring channel is made of long wires 1000 made of upper level metal. Wires 1000 distribute signals to Input/Output buffers 102. Intersecting the long upper-level metal wires 1000 are short lower-level metal wires 1002 that are used to connect (e.g., through interfaces similar to those shown in Figs.8A and 8B) wires 1000 to the wiring patterns 221H, 221J in the wiring channels 220. In addition, coupling sites 300W can be used to connect long wires 1000 to short lower-level metal wires 1001 connected to the input/output buffers 102. Using this arrangement, it is possible to route any signal internal to wiring channels 220 to any input/output buffer 102. While wires 1001 in Fig. 16 are directly connected to I/O buffers 102, it should be apparent to a practitioner of the art that additional interface circuitry (mask-programmable or otherwise) might be interposed between the wires 1001 and buffers 102.

Other Structures

In addition to the Uncommitted Logic Array architecture that could realize almost any digital circuit, one can efficiently use programmable NOR gate structures to implement Programmable Logic Arrays (PLAs) and Read Only Memories (ROMs). Fig. 17 shows a schematic diagram of an example of a programmable NOR gate 1100 with a "pull-up" PMOS load transistor 1110 having its gate 1111 coupled to the ground voltage. NOR gate 1100 also comprises "pull-down" NMOS transistors 1120A,

1120B, 1120C, 1120D, and 1120E with wires 1121 A, 1121B, 1121C, 1121D, and 1121E connected to their respective gates. Transistors 1120A, 1120B, 1120C, 1120D, and 1120E are prefabricated but not connected to the output node 1101. By selectively programming a subset selected from coupling sites 330P, 330Q, 330R, 330S, and 330T, one can program which of the pull-down transistors will attach to the output node and thus effect the NOR function of a selected subset of nodes 1121 A, 1121B, 1121C,

1121D, and ll21E.

Fig. 18A shows a top view on a small section of programmable NOR gate 1100 of Fig. 17. Polysilicon input lines 1121A, 1121B cross the diffusion area to form NMOS transistors 1120A, 1120B. Both transistors have a common (grounded) diffusion source area 1122. Two drain areas 1123A, 1123B are connected to lower-level metal pieces 1124A, 1124B through the diffusion contacts 1125A, 1125B.

Output wire 1101 of gate 1100 is made of the upper-level metal, and can be (potentially) connected to drains 1123A, 1123B of NMOS pull-down transistors 1120A, 1120B by (potentially) fabricating contacts 1126A, 1126B. It can be seen that diffusion contact 1125A, metal piece 1124A and the potential contact 1126A together comprise coupling site 330P of Fig. 17, and diffusion contact 1125B, metal piece 1124B and the potential contact 1126B together comprise coupling site 330Q of Fig. 17.

Fig. 18B illustrates the coupling sites 330P and 330Q of Fig. 17, in a view unobstructed by other components of the NOR gate section of Fig. 18A. Elements in Figs. 18A and 18B which are the same use the same reference numerals. Fig. 19 shows a five-by-five array of NOR gates. All the NOR gates 1100A through 1100E share the same inputs 1121 AA through 1121EE. The array is customized by selectively programming connection means 330Z.

It should be clear to a person skilled in the art that certain connection means located in the coupling sites and coupling locations indicated in Figs. 6B, 7A, 7F, 8A-B, 9A, 10A, 11, 13A, 14, 15A, 16,

17, and 19 could be replaced with non-discretionary permanent contacts while still permitting one to fabricate, in accordance with the present invention, a device capable of being mask-programmed to perform distinct functions. The number of different combinations of such coupling sites to be replaced by permanent contacts is too large to list here, yet the usefulness of any such combination should be readily appreciated by a person skilled in the art.

Summary

Using the structures described above or other collections of configurable functional units, transistors, resistors, capacitors and other elements, a common device type is fabricated in large quantity and is stored at the factory for subsequent customization. The device could comprise Uncommitted Logic Array(s), imbedded ROM(s), PLA controller(s), imbedded memory, or any additional collection of analog and digital components that could be connected in many different ways to form complex systems. Depending on the structures of the mask-programmable coupling sites and connection means, the customization may then proceed using one of two possible flows, described below for a technology with two levels of metal wires.

For low-volume, fast turnaround production, the preferred customization method is to use the Top Level Via structures of Figs. 5C-E as the mask-programmable parts of the means for connecting two prefabricated metal wires. This facilitates a single-step customization. The common device type is prefabricated all the way to, and including, the upper level of metal wires. For the customization, only one additional fabrication step is performed to form TLV connections selectively, thereby customizing the circuits in accordance with different customer specifications. This customization method may also be used for high-volume production if so desired. An alternative method for high-volume production, with a somewhat lower turnaround time, is to employ the conventional contact (via) structure of Figs.5A and 5B as the mask-programmable part of the connection means. In many contemporary IC technologies, the common device type could be prefabricated all the way to, and including, the insulator covering the lower level of metal wires. For the customization, contact holes over the lower level of metal wires are opened selectively in locations required to customize the circuits in accordance with circuit specifications. This step is followed by fabricating the upper level of metal wires. These upper-level metal wires do not depend on customer's specifications and are identical for all devices. A possible advantage of this method over using the Top Level Via in high-volume production is that the sequence of processing steps is identical to the traditional IC manufacturing process and no special processing (needed by the TLV structure) is required. Hence the manufacturing cost may be lower as compared to using the TLV structure.

It should be apparent to persons skilled in the art that an ASIC implementation of certain electric functions may not utilize all available resources of an ULA device, e.g., some wiring segments, cells, I/O buffers, or transistors may remain unconnected after ULA device customization. In certain situations, removing such elements from the mass-produced version of the ASIC may increase the yield and further decrease the variable costs per ASIC unit. This cost decrease may justify an increase in the number of discretionary masks used for the high-volume production. In one simple scenario, such discretionary masks could be obtained from the non-discretionary masks by removing patterns related to the fabrication of the unused resources.

Note that, in accordance with Figs. 7B and 11, an appropriate design of the lower and upper levels of metal wires enables the patterns of those wires to be shared between the devices fabricated for both the low- and high-volume production processes described above. Fabricating customizable devices in accordance with the present invention provides numerous advantages over the prior art architectures and methods. One of the advantages of the present invention is that ICs manufactured using the method described herein exhibit higher performance (speed) than FPGA devices. This performance improvement stems from the fact that the customization is done by forming metal-to-mctal connections using photolithography, hence the resistance and capacitance of the connections are much lower than the ones used in Field

Programmable Gate Arrays. Therefore, the invention offers ways to customize high performance devices. Another advantage of the present invention is that the processing time could be shortened because the customization is done using only one discretionary mask.

The majority of the art practiced heretofore involved multiple-step customization, and none of the known single-step customization methods was based on selective fabrication of contact- or via-type structures. The method of IC programming by selectively fabricating connection means provides an advantage over the prior art of single-mask IC customization that was accomplished by fabricating the discretionary upper layer of metal. It should be apparent to a person skilled in the art that if a circuit contains pre-manufactured, non-customizable contact (via) holes, then the upper layer of metal interconnections must be designed to avoid making undesirable contacts, thus lowering the interconnection density. Areas in the vicinities of the holes that could create undesirable contacts may be unusable for interconnects on the upper layer of metal. On the other hand, IC customization in accordance with the present invention does not produce any such unusable areas.

Since customization is done using only one discretionary mask, the required processing time should not exceed the time required by any previously known structures, with the exception of

FPGAs. In particular, the processing time is believed to be lower than that required by most of the previously known Gate Array structures. Furthermore, since more masks are shared among many designs, the non-recurring engineering (NRE) costs per design can be lower than that of the previously known structures. Conventional low-cost batch fabrication is used to manufacture the not-yet-customized devices.

Applications of the TLV structure for a single-step customization using semiconductor processes other than the conventional one with two layers of metal should be immediately apparent to a practitioner of the art. The advantages of the TLV structure used in the present invention are threefold. The first advantage is that since TLV structures are made after all the levels of metal are fabricated, the time required for customization may be reduced. Furthermore, the not-yet-customized ICs can be prefabricated in large quantities, using a normal, inexpensive batch production process. The second advantage is that, in the architecture of programmable channels and cells described herein, the pitch (i.e., feature size plus feature separation) of TLVs comprised in the connection means permits the IC customization by using a novel process for selectively patterning the via holes. This novel process is the subject of a co-pending patent application filed April 13, 1993, as Serial Number 08/046529 by Kellam et al. entitled "High Resolution Mask Programmable Via Selected By Low Resolution Photomasking." The use of this novel process further reduces the customization cost and time. The third advantage is that TLV structure can be used to connect more than two conducting layers (by using a single lithography step). As a result, the flexibility and achievable density of interconnections are likely to be increased. For example, if the technology supports two levels of metal, then those two levels can be readily connected by a Top Level Via; however, metal-polysilicon, metal-implantation, and metal-diffusion TLV connections are also feasible, possibly with certain compromises permitting an increase in the size of the TLV structure. If the technology supports three levels of metal, i.e., metal-1, metal-2, and metal-3, then a Top Level Via is used most conveniently to connect wires in metal-2 and metal-3 layers. Nevertheless, connecting metal-2 to metal-1 and metal- 3 to metal-1 in the same step used to connect metal-2 and metal-3 is feasible, possibly requiring certain compromises involving the TLV size. Extrapolation of the architecture described herein for the case of three or more metal layers should be apparent to a person skilled in the art.

It can be seen from the above that this invention bridges the gap between gate array technology and FPGA devices. It provides means to fabricate flexible, high performance ASICs with high transistor density, low NRE costs, and fast turnaround time. Furthermore, the present invention provides economical means to fabricate small batches of ICs and offers a transparent path to high volume production with low unit cost. An IC design, functionally identical to one made with TLV- based customization, can be fabricated in large quantities with no modifications, other than replacing the customization mask, using conventional fabrication methods.

The programmable coupling sites made in accordance with the present invention require much less area than connections made in FPGA devices. Therefore, the ICs made in accordance with the present invention can be made denser and their unit costs can be much lower than field programmable ICs, even when produced in low volumes of only a few hundred parts. Unlike FPGA devices, the present invention retains the flexibility and performance offered by gate arrays. The present invention does not require any special processing like FPGAs and is equally applicable to other semiconductor technologies like GaAs, Bipolar, and BiCMOS. The invention is applicable to digital, analog, and mixed digital-analog designs.

What is demonstrated is a fast and inexpensive means of customizing general-purpose digital logic, PLAs, ROM structures, and other analog or digital circuits. The customization is done with a single discretionary mask pattern.

Numerous modifications and variations will become apparent to those skilled in the art. It is to be understood that the above detailed description of the preferable embodiments is intended to be merely illustrative of the spirit and scope of the invention and should not be taken in a limiting sense. The scope of the invention is defined by reference to the attached claims.

Claims

What Is Claimed Is:

I. A method for customizing semiconductor devices having a plurality of layers comprising the steps of: providing a plurality of substantially identical semiconductor devices capable of performing a selected electrical function chosen from among a plurality of different potentially available electrical functions, each of said semiconductor devices comprising at least one coupling site adjoining a first conductive region of any of said layers and a second conductive region of any of said layers, said coupling site being initially fabricated in a non-connected state and capable of being programmed into a connected state by electrically interconnecting said first and said second conductive regions; and fabricating at least one of said semiconductor devices to perform said selected electrical function by programming at least one coupling site to said connected state using a single discretionary pattern.

2. The method of Claim 1 wherein said first and said second conductive regions are located on different layers, and wherein a portion of said first conductive region has an overlapping relationship with a portion of said second conductive region.

3. The method of Claim 1 wherein said programming step further comprises fabricating a top level via between said first and said second conductive regions by connecting said first and said second conductive regions with a conductive material passing through an insulating region separating said regions.

4. The method of Claim 1 wherein each of said plurality of substantially identical semiconductor devices further comprises a cell capable of being electrically connected to said first conductive region by using said single discretionary pattern.

5. The method of Claim 4 wherein said cell comprises a transistor.

6. The method of Claim 4 wherein said cell comprises a logic gate.

7. The method of Claim 4 wherein said cell comprises a programmable cell.

8. The method of Claim 7 wherein said programmable cell comprises a semiconductor component having a terminal, a conductive region, and a coupling site adjoining said terminal and said conductive region, said coupling site of said programmable cell capable of being programmed into an electrically connected state using said single discretionary pattern.

9. The method of Claim 8 wherein said semiconductor component comprises a transistor.

10. The method of Claim 9 wherein said semiconductor component comprises a logic gate.

II. The method of Claim 1 wherein each of said plurality of substantially identical semiconductor devices further comprises an input-output buffer capable of being electrically connected to said first conductive region by using said single discretionary pattern.

12. A method for fabricating semiconductor devices comprising the steps of: providing a first set of substantially identical semiconductor devices having a plurality of layers, each of said semiconductor devices comprising a first conductive region in a first layer; fabricating a second conductive region on said first set of semiconductor devices, said second conductive region separated from said first conductive region by an insulating region to form a coupling site, said coupling site capable of being programmed into a connected state by electrically interconnecting said first and said second conductive regions with a third conductive region; programming said coupling site to said electrically connected state using a single discretionary pattern; providing a second set of semiconductor devices which are substantially identical to said first set, said second set of semiconductor devices including a first conductive region in a first layer corresponding to said first conductive region and said first layer, respectively, of said first set; fabricating an insulating layer on said first layer of said second set of semiconductor devices, said insulating layer having holes at selected locations, including a hole uncovering a portion of said first conductive region; and fabricating a second conductive region in said second set of semiconductor devices, said second conductive region having a first portion making electrical contact with said portion of said first conductive region of said second set through said hole and a second portion which is substantially the same as said second conductive region of said first set, whereby said first and said set of semiconductor devices perform substantially the same electrical function.

13. The method of Claim 12 wherein said second conductive regions of said first and said second sets are located in a second layer, and wherein a portion of said first conductive region of each set has an overlapping relationship with a portion of said second conductive region of a corresponding set.

14. The method of Claim 12 wherein said programming step further comprises fabricating a top level via between said first and said second conductive regions of said first set by connecting said first and said second conductive regions with a conductive material passing through an insulating region separating said regions.

15. The method of Claim 12 wherein each of said first and said second sets of semiconductor devices contains a cell capable of being electrically connected to said first conductive region of the corresponding sets.

16. The method of Claim 15 wherein said semiconductor cell is a programmable cell.

17. The method of Claim 12 wherein each of said first and said second sets of semiconductor devices contains an input-output buffer capable of being electrically connected to said first conductive region.

18. The method of Claim 12 wherein said programming step further comprises fabricating a hole in said insulating layer and a conductive material connecting said first and said second conductive regions through said hole.

19. A semiconductor device comprising a wiring pattern of a first type and a wiring pattern of a second type, said first type comprising: a first set of conductive wires having a first orientation; a second set of conductive wires having a second orientation and having an overlapping relationship with said first set; and an insulating layer located between said first and said second set of wires; said second type of wiring pattern comprising: a third set of conductive wires having an orientation substantially the same as said second orientation; a fourth set of conductive wires having an orientation substantially the same as said first orientation and having an overlapping relationship with said fourth set; and an insulating layer located between said third and said fourth set of wires; said first type of wiring pattern being positioned adjacent to said second type of wiring pattern, and at least one member of said fourth set of conductive wires capable of being connected to at least one member of said first set of conductive wires.

20. The device of Claim 19 further comprising means for electrically connecting said at least one member of said fourth set of conductive wires to said at least one member of said first set of conductive wires.

21. The device of Claim 20 wherein said means for connecting comprises a top level via.

22. The device of Claim 20 wherein said means for connecting comprises a contact.

23. The device of Claim 19 wherein at least one member of said first set of conductive wires and at least one member of said second set of conductive wires is electrically connected.

24. The device of Claim 23 wherein said at least one member of said first set of conductive wires and said at least one member of said second set of conductive wires are connected using a top level via.

25. The device of Claim 23 wherein said at least one member of said first set of conductive wires and said at least one member of said second set of conductive wires are connected using a contact.

26. The device of Claim 19 further comprising a cell capable of being connected to at least one member of said first set of conductive wires.

27. The device of Claim 26 wherein said cell is programmable.

28. The device of Claim 26 wherein said cell comprises a transistor.

29. The device of Claim 26 wherein said cell comprises a logic gate.

30. The device of'Claim 19 further comprising an input-output buffer capable of being connected to one member of said first set of conductive wires.

31. A semiconductor device having a plurality of layers comprising: a conductive wire located on one of said plurality of layers; a first transistor capable of being connected to said conductive wire; a plurality of transistors each having a conductive terminal and having an overlapping relationship with said conductive wire; an insulating layer located between said conductive wire and said conductive terminals of said plurality of transistors; and means for connecting at least one of said conductive terminals of said plurality of transistors to said conductive wire.

32. The device of Claim 31 wherein said means for connecting comprises a top level via.

33. The device of Claim 31 wherein said means for connecting comprises a contact.