WO1995010084A3 - Circuit tampon a adressage virtuel - Google Patents

Circuit tampon a adressage virtuel Download PDF

Info

Publication number
WO1995010084A3
WO1995010084A3 PCT/US1994/011273 US9411273W WO9510084A3 WO 1995010084 A3 WO1995010084 A3 WO 1995010084A3 US 9411273 W US9411273 W US 9411273W WO 9510084 A3 WO9510084 A3 WO 9510084A3
Authority
WO
WIPO (PCT)
Prior art keywords
address
virtual addressing
addressing buffer
output
buffer circuit
Prior art date
Application number
PCT/US1994/011273
Other languages
English (en)
Other versions
WO1995010084A2 (fr
Inventor
Jason Seung-Min Kim
Original Assignee
Ast Research Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ast Research Inc filed Critical Ast Research Inc
Priority to CA002168335A priority Critical patent/CA2168335C/fr
Priority to AU79286/94A priority patent/AU7928694A/en
Priority to KR1019960701782A priority patent/KR100341180B1/ko
Publication of WO1995010084A2 publication Critical patent/WO1995010084A2/fr
Publication of WO1995010084A3 publication Critical patent/WO1995010084A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function

Abstract

Un circuit tampon à adressage virtuel (10) formate l'adresse de sortie au moyen d'un registre de formatage (16) sous forme d'une combinaison de nouveaux bits d'adresse et de bits d'adresse d'entrée originaux. L'aptitude à formater l'adresse de sortie permet à l'utilisateur de remplacer certains bits d'adresse sans qu'il soit nécessaire de remplacer toute l'adresse. Le tampon à adressage virtuel commande la sortie de plusieurs signaux de commande vers des circuits externes afin d'indiquer comment le système doit réagir à la sortie d'adresse provenant du tampon d'adressage virtuel. Les signaux de commande sont régis par un registre de commande (20) et sont extraits du tampon d'adressage virtuel uniquement lorsqu'une correspondance d'adresse a été vérifiée. Le circuit tampon à adressage virtuel élimine certains bits d'une adresse d'entrée selon les indications d'un registre de filtrage (22) avant de vérifier si l'adresse d'entrée correspond à une adresse stockée. Une fois qu'une correspondance d'adresse a été détectée, le circuit tampon à adressage virtuel remplace toute l'adresse d'entrée par une nouvelle adresse formatée.
PCT/US1994/011273 1993-10-06 1994-10-04 Circuit tampon a adressage virtuel WO1995010084A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002168335A CA2168335C (fr) 1993-10-06 1994-10-04 Circuit tampon a adressage virtuel
AU79286/94A AU7928694A (en) 1993-10-06 1994-10-04 Virtual addressing buffer circuit
KR1019960701782A KR100341180B1 (ko) 1993-10-06 1994-10-04 가상어드레싱버퍼회로,및어드레스번역방법,시스템bios의셰도잉방법,실제메모리최적화방법,실제메모리이용방법,cpu제어시스템에서의에뮬레이팅방법및cpu요청리디렉트방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/132,643 1993-10-06
US08/132,643 US5526503A (en) 1993-10-06 1993-10-06 Virtual addressing buffer circuit

Publications (2)

Publication Number Publication Date
WO1995010084A2 WO1995010084A2 (fr) 1995-04-13
WO1995010084A3 true WO1995010084A3 (fr) 1996-02-29

Family

ID=22454953

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/011273 WO1995010084A2 (fr) 1993-10-06 1994-10-04 Circuit tampon a adressage virtuel

Country Status (5)

Country Link
US (3) US5526503A (fr)
KR (1) KR100341180B1 (fr)
AU (1) AU7928694A (fr)
CA (1) CA2168335C (fr)
WO (1) WO1995010084A2 (fr)

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Also Published As

Publication number Publication date
US5737769A (en) 1998-04-07
KR100341180B1 (ko) 2002-11-23
CA2168335A1 (fr) 1995-04-13
US5526503A (en) 1996-06-11
CA2168335C (fr) 2002-07-30
KR960705274A (ko) 1996-10-09
WO1995010084A2 (fr) 1995-04-13
US5809559A (en) 1998-09-15
AU7928694A (en) 1995-05-01

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