WO1995011521A1 - Method and apparatus for the planarization of layers on semiconductor substrates - Google Patents

Method and apparatus for the planarization of layers on semiconductor substrates Download PDF

Info

Publication number
WO1995011521A1
WO1995011521A1 PCT/GB1994/002326 GB9402326W WO9511521A1 WO 1995011521 A1 WO1995011521 A1 WO 1995011521A1 GB 9402326 W GB9402326 W GB 9402326W WO 9511521 A1 WO9511521 A1 WO 9511521A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
flat
substrate
anvil
exposed surface
Prior art date
Application number
PCT/GB1994/002326
Other languages
French (fr)
Inventor
Christopher David Dobson
Original Assignee
Christopher David Dobson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Christopher David Dobson filed Critical Christopher David Dobson
Publication of WO1995011521A1 publication Critical patent/WO1995011521A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC

Definitions

  • This invention relates to method and apparatus for use in the treatment of semiconductor substrates and in particular, but not exclusively, when layers are deposited and etched on the substrate.
  • the insulating layer is at least for a time in a liquid state i.e. it is non-gaseous and capable of flowing at least at its exposed surface and at operational temperatures under moderate pressures.
  • the invention consists in a method of forming a flat layer on semiconductor substrate, comprising forming a layer on the substrate in a liquid state and engaging the exposed surface of the layer, whilst the layer is still in the liquid state, with a flat or smoothing surface such that the exposed surface is flatten to conform with the flat or smoothing surface.
  • the flat surface and exposed surface are moved relative to one another to achieve engagement.
  • the flat surface may be formed on an anvil of sufficient mass to cause conforming flow in the layer.
  • the anvil may be suspended above the substrate and the substrate may be moved against the anvil to lift it from its suspended position.
  • the flat surface and the exposed surface may be pressed together by pneumatic pressure e.g. ambient or atmospheric pressure.
  • the flat surface may be formed on a plate or the like.
  • the flat surface and the exposed surface may be separated after flattening by gas or vapour being injected or formed between the surfaces.
  • the method is carried out in a vacuum chamber in which the substrate is being processed.
  • the smoothing surface may be provided by a roller, which may be one of a pair of nip rollers.
  • the invention consists in apparatus for flattening a deposited layer, in a liquid state, on a semiconductor substrate, comprising a body having a flat or smoothing surface and means for causing relative movement between the flat or smoothing surface and the layer for causing conforming engagement between the flat or smoothing surface and the exposed surface of the layer.
  • the apparatus includes an anvil defining the flat surface, means for suspending the anvil above the exposed surface and means for lifting the substrate so that it engages the exposed surface against the flat surface and lifts the anvil from its suspended position.
  • the smoothing surface may be provided by a roller, which may be one of a pair of nip rollers.
  • Figure 1 is a schematic side view of apparatus for flattening a layer, in a liquid state, which has been deposited on a semiconductor substrate; the apparatus being shown in its start position.
  • Figure 2 shows the apparatus of Figure 1, with an anvil above the layer
  • Figure 3 shows the apparatus of Figure l with the layer and anvil engaged
  • Figure 4 shows the apparatus of Figure 1 in the separated position after flattening, and indicates a separation device
  • FIG. 5 illustrates schematically an alternative flattening apparatus.
  • FIG 1 a semiconductor wafer 10 sits on a wafer support 11 which is provided with lifting pins 12.
  • the wafer 10 has already been subjected to some treatment and there is thus an etched conducting layer 13 and a planarisation layer 14, which has been deposited on the conducting layer 13 and is still in a liquid state.
  • the support 11 is contained within a vacuum chamber (not shown) and a wafer transfer mechanism 15 is provided for moving wafers into and out of the chamber.
  • An anvil 16 is suspended on the spatula 17 of the wafer transfer mechanism 15 by means of a frame 18.
  • the undersurface 19 of the anvil 16 is optically flat.
  • the pins 12 then lift the complete wafer 10 to engage the exposed surface 20 against the flat surface 19.
  • This engagement causes local conforming flow in the exposed surface 20, so that the hills and valleys 21,22 (see Figures 1 and 2) are smoothed out until the exposed surface 20 completely conforms with the flat surface 19.
  • planarisation layer 14 is formed as described in International Patent Application No. PCT/GB93/01368 water vapour will be given off and in the reduced pressure conditions this should be sufficient to provide for separation of the surfaces 19,20 when the pins are lowered (see Figure 4) .
  • separation can be achieved or enhanced by introducing gas between the surfaces through line 23.
  • the above mechanism is particularly convenient because it enables the flattening to take place within the chamber in which planarisation deposition took place and so it prevents the planarisation layer going off before flattening occurs.
  • a thin plate may be placed on top of the planarisation layer and the pressure in the vacuum chamber raised so that the flattening force is essentially pneumatic. Conveniently the chamber can be raised to atmospheric pressure.
  • planarisation will however take place at low temperatures and pressures and an appropriate anvil temperature or its equivalent may be desirable or necessary.
  • FIG. 5 An alternative approach is illustrated in Figure 5.
  • the wafer 10, and its deposited layers 13 and 14 are passed between nip rollers 24 to flatten the layer 14.
  • the process could be achieved in single or multiple passes or the rollers could be reversed several times so that the wafer 10 moves back and forth between them.

Abstract

A semiconductor wafer (10) is provided with a planarization layer (14) which has its exposed surface (20) flatten by being engaged with a flat surface (19) on an anvil (16), which may be temporarily supported on the layer (14).

Description

METHOD AND APPARATUS FOR THE PLANARIZATION OF LAYERS ON SEMICONDUCTOR SUBSTRATES
This invention relates to method and apparatus for use in the treatment of semiconductor substrates and in particular, but not exclusively, when layers are deposited and etched on the substrate.
During the formation of semiconductor circuits on silicon wafers (and other semiconductors) , a number of alternating layers of conducting and insulating films or layers is built up. The etching of the conducting layers to form interconnecting tracks causes an inherent "bumpiness" in the conducting layers. The application of a conformal dielectric layer to insulate one conducting layer from another enhances this surface "bumpiness". With reducing dimensions, the depth of focus of the lithographic equipment becomes incapable of accommodating the height variations caused by the lack of flatness in the built-up layers. Various techniques have been developed in an attempt to produce an insulating layer which gives a flat exposed surface ready for the next deposition. These include spin- on-glass; electron cyclotron resonance deposition; a planarisation treatment described in my International Patent Application No. PCT/GB93/01368 and chemical mechanical polishing. Only the last is capable of producing a surface which is flat within the terms accepted by the industry, typically optically flat, but it is a time consuming process. In some of these techniques the insulating layer is at least for a time in a liquid state i.e. it is non-gaseous and capable of flowing at least at its exposed surface and at operational temperatures under moderate pressures. From one aspect the invention consists in a method of forming a flat layer on semiconductor substrate, comprising forming a layer on the substrate in a liquid state and engaging the exposed surface of the layer, whilst the layer is still in the liquid state, with a flat or smoothing surface such that the exposed surface is flatten to conform with the flat or smoothing surface.
Preferably the flat surface and exposed surface are moved relative to one another to achieve engagement. In one embodiment, the flat surface may be formed on an anvil of sufficient mass to cause conforming flow in the layer. In this case the anvil may be suspended above the substrate and the substrate may be moved against the anvil to lift it from its suspended position.
Alternatively, the flat surface and the exposed surface may be pressed together by pneumatic pressure e.g. ambient or atmospheric pressure. In this case the flat surface may be formed on a plate or the like.
The flat surface and the exposed surface may be separated after flattening by gas or vapour being injected or formed between the surfaces.
Preferably the method is carried out in a vacuum chamber in which the substrate is being processed.
In another embodiment the smoothing surface may be provided by a roller, which may be one of a pair of nip rollers.
From another aspect the invention consists in apparatus for flattening a deposited layer, in a liquid state, on a semiconductor substrate, comprising a body having a flat or smoothing surface and means for causing relative movement between the flat or smoothing surface and the layer for causing conforming engagement between the flat or smoothing surface and the exposed surface of the layer. In one embodiment the apparatus includes an anvil defining the flat surface, means for suspending the anvil above the exposed surface and means for lifting the substrate so that it engages the exposed surface against the flat surface and lifts the anvil from its suspended position.
In another embodiment the smoothing surface may be provided by a roller, which may be one of a pair of nip rollers.
Although the invention has been defined above, it is to be understood that it includes any inventive combination of the features set out above or in the following description.
The invention may be performed in a number of ways, specific embodiments of which will now be described, by way of example, with reference to the accompanying drawings, in which:-
Figure 1 is a schematic side view of apparatus for flattening a layer, in a liquid state, which has been deposited on a semiconductor substrate; the apparatus being shown in its start position.
Figure 2 shows the apparatus of Figure 1, with an anvil above the layer;
Figure 3 shows the apparatus of Figure l with the layer and anvil engaged;
Figure 4 shows the apparatus of Figure 1 in the separated position after flattening, and indicates a separation device; and
Figure 5 illustrates schematically an alternative flattening apparatus.
In Figure 1 a semiconductor wafer 10 sits on a wafer support 11 which is provided with lifting pins 12. As can be seen, the wafer 10 has already been subjected to some treatment and there is thus an etched conducting layer 13 and a planarisation layer 14, which has been deposited on the conducting layer 13 and is still in a liquid state.
As usual the support 11 is contained within a vacuum chamber (not shown) and a wafer transfer mechanism 15 is provided for moving wafers into and out of the chamber. An anvil 16 is suspended on the spatula 17 of the wafer transfer mechanism 15 by means of a frame 18. The undersurface 19 of the anvil 16 is optically flat.
In Figure 2, the wafer transfer mechanism has been moved into the position in which it overlies the support 11 and hence holds the anvil 16 with its surface 19 immediately above the exposed surface 20 of the planarisation layer 14.
As can be seen in Figure 3, the pins 12 then lift the complete wafer 10 to engage the exposed surface 20 against the flat surface 19. This engagement causes local conforming flow in the exposed surface 20, so that the hills and valleys 21,22 (see Figures 1 and 2) are smoothed out until the exposed surface 20 completely conforms with the flat surface 19.
If the planarisation layer 14 is formed as described in International Patent Application No. PCT/GB93/01368 water vapour will be given off and in the reduced pressure conditions this should be sufficient to provide for separation of the surfaces 19,20 when the pins are lowered (see Figure 4) . However, if this does not occur, or if the system is used with some other planarisation layer, separation can be achieved or enhanced by introducing gas between the surfaces through line 23. The above mechanism is particularly convenient because it enables the flattening to take place within the chamber in which planarisation deposition took place and so it prevents the planarisation layer going off before flattening occurs. However, in other circumstances, it may be perfectly proper to have a separate flattening chamber and in that case a fixed flattening surface may be provided. In a further variation a thin plate may be placed on top of the planarisation layer and the pressure in the vacuum chamber raised so that the flattening force is essentially pneumatic. Conveniently the chamber can be raised to atmospheric pressure.
Normally the planarisation will however take place at low temperatures and pressures and an appropriate anvil temperature or its equivalent may be desirable or necessary.
An alternative approach is illustrated in Figure 5. Here the wafer 10, and its deposited layers 13 and 14, are passed between nip rollers 24 to flatten the layer 14. The process could be achieved in single or multiple passes or the rollers could be reversed several times so that the wafer 10 moves back and forth between them.

Claims

Claims
1. A method of forming a flat layer on a semiconductor substrate comprising, forming a layer on the substrate in a liquid state and engaging the exposed surface of layer, whilst the layer is still in the liquid state, against a flat or smoothing surface such that the exposed surface is flatten to conform with the flat or smoothing surface.
2. A method as claimed in Claim 1, wherein the flat surface and the exposed surface are moved relative to one another to achieve engagement.
3. A method as claimed in Claim 1 or Claim 2, wherein the flat surface is formed on an anvil of sufficient mass to cause conforming flow in the layer.
4. A method as claimed in any one of the preceding Claims, wherein the anvil is suspended above the substrate and the substrate is moved against the anvil to lift it from its suspended position.
5. A method as claimed in Claim 1 or Claim 2, wherein the flat surface and the exposed surface are pressed together by the ambient pressure.
6. A method as claimed in any one of the preceding Claims, wherein the flat surface and the exposed surface are separ¬ ated after flattening by gas or vapour being injected or formed between the surfaces.
7. A method as claimed in any one of the preceding Claims, wherein the method is performed within a vacuum chamber.
8. A method as claimed in Claim 1, wherein the smoothing surface is the surface of a roller.
9. A method as claimed in Claim 8, wherein the substrate and layer are past through a pair of nip rollers.
10. A method substantially as hereinbefore described, with reference to the accompanying drawings.
11. Apparatus for flattening a deposited layer, in a liquid state, on a semiconductor substrate comprising a body having a flat or smoothing surface and means for causing relative movement between the flat or smoothing surface and layer for causing conforming engagement between the flat or smoothing surface and the exposed surface of the layer.
12. Apparatus as claimed in Claim 11, including an anvil defining the flat surface, means for suspending the anvil above the exposed surface and means for lifting the substrate so that it engages the exposed surface against the flat surface and lifts the anvil from its suspended posi¬ tion.
13. Apparatus as claimed in Claim 11, wherein the suspend¬ ing means include a semiconductor wafer transfer mechanism.
14. Apparatus as claimed in Claim 11, including a roller for providing the smoothing surface.
15. Apparatus as claimed in Claim 14, including a pair of nip rollers through which the substrate and layer may pass.
16. Apparatus for flattening a deposited layer on a se i- conductor substrate substantially as hereinbefore defined.
PCT/GB1994/002326 1993-10-23 1994-10-21 Method and apparatus for the planarization of layers on semiconductor substrates WO1995011521A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9321900.4 1993-10-23
GB939321900A GB9321900D0 (en) 1993-10-23 1993-10-23 Method and apparatus for the treatment of semiconductor substrates

Publications (1)

Publication Number Publication Date
WO1995011521A1 true WO1995011521A1 (en) 1995-04-27

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WO (1) WO1995011521A1 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0665580A2 (en) * 1994-01-28 1995-08-02 Texas Instruments Incorporated Method and apparatus for global planarisation of a surface of a semiconductor wafer
EP0683511A3 (en) * 1994-05-18 1996-05-01 At & T Corp Device fabrication involving planarization.
US5932045A (en) * 1997-06-02 1999-08-03 Lucent Technologies Inc. Method for fabricating a multilayer optical article
WO2001018860A2 (en) * 1999-09-09 2001-03-15 Alliedsignal Inc. Improved apparatus and methods for integrated circuit planarization
EP1254742A2 (en) * 2001-05-04 2002-11-06 Chartered Semiconductor Manufacturing Ltd. Thermal mechanical planarization in intergrated circuits
US6589889B2 (en) 1999-09-09 2003-07-08 Alliedsignal Inc. Contact planarization using nanoporous silica materials
US6721076B2 (en) 2001-08-03 2004-04-13 Inphase Technologies, Inc. System and method for reflective holographic storage with associated multiplexing techniques
US6825960B2 (en) 2002-01-15 2004-11-30 Inphase Technologies, Inc. System and method for bitwise readout holographic ROM
US7001541B2 (en) 2001-09-14 2006-02-21 Inphase Technologies, Inc. Method for forming multiply patterned optical articles
US7112359B2 (en) 2001-08-22 2006-09-26 Inphase Technologies, Inc. Method and apparatus for multilayer optical articles

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JPH0691223A (en) * 1992-09-09 1994-04-05 Toshiba Corp Method for smoothing resin film

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JPS6245045A (en) * 1985-08-22 1987-02-27 Nec Corp Manufacture of semiconductor device
JPH02125436A (en) * 1988-11-04 1990-05-14 Nec Kagoshima Ltd Die bonding device
JPH05337438A (en) * 1992-06-03 1993-12-21 Sekisui Chem Co Ltd Formation of coating film on porous body
JPH0691223A (en) * 1992-09-09 1994-04-05 Toshiba Corp Method for smoothing resin film

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0665580A3 (en) * 1994-01-28 1997-03-05 Texas Instruments Inc Method and apparatus for global planarisation of a surface of a semiconductor wafer.
EP0665580A2 (en) * 1994-01-28 1995-08-02 Texas Instruments Incorporated Method and apparatus for global planarisation of a surface of a semiconductor wafer
EP0683511A3 (en) * 1994-05-18 1996-05-01 At & T Corp Device fabrication involving planarization.
US5932045A (en) * 1997-06-02 1999-08-03 Lucent Technologies Inc. Method for fabricating a multilayer optical article
US6797607B2 (en) 1999-09-09 2004-09-28 Alliedsignal Inc. Contact planarization using nanoporous silica materials
WO2001018860A2 (en) * 1999-09-09 2001-03-15 Alliedsignal Inc. Improved apparatus and methods for integrated circuit planarization
WO2001018860A3 (en) * 1999-09-09 2002-01-17 Allied Signal Inc Improved apparatus and methods for integrated circuit planarization
US6589889B2 (en) 1999-09-09 2003-07-08 Alliedsignal Inc. Contact planarization using nanoporous silica materials
EP1254742A2 (en) * 2001-05-04 2002-11-06 Chartered Semiconductor Manufacturing Ltd. Thermal mechanical planarization in intergrated circuits
EP1254742A3 (en) * 2001-05-04 2003-11-12 Chartered Semiconductor Manufacturing Ltd. Thermal mechanical planarization in intergrated circuits
US6721076B2 (en) 2001-08-03 2004-04-13 Inphase Technologies, Inc. System and method for reflective holographic storage with associated multiplexing techniques
US7112359B2 (en) 2001-08-22 2006-09-26 Inphase Technologies, Inc. Method and apparatus for multilayer optical articles
US7001541B2 (en) 2001-09-14 2006-02-21 Inphase Technologies, Inc. Method for forming multiply patterned optical articles
US6825960B2 (en) 2002-01-15 2004-11-30 Inphase Technologies, Inc. System and method for bitwise readout holographic ROM

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