WO1995024076A1

WO1995024076A1 - Slew-rate controlled power switching circuit

Info

Publication number: WO1995024076A1
Application number: PCT/US1995/002312
Authority: WO
Inventors: Vivek Mehra
Original assignee: Apple Computer, Inc.
Priority date: 1994-03-01
Filing date: 1995-02-24
Publication date: 1995-09-08

Abstract

A slew-rate controlled switching circuit comprises a transistor having a source coupled to a power supply; a pull-up resistor having a first terminal coupled to the source of the transistor; a gate resistor having a first terminal coupled to the gate of the transistor and a second terminal coupled to a second terminal of the pull-up resistor; and a feedback capacitor having a first terminal coupled to the gate resistor and a second terminal coupled to the drain of the transistor. The second terminal of the gate resistor forms a circuit input. The feedback capacitor is enhanced by the Miller effect. The gate resistor limits the rate at which charge states of the capacitances present at the gate of the transistor can change. When the circuit input is switched from a high value to a low value, the drain voltage increases smoothly and nearly linearly from a low value to a high value at a rate proportional to the product of the value of the gate resistor and the value of a capacitance present between the gate and the drain. The time required for the drain voltage to switch from its low value to its high value is sufficient to enable a power supply to respond to changing current demand.

Description

SLEW-RATE CONTROLLED POWER SWITCHING CIRCUIT

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to circuits for power switching, and more particularly to power switching circuits in systems having a minimum operating voltage. Still more particularly, the present invention is a slew-rate controlled power switching circuit.

Description of the Background Art An electronic system can include a number of subsystems, where each subsystem performs a given function. A given electronic system commonly includes one or more subsystems that are used sporadically. In applications where power consumption must be minimized, power is typically applied to a particular subsystem only when the subsystem is in use. Power switching circuits facilitate the routing of power to a particular subsystem only when use of the subsystem is required.

A battery-powered portable computer system provides an example of an electronic system having subsystems that are not continuously used. Referring now to Figure 1, a block diagram of an exemplary battery-powered portable computer system is shown. The exemplary battery-powered portable computer comprises a processor, a memory, a system controller, an I/O subsystem, a hard disk subsystem, and a first and a second power switching circuit. In the battery- powered portable computer system of Figure 1, and in most similar systems, power is continuously provided to the system controller, the processing unit, and the memory. Information transfers involving the hard disk drive do not occur continuously, and in general do not occur on a regular basis. In a like manner, I/O operations do not occur on a regular basis. Therefore, to conserve power and significantly extend battery life, the first and the second power switching circuits route power to the hard disk subsystem and the I/O subsystem, respectively, only when required. The power switching circuits are controlled by the system controller as indicated by the dashed lines. Power switching circuits are based upon transistors, and can comprise either bipolar transistors or Metal-Oxide-Semiconductor (MOS) transistors. Bipolar transistors require a bias current at all times for switching and exhibit higher on-state voltage drops than MOS transistors, thereby reducing the voltage applied to the system. Thus, most high performance power switching circuits are based upon MOS transistor technology.

Referring now to Figure 2, a circuit diagram of a prior art power switching circuit coupled to a voltage output rail of a power supply, a decoupling capacitor C, and a subsystem "S" is shown. The power switching circuit consists of a P- channel MOS (PMOS) transistor "QI" having a gate, a source, and a drain. The decoupling capacitor "C " has a first terminal and a second terminal. Subsystem "S" has an input and a ground terminal. A power supply (not shown) maintains the voltage output rail at V c volts. The source of transistor Ql is connected to the voltage output rail, and is therefore also maintained at V c volts. The drain of transistor Ql is connected to the input of subsystem S and the first terminal of decoupling capacitor C, and forms an output for the power switching circuit at which a voltage V₀ut is measured. The ground terminal of subsystem S and the second terminal of decoupling capacitor C are connected to electrical ground. The gate of transistor Ql forms a control input to the power switching circuit to which a digital voltage signal Vi_n is applied. For example, transistor Ql may be a

Siliconix Si9405DY P-Channel Enhancement-Mode MOS Transistor, decoupling capacitor C may have a capacitance of 2.2 μF, and Vcc may equal 5 volts.

When subsystem S is not needed, Vi_n is held at a high voltage, preventing current flow in transistor Ql and thereby maintaining the Vout at zero Volts. Herein, it is assumed that subsystem S provides a resistive current path to electrical ground. If use of subsystem S is required, Vin is switched to a low voltage, forcing the voltage at the gate of transistor Ql to a low value. Transistor Ql then conducts current, charging decoupling capacitor C and bringing the output voltage Vout to a high value. Once Vout has risen to a predetermined voltage level, subsystem S can properly function. The rate at which decoupling capacitor C is charged is limited by the switching speed of transistor Ql, the on-resistance of transistor Ql, the Effective Series Resistance (ESR) of decoupling capacitor C, and the output impedance of the power supply. Historically, transistor development efforts have continuously focused on providing transistors that switch between an "off" state and an "on" state as rapidly as possible. Reduction of a transistor's on-resistance has also been an ongoing technological trend. In a like manner, technological advances related to capacitors have provided capacitors with ever-decreasing ESR values. Typical present-day values for PMOS transistor turn-on delay time and on-resistance are 25 ns and 75 mΩ, respectively. A typical present-day capacitor ESR value is 400 mΩ; some present-day capacitors have ESR values as low as 50 mΩ.

The maximum current Imax through transistor Ql and decoupling capacitor C is approximately given by Vcc divided by the sum of the resistances present. Using a voltage of 5 volts for V_C Imax is given by 5 Volts divided by (400 + 75) mΩ, or 10.5 Amps. Normal subsystem operating currents generally fall within a range of 1 mA to 1 A; thus, Imax is very large relative to normal operating currents.

The time interval required to charge decoupling capacitor C can be approximated by the equation: Δt = (C * ΔV)/I_max (1) which, when calculated using the exemplary value of C = 2.2 μF, gives a time interval of approximately 1 microsecond. Ideally, the voltage on the voltage output rail, namely V_cc, should remain constant at all times. Unfortunately, power supplies have a finite output impedance and are not able to respond to surges in such short time intervals. The voltage generated by the power supply therefore falls during the current surge.

Referring now to Figure 3, a voltage signal diagram showing values for Vin, V_cc, and V_Dut in the prior art power switching circuit is shown. As can be seen from Figure 3, when Vi_n is switched from a high value to a low value, V₀ut rapidly rises, and Vcc rapidly drops approximately 1 volt. The power supply voltage drop may violate the minimum operating voltage of one or more components of the system. Thus, when the power supply voltage drops, one or more subsystems, and possibly the entire system itself, may fail to operate properly. Currently, portable electronic systems are being designed to operate with lower power supply voltages to further reduce power consumption. For example, portable computers and personal communications devices are now being designed with power supplies that provide an operating voltage of 3.3 volts rather than 5 volts. While a 1-volt drop represents a 20% voltage change relative to 5 volts, the 1-volt drop is a 30% voltage change relative to 3.3 volts. As the percentage change in operating voltage increases, the risk of subsystem failure becomes greater. In the future, portable electronic systems are expected to operate at even lower power supply voltages, and resulting subsystem and system failures are expected to become more common. The ongoing trend towards faster- switching transistors and towards capacitors having lower ESR values serves to worsen the problem. Thus, there is a need for a power switching circuit that prevents power supply voltage drops when a subsystem is turned on.

SUMMARY OF THE INVENTION The present invention is a slew-rate controlled power switching circuit that prevents a power supply voltage drop when a subsystem is switched on. A first and discrete embodiment of the present invention comprises a PMOS transistor, a pull-up resistor, a gate resistor, and a feedback capacitor. The PMOS transistor has a gate, a source, and a drain. The pull-up resistor, the gate resistor, and the feedback capacitor each have a first terminal and a second terminal. The source of the PMOS transistor is coupled to a voltage output rail of a power supply, and is maintained at Vcc Volts. The gate of the PMOS transistor is coupled to the first terminal of the gate resistor and the first terminal of the feedback capacitor. The PMOS transistor's drain is coupled to the second terminal of the feedback capacitor, and provides a voltage output at which a voltage Vout is available. The drain is also coupled to a voltage input of a subsystem, and to a first terminal of a decoupling capacitor. The decoupling capacitor has a second terminal that is coupled to electrical ground. The first terminal of the pull-up resistor is coupled to the source, and the second terminal of the pull-up resistor is coupled to the second terminal of the gate resistor. The second terminal of the gate resistor forms a control input to which a voltage control signal Vi_n is applied. A second and integrated embodiment of the present invention comprises a

PMOS transistor and a gate resistor as an integrated circuit. The PMOS transistor has a source, a gate, and a drain. The couplings in the second and integrated embodiment are identical to those in the first and discrete component embodiment, except that there is no feedback capacitor explicitly present in the second and integrated embodiment. Rather, the second and integrated embodiment relies upon the parasitic gate-to-drain capacitance of the PMOS transistor itself for capacitance between the gate and the drain.

In the present invention, a capacitive feedback path is provided between the gate and the drain of the PMOS transistor. The gate resistor affects the maximum rate at which the capacitance present in the feedback path can discharge. Because the voltage present at the gate controls the current flow in the PMOS transistor, the feedback path causes changes in Vout to affect the transistor current flow as well. When Vi_n is held at a high voltage, preferably at V_Cc, the transistor is in an "off" state. While the PMOS transistor is in the "off" state, no current flows through the PMOS transistor, the capacitance present in the feedback path between the gate and the drain is fully charged, and V₀ut equals zero Volts. When Vi_n is switched from V_Cc volts to electrical ground, the capacitance in the feedback path can discharge, causing the gate voltage to drop. As the gate voltage drops, the PMOS transistor is switched into an "on" state, causing Vout to rise towards V_Cc- The time required to raise V_Qut from zero

Volts to V_Cc Volts depends upon the capacitance present in the feedback path and upon the value of the gate resistor. The capacitance present in the feedback path increases the time required to switch Vout from zero to Vcc Volts via the Miller effect. The rising drain voltage causes a current to flow in the feedback path and thus through the gate resistor. This current flowing in the feedback path drives the gate voltage towards the source voltage as well, moving the PMOS transistor back towards the "off" state and limiting the current flow in the PMOS transistor. The limited current flow thereby increases the time required to switch V₀ut from zero to Vcc Volts. The gate resistor and the capacitance present between the gate and the drain thus increase the time required to charge the decoupling capacitor. This in turn ensures that the power supply has sufficient time to respond to the increasing current demand of the circuit of the present invention, thereby ensuring that the power supply voltage remains constant.

The maximum time rate of change exhibited by Vout is referred to herein as the slew rate of the circuit of the present invention. Thus, via the feedback path, the slew rate affects the transistor current, and therefore provides sufficient time for the power supply to respond to changing current demand.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of an exemplary battery-powered portable computer system;

Figure 2 is a circuit diagram of a prior art power switching circuit coupled to a voltage output rail of power supply, a decoupling capacitor (C), and a subsystem (S);

Figure 3 is a timing diagram showing values for Vi_n, V_C and V₀ut for the prior art power switching circuit of Figure 2;

Figure 4 is a circuit diagram of a first and discrete embodiment of a slew- rate controlled power switching circuit constructed in accordance with the present invention;

Figure 5 is a circuit diagram of a PMOS transistor including parasitic capacitances;

Figure 6 is a graph showing the variation in PMOS transistor gate-to-drain capacitance as a function of the voltage difference between the gate and the drain;

Figure 7 is a graph of an exemplary turn-on charge characteristic for a PMOS transistor; Figure 8 is a timing diagram showing values for V , V o and V₀ut for a first exemplary embodiment of the circuit of Figure 4; Figure 9 is a circuit diagram of a second and integrated embodiment of a slew-rate controlled power switching circuit of the present invention using an integrated circuit with a gate resistance and a parasitic gate to drain capacitance according to the present invention; and Figure 10 is an exemplary cross-sectional view of the second and integrated embodiment of the circuit of Figure 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to Figure 4, a circuit diagram of a first embodiment of a slew- rate controlled power switching circuit 10 constructed in accordance with the present invention is shown. The first and discrete embodiment of the present invention is preferably made of discrete components, and comprises a PMOS transistor 12, a pull-up resistor 14, a gate resistor 16, and a external feedback capacitor 18. The PMOS transistor 12 has a gate 30, a source 32, and a drain 34. The pull-up resistor 14, the gate resistor 16, and the external feedback capacitor 18 each have a first terminal and a second terminal. In the present invention, which of a resistor's terminals or a capacitor's terminals is designated as the first or second terminal is irrelevant to the behavior of the resistor or capacitor, respectively. A voltage output rail 40 of a power supply (not shown) is coupled to the source 32 of the PMOS transistor, and supplies an operating voltage of V c volts to the circuit 10. For example, the V_Cc may be 5 volts. The gate 30 of the PMOS transistor 12 is coupled to the first terminal of the gate resistor 16 and to the first terminal of the external feedback capacitor 18. The drain 34 of the PMOS transistor 12 provides an output voltage V_Cut_/ arid is coupled to a subsystem 50 via a subsystem voltage input line 52. The drain 34 is also coupled to the second terminal of the external feedback capacitor 18, and to a first terminal of a decoupling capacitor 60. The second terminal of the decoupling capacitor 60 is coupled to electrical ground, which herein is taken to be zero volts. The first terminal of the pull-up resistor 14 is coupled to the source 32, and the second terminal of the pull-up resistor 14 is coupled to the second terminal of the gate resistor 16. The second terminal of the gate resistor 16 forms a control input to the circuit 10 to which a voltage control signal (Vi_n) is applied. In the preferred embodiment, Vin is generated by an integrated circuit 100, and is delivered to the circuit 10 by a tristate output driver 102. During normal operation, the tristate output driver outputs a voltage of either Vcc Volts or zero Volts. While in a test mode, the tristate output driver 102 may supply an undefined voltage. The pull- up resistor 14 thus ensures that the voltage present at the control input of the circuit 10 is maintained at Vcc Volts when the tristate output driver 102 is in a test mode. When the voltage present at the control input of the circuit 10 is held at Vcc Volts, the voltage present at the gate 30 is also V c Volts. Therefore, the PMOS transistor 12 is in an "off" state. For simplicity, it is assumed herein that the subsystem 50 provides a resistive current path to electrical ground. When the PMOS transistor 12 is in an "off" state, Vout is held at electrical ground, the decoupling capacitor 60 is discharged, the voltage across the external feedback capacitor 18 equals V_Cc, and no power is being delivered to the subsystem 50.

When operation of the subsystem 50 is required, the PMOS transistor 12 must be switched into an "on" state. The switching characteristics of a PMOS transistor 12, and of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) in general, depend upon the total input capacitance present at the gate 30 during switching. In addition to the external feedback capacitor 18 present between the gate 30 and the drain 34, the total input capacitance present between the gate 30 and the drain 34 includes a set of parasitic capacitances that arise from the structure of the PMOS transistor 12 itself. Referring now to Figure 5, a circuit diagram of the PMOS transistor 12 including a parasitic capacitance Cgs between the gate 30 and the source 32 and a parasitic capacitance Cgd between the gate 30 and the drain 34 is shown. The total input capacitance seen at the gate 30 during switching due to the external feedback capacitor 18, Cgs and Cgd is given by the equation

Cinp = Cg_S + (Cgd + Cf)* (1 - A_v) (1) where Cf is the capacitance value of the external feedback capacitor 18 and A_v is the voltage gain of the PMOS transistor 12. The value of A_v is given by the derivative of the drain voltage with respect to the gate voltage. The multiplication of the gate-to-drain capacitance, namely, (Cgd + Cf), by A_v is due to what is conventionally referred to as the "Miller effect."

To switch the PMOS transistor 12 into an "on" state, the tristate output driver 102 switches Vi_n from V c to zero Volts, grounding the control input of the circuit 10. As soon as Vi_n equals zero volts, the capacitance present between the gate 30 and the drain 34, namely Cgd and the external feedback capacitor 18, begin to discharge. The capacitive discharge causes the gate voltage to drop from Vcc towards zero volts. The value of the gate voltage as it drops is initially given by the equation

V_g(t) = V_cc * exp (-t/(R_g * (Cf + C_gd))) (2) where t is the time that has elapsed since Vin ^was switched from Vcc to zero volts and Rg is the value of the gate resistor 16. As t increases, the rate at which the gate voltage drops decreases. As the gate voltage drops below the source voltage, the PMOS transistor 12 begins to conduct current and Cg_S begins to charge. Because of the current conduction through the PMOS transistor 12, V₀ut begins to rise towards the source voltage, namely V c- Those skilled in the art will recognize that the parasitic capacitances present in the PMOS transistor 12, particularly Cgd, are voltage dependent. Referring now to Figure 6, a graph showing the variation in Cgd as a function of the voltage difference between the gate 30 and the drain 34 is shown, where Vgd is the voltage difference between the gate 30 and the drain 34. As can be seen in Figure 6, Cgd varies greatly with changes in Vgd-

Referring now to Figure 7, a graph of the turn-on charge characteristics for an exemplary PMOS transistor 12 is shown. In Figure 7, Vds is the voltage difference between the drain 34 and the source 32, Vgs is the voltage difference between the gate 30 and the source 32, and Qg is the electrical charge seen at the gate 30 of the PMOS transistor 12. Figure 7 is divided into a first region, a second region, and a third region. The first, second, and third regions are labeled as Region 1, Region 2, and Region 3, respectively. The boundary between the first region and the second region is defined by the value of Vds equal to 90% of its initial value, and the boundary between the second region and the third region is the defined by value of Vds equal to 10% of its initial value. These boundaries conventionally define the rise time for V_out- While the PMOS transistor 12 operates in Region 1, Cg_S is being charged. While the PMOS transistor 12 operates in Regions 2 and 3, the Miller effect becomes the dominant capacitive effect, greatly increasing the time required to raise Vout to V_Cc- The Miller effect is compounded by the increasing value of Cgd as Vgd changes according to Figure 6, and by the presence of the additional capacitance in the feedback path due to the external feedback capacitor 18.

As Vout rises towards V_C the changing value of V_Dut causes a displacement current to flow in the external feedback capacitor 18 and in Cgd- As a result, a current flows through the gate resistor 16, thereby increasing the gate voltage and increasing the time required for the gate voltage to reach zero Volts. The overall rise time of V₀ut in the circuit 10 is proportional to the value of the gate resistor 16 multiplied by the total input capacitance seen at the gate 30 during switching. Therefore, the presence of the gate resistor 16 and the enhancement of the Miller effect via the external feedback capacitor 18 greatly increase the time required for V_Qut to rise to V c- Referring now to Figure 8, a timing diagram showing values for Vin, Vc and Vout for a first exemplary embodiment of the circuit 10 of Figure 4 is shown. In the exemplary embodiment, the PMOS transistor 12 is a Siliconix 9405DY P- Channel MOS Transistor, the value of the pull-up resistor 14 is 1.0 MΩ, the value of the gate resistor 16 is 10 kΩ, the value of the external feedback capacitor 18 is 0.01 μF, and the value of the decoupling capacitor is 2.2 μF. In the exemplary embodiment, Vcc equals 5.0 volts. As can be seen from Figure 8, when Vi is switched from Vcc to zero volts, Vout does not respond immediately. As discussed above, the delay exhibited by V₀ut iⁿ reaching V_Cc is due to the time required to discharge the external feedback capacitor 18 through the gate resistor 16 until the PMOS transistor 12 turns on. The PMOS transistor 12 turn-on occurs as the gate voltage drops below the source voltage. For the exemplary embodiment of the circuit of Figure 4 as shown in Figure 8, this time is measured to be approximately lOμs.

Once the Siliconix 9405 DT transistor turns on, Vout increases smoothly to its final value according to the behavior shown in Figures 6 and 7, where the majority of the Vout transition is linear. As shown in Figure 8, the exemplary embodiment of the circuit 10 of Figure 4 requires a total time of approximately 80 μs to bring Vout to its final value of V_Cc after Vin i switched from V_Cc to zero volts. Therefore, approximately 70 μs elapse while the transistor 12 transitions between the "off" state and the "on" state. The average current through the decoupling capacitor 60 during the 70 μs time interval is given by the equation:

Idecoupling(avg) = C * ΔV_out / Δt_on (5) where C is the value of the decoupling capacitor 60, ΔV_Dut is the change in V_Dut over the time interval, and Δton is the duration of the time interval for the transistor to transition between the off state and the on state. For the exemplary embodiment of the circuit 10 of Figure 4, Idecoupling(avg) approximately equals

157 mA. Preferably, the 10 kΩ value of the gate resistor 16 represents an approximate minimum value to be used in an embodiment of the circuit 10.

The time require ^' for Vout to rise from zero to Vcc volts is proportional to the product of the gate resistor value and the value of the capacitance present between the gate 30 and the drain 34. Thus, the value of the gate resistor 16 can be chosen such that the present invention functions properly when Cgd alone provides the feedback path between the gate 30 and the drain 34. In a second exemplary embodiment (not shown) of the circuit 10 of Figure 4, use of a gate resistor 16 having a value of 150 kΩ and elimination of the external feedback capacitor 18 produce a measured time of approximately 400 μs to switch V_Qut from zero to Vcc volts, thereby limiting Idecoupling(avg) to approximately 25 mA. Thus, the circuit 10 of Figure 4 readily provides a reduction in the current through the decoupling capacitor 60 of approximately two orders of magnitude over to the prior art using the values cited above. Preferably, the gate resistor 16 has a target value of 150 kΩ plus or minus 50% to achieve the desired behavior. In addition, the pull-up resistor preferably has a target value of 750 kΩ plus or minus 33%.

The power supply can readily respond to the current required over the time interval provided by the circuit 10 of Figure 4. Because the power supply is not exposed to a sudden surge in current over a very short time interval, Vcc remains constant. Thus, the present invention eliminates the risk of subsystem failure due to V_Cc fluctuation during subsystem turn-on. Moreover, this enhances the life of the power supply and other circuit components of the computer system since they are not subjected to power surges that can significantly reduce the life of all electrical parts.

When a given subsystem 50 is turned on, the subsystem 50 typically performs self-diagnostic functions. Completion of the self-diagnostic functions requires on the order of 100 msec. While performing the self-diagnostic functions, the subsystem 50 is not available for other activities. Therefore, in the present invention, the time taken for V_Dut to rise to a value at which the subsystem 50 can properly function is insignificant relative to the time that must elapse before the subsystem 50 is available for use.

The historical trend in transistor development has been towards the development of faster-switching transistors, that is, transistors in which the time to switch between "on" and "off" states is minimized. In contrast to technological trends, the goal of the present invention is to increase the time required to smoothly switch the PMOS transistor 12 from an "off" state to an "on" state. The present invention accomplishes this goal through the use of the gate resistor 16 and /or by enhancing the Miller effect. In the prior art power switching circuit of Figure 2, the likelihood that a subsystem will fail when switched on due to a V_Cc drop increases as the PMOS transistor switching speed increases. In the present invention, the PMOS transistor 70 will require a longer time interval to switch between "on" and "off" states, and to raise Vout to its final value, as the capacitance is present between the gate 30 and the drain 34 is increased, or as a larger-valued gate resistor 16 is used. In the first and discrete embodiment of the present invention, the external feedback capacitor 18 provides additional capacitance to enhance the Miller effect, and the gate resistor 16 greatly increases the time required to change the charge states of the capacitances present. Because the Miller effect plays a major role in determining PMOS transistor switching speed, device designers have continually devised means for decreasing the Miller effect by reducing Cgd- The present invention, on the other hand, functions better as Cgd is increased. Those skilled in the art will recognize that the parasitic capacitance Cgd can be increased by fabricating the PMOS transistor 12 according to an appropriate set of design parameters. However, for a given PMOS transistor having a small Cgd value, the value of the gate resistor 16 can be chosen to optimize the performance of the present invention. Thus, with an appropriate choice of the gate resistor value, the present invention prevents Vcc from dropping even when a fast-switching PMOS transistor 12 is used.

Referring now to Figure 9, a second and integrated embodiment of a circuit 11 constructed in accordance with the present invention is shown. For convenience, circuit elements in Figure 9 that are identical to circuit elements in Figure 4 are given identical reference numbers. The second and integrated embodiment of the present invention comprises the PMOS transistor 12, an integrated pull-up resistor 15, and an integrated gate resistor 17. The second and integrated embodiment of the circuit 11 relies upon the PMOS transistor's parasitic gate-to-drain capacitance Cgd to provide the feedback path between the gate 30 and the drain 34; no additional capacitor is provided, as is done in the first and discrete embodiment of the present invention. The integrated pull-up resistor 15 and the integrated gate resistor 17 are preferably fabricated via an ion- implant process or a diffusion process. In the second and integrated embodiment of the circuit 11, the integrated pull-up resistor 15 and the integrated gate resistor 17 are fabricated such that it is part of the integrated circuit forming the PMOS transistor 12.

Referring now to Figure 10, an exemplary cross-sectional view of the PMOS transistor 12 in the second and integrated embodiment of the circuit 11 of Figure 9 is shown. The PMOS transistor 12 is formed according to conventional MOSFET fabrication processes, wherein layers of polysilicon and oxide are used to form the structure of the gate 30. Preferably, the gate resistor 17 is fabricated via an ion- implant process or via a diffusion process to have a value of 150 kΩ. This value of the integrated gate resistor 17 ensures that the circuit 11 functions properly despite variations in the values of the integrated gate resistor 17 and Cgd due to fabrication process variation.

While the present invention has been described with reference to certain preferred embodiments, those skilled in the art will recognize that various modifications may be provided. For example, in a second and integrated embodiment, the value of Cgd could be modified to provide the desired increase in the time required for V_Dut to rise to Vcc relative to a fixed, predetermined gate resistor value. Those skilled in the art will recognize that the value of Cgd can be increased by increasing the area of the overlap capacitance between the gate and the drain 34 during PMOS transistor 12 fabrication, or by decreasing the thickness of the dielectric used to create Cgd- As another example, an N-channel Metal- Oxide-Semiconductor (NMOS) transistor could be used instead of the PMOS transistor 12 in another embodiment of the present invention. These and other variations upon and modifications to the preferred embodiments are provided for by the present invention, which is limited only by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A slew-rate controlled power switching circuit, for preventing a power supply voltage drop when a subsystem is switched from an off state to an on state, the slew-rate controlled power switching circuit comprising: a transistor having a gate, a source, and a drain, the source coupled to a voltage output of a power supply that supplies a voltage V_cc, the drain coupled to a power input of the subsystem and forming an output of the circuit; and a gate resistor, the gate resistor having a first terminal and a second terminal, the first terminal of the gate resistor coupled to the gate of the transistor, the second terminal of the gate resistor forming an input to the circuit.

2. The circuit of Claim 1, wherein the voltage present at the drain of the transistor rises smoothly and nearly linearly when a signal present at the second terminal of the gate resistor is switched from a first state to a second state, the rate at which the voltage present at the drain of the transistor rises being proportional to the value of the gate resistor and to the value of a capacitance present between the gate and the drain.

3. The circuit of Claim 2, wherein the product of the value of the gate resistor and the value of the capacitance between the gate and the drain of the transistor has a value of at least 50 microseconds.

4. The circuit of Claim 2, wherein the value of the capacitance between the gate and the drain of the transistor varies as the voltage at the drain of the transistor rises to maintain a nearly linear rise between zero volts and Vcc volts at the drain over a period of at least 50 microseconds.

5. The circuit of Claim 1, wherein the gate resistor has a resistance of at least 10 kΩ.

6. The circuit of Claim 1, further comprising a pull-up resistor having a first terminal and a second terminal, the first terminal of the pull-up resistor coupled to the source, the second terminal of the pull-up resistor coupled to the second terminal of the gate resistor.

7. The circuit of Claim 6, wherein the pull-up resistor has a value of greater than 500 kΩ.

8. The circuit of Claim 1, further comprising a feedback capacitor having a first terminal and a second terminal, the first terminal of the feedback capacitor coupled to the first terminal of the gate resistor, the second terminal of the feedback capacitor coupled to the drain.

9. The circuit of Claim 8, wherein the feedback capacitor has a value of about .OlμF.

10. The circuit of Claim 9, wherein the gate resistor has a resistance of at least 10 kΩ.

11. The circuit of Claim 8, wherein the product of the value of the gate resistor and the sum of the value of the feedback capacitor and a value of a parasitic gate-to-drain capacitance of the transistor is at least 50 microseconds.

12. The circuit of Claim 1, wherein the transistor is one from the group of an NMOS transistor and a PMOS transistor.

13. The circuit of Claim 1, wherein the gate resistor and the transistor form a single integrated circuit.

14. The circuit of Claim 13, wherein the value of a capacitance between the gate and drain is set to vary to between about 100 pF and about 1000 pF according to changes in the difference between the voltage at the gate of the transistor and the voltage at the drain of the transistor, the value of the capacitance being set by increasing the area of the overlap capacitance between the gate and the drain of the transistor.

15. The circuit of Claim 13, wherein the value of a capacitance between the gate and drain is set to vary between about 100 pF and about 1000 pF according to changes in the difference between the voltage at the gate of the transistor and the voltage at the drain of the transistor, the value of the capacitance being set by decreasing the thickness of the dielectric of the transistor.