WO1995033354A1

WO1995033354A1 - Bus extended tst architecture

Info

Publication number: WO1995033354A1
Application number: PCT/FI1995/000293
Authority: WO
Inventors: Ove Strandberg; Patric Östergård
Original assignee: Nokia Telecommunications Oy
Priority date: 1994-05-26
Filing date: 1995-05-26
Publication date: 1995-12-07
Also published as: FI96373C; AU2568095A; FI942465A; GB2303522A; GB2303522B; DE19581671T1; FI942465A0; GB9624250D0; DE19581671B4; FI96373B

Abstract

In a digital cross-connect for implementing broadcasting and/or route protection a TST architecture is proposed, in accordance with the invention, in which architecture in parallel with the basic TS series connection (TS) formed by the time stage (12) and space stage (13) of the input side are connected one or more similar parallel TS series connections (TS) formed by the time stages and space stages. The signals of the input interface (11) are connected via the input bus (IB) in parallel to the inputs of all the time switches (121...12n) of the input side. The signals of the outputs of the space switches (13) are connected via the output bus (OB) in parallel to the inputs of the time switches (14) of the output side.

Description

Bus extended TST architecture

This invention relates to a TST architecture in a Digital Cross Connect (DXC) , in accordance with the preamble to Claim 1, for broadcasting or route protection as well as cross connect route algorithms, particularly for broadcast cases.

The recommendations CCITT G.707 define the Synchronous Transport Module (STM-1) signals of the first level of SDH signals. Other defined levels are STM-4 and STM-16. The recommendation CCITT G.708 defines the frame structure STM-N (in which N=l, 4, 16) . The STM-1 frame enables the transmission of 63 subsystem containers (e.g. TU-12, Tributary Unit, which can contain a two Mbit/s signal of an ordinary 30-channel PCM system) . The STM-N frames are assembled from several STM-1 signals, for example, an STM-4 signal is composed of four STM-1 signals.

Digital Cross Connect systems have been defined for SDH; the CCITT draft recommendations G.sdxc-1... -3. SDH DXC define

(abridging freely) : "A digital SDH cross connect is a cross connect device having two or more interfaces at SDH rates (G.707) and being at least able to terminate a transmission section and to controllably, transparently connect and reconnect virtual containers (VC) between the interface ports.

An SDH DXC can transmit traffic between different SDH levels and connect traffic between different signals. The use of the cross connect also includes a possibility for remote control of routing, route protection, initialization of reserve routes, connection from one signal to several signals (broadcasting) , and so on. The connections are usually bidirectional.

Cross connects can be implemented with a number of architectures. Known are the TS structure (Time-Space) and the TST structure (Time-Space-Time) , i.e. a time-space-time cross connect which quite well fulfils the conditions of non-blocking properties and implementability. A TST cross connect is also well adapted to very large cross connects, though in this case certain problems arise in expanding the system.

The architecture proposed in the invention can be considered to be an intermediate form of the T²S and TST architectures. In the T²S architecture, squared T switches comprise the first stage, and it is known that this is non-blocking but expensive. A number of DXC manufacturers use a T²S architecture. In the TST structure, problems occur in using the route protection of the SDH standard (Sub Network Connection Protection) and especially in broadcasting.

To solve the above problems, an n(TS)T architecture is proposed, which is characterized by the distinctive features set forth in Claim 1. Simplifying somewhat, it can be said that in the proposed architecture, a TST architecture is used for the routing and a parallel TS structure for broadcasting, whereby the parallel TS stages are connected by means of the input and output buses of the basic TS stage. In the general notation n(TS)T the letter n means a guaranteed amount of parallel outputs. In fact, the architecture according to the present invention combines the low cost of TST with the freedom of choice for the connections in the TS. The architecture in accordance with the invention can be realized with an architecture of a reasonable size.

According to the preferable embodiments of the invention, the S stages of the proposed architecture are expanded in the form of a full Benes network to handle larger digital -cross connect capacities. Alternatively, the expansion can be accomplished in the form of a reduced Benes network, whereby the broadcasting can be solved at a lower cost than in the case of a full Benes network. The reduced network is based on the use of a special reduction bus. In the architecture according to the invention, the n(TS)T routing, and also the broadcast routing, can be handled with a simple algorithm. For the user this architecture offers non- blocking normal routings through the cross connect and in addition non-blocking broadcasting 1 ->n. Subnetwork connection protection can be considered a special case of broadcasting, in which n=2. The maximum extent of the branching of the broadcasting 1 ->x is determined according to the number of parallel TS stages. Similarly, selection of the subnetwork connection protection (2 ->1) can be accomplished on the receiving side by freely routing the selected signal with the S switches.

The structure in accordance with the invention can be implemented advantageously by means of modular integrated circuits, for example, such that on the same card there is one T switch stage which comprises 16 time switches for STM-1 signals and one space switch 16^*16 for STM-1 signals.

In the following the invention is discussed in greater detail by means of embodiment examples with reference to the accompanying drawing in which:

Figure 1 shows a schematic block diagram of the n(TS)T architecture in accordance with the invention;

In Figure 2 an embodiment of a routing algorithm of the n(TS)T architecture is examined by means of a diagram, when n=3;

Figure 3 illustrates a problem situation in the n(TS)T architecture when n=2;

Figure 4 is an embodiment of the n(TS)T architecture which is of the form 32^*32 and in which n=2; Figure 5 shows an embodiment of the n(TS)T architecture which makes application of a reduced expansion of the S stage for broadcasting;

Figure 6 presents an embodiment of the n(TS)T architecture which makes application of fully reduced expansion of the S stage for broadcasting;

Figure 7 is a schematically illustrated routing algorithm of the reduced n(TS)T architecture in parallel TS stages for broadcasting when n=3; and

Figure 8 presents comparison tables of the numbers of chips with different parameter values and in different reduction cases.

Figure 1 shows a schematic block diagram of the n(TS)T architecture. It is evident from the figure that this architecture is based on conventional TST architecture in which the basic TS stage 121, 131 is extended with parallel TS stages 12n, 13n connected in parallel. The extension is carried out with two buses, whereby the input bus IB is between the input interface 11 and the first T stage 12, and the output bus OB is between the S stage 13 and the last T stage 14. T stage 14 is thus connected to output interface 15.

In Figure 1 the TST stage 121, 131, 14 of the uppermost row implements the normal routings through the switch. Broadcasts are handled by the TS stages 12n, 13n of the extension. The broadcasting works in such a way that the input bus IB "copies" the signals coming from input interface 11 to all the TS stages 12. The desired broadcast signals can be individually selected from the TS stage 122, 132; 123, 133, ... because via the TS stage only one signal is connected from the broadcast signal. This is in fact the normal operation of the TST switch. In the n(TS)T architecture shown in Figure 1, the routing of the normal point-to-point links and one broadcast signal can be implemented with some TST algorithm that is known per se. If broadcast signals have to be routed from the second, third, ..., n'th parallel TS stage 122, 132; 123, 133; ..., then there will exist empty slots on the output bus OB as a result of the TST algorithm. The broadcast algorithm has to route the broadcast signals to these empty time slots of the TS stages. In considering the routing of one specific broadcast signal l-> x in which x is the broadcast degree, an alternative of the (n-l)TS stage can be offered for it. Figure 2 gives the example n(TS)T, in which n=3 and in which the connection of the signals from the input bus IB through the TS stages to the output bus OB is examined (in Figure 2 the marking T and Output refer to the last T stage 14 and output interface 15, which are not shown in this figure) . In the example in Figure 2, for purposes of illustration the size of the DXC is only 4^*4 and there are only 4 time slots. In this example the broadcast 1 ->3 is guaranteed when n = x = 3. The numbers in the squares indicate the desired output port 1...4. By means of the basic TS stage 121, 131, after space switch 13 the free slots outlined with a dark line in the figure are arranged for the output bus OB, and the signals obtained from the parallel TS stage can be fitted to these free slots in the manner described.

The TS routing nevertheless runs into a contradiction because the same input of the TS stage can have many broadcast signals. This situation is illustrated in Figure 3, in which for simplicity's sake the n(TS)T situation is examined when n=2. The contradictory situation is shown on the left-hand side of the figure, in which the broadcast signals are brought from the input bus IB to the second row of the T stage, i.e. to the second input. If more than one broadcast signal tries to get into the same time slot of the output bus OB via S switch 13, a blocking situation arises. The blocking situation is due to the nature of TST routing because the result of TST routing could set the available empty slots to the same time slot. In the worst case all the empty slots are located in the same time slot. It must nevertheless be noted that the conflict situation arises when signals are competing in the same TS stage and not from competition between signals in different TS stages. To circumvent the blocking, the TST algorithm must receive feedback on a possible contradiction arising from the result of the TS routing. This means that in these cases the TST and TS routing algorithms have to be recursively executed again until an acceptable solution is found. It is thus observed that broadcast routing is carried out advantageously in two phases, first for the parallel TS stages and then for the entire TST.

Recursive execution of the different parts of the routing leads to slow execution. For this reason, the TST algorithm can be developed to incorporate the TS routing requirements. The final n(TS)T algorithm will then at one launch solve the configuration with no blocking. A suitable broadcast degree x can be found without an expensive hardware solution as is the case with the TS architecture.

In principle, in the n(TS)T architecture the number of parallel ports n indicates the guaranteed broadcast degree. The algorithm can nevertheless be developed so as to yield a broadcast degree that is greater than n. This nevertheless involves a probability of blocking because with a broadcast degree that exceeds the guaranteed broadcast degree (=n) throughgoing routing will not succeed in all cases. Routing with an "over-the-limit" broadcast degree calls for considerably more execution time than does a simple routing algorithm. One way of implementing "over-the-limit" broadcasting in a non-blocking manner is to carry out the remaining multiplication of the n degree in the TS broadcast stages in such a way that the broadcast signal is copied in the time switches. Accordingly, the TST routing is not disturbed. The TS broadcast stages realize filling in of the gaps for all the "over-the-limit" broadcast signals. The non-blocking property is apparent if sufficient copying capacity can be found in the time switch of the broadcast stages.

Route protection is implemented on the output side by copying the signal to be protected into two signals (W, P, working, protecting) and routing them in the same way as in the broadcast case. Implementation of route protection on the receiving side is carried out in such a way that both protection signals ( , P) are brought to a different TS stage. The protected signal (W) is brought to the first TS stage, 121 and 123 in Figure 1, and the protecting signal (P) is brought to n at the TS stage, 12n and 13n in Figure 1. Both signals are routed in the same time slot to the same port. The S switches select the signal to be throughswitched.

Discussed in the above is one possible DXC application which makes use of, for example, 16^*16 modules that today can be easily implemented on the same card or with an integrated circuit, i.e. a chip. When larger units are needed, for example, 128^*128 or 256^*256, in all architectures expansion of the n(TS)T involves an ordinary problem of expanding the S stage. The chip unit could possibly be expanded but the large sizes mentioned are not at the present moment sensible as a single-chip solution, in which case the only alternative that remains is some type of network solution. The Benes solution, which requires a minimum of resources for expanding the switch stage, involves the least costs and nevertheless makes possible a non-blocking solution for the S stage. The number of T stages increases linearly as the DXC grows.

A Benes solution means that every S switch of the n(TS)T must be implemented with a full Benes network. In this case each broadcast stage (TS) can route a broadcast signal to any desired time slot. Figure 4 shows the principle underlying this solution, considering as an example an architecture that is expanded to the size 32^*32 and in which n=2. The space switches 13 (S) are of the form 16^*16 and there are 8 time switches 12 (T) . In each space stage at any given time there is a link from each space switch 13S1, 13S2 to each successive space switch 13S2 and, similarly, to 13S3.

A full implementation of the Benes network is nevertheless costly. Accordingly, a reduction of the Benes network whereby the number of chips can be cut is considered to be more cost- effective. In this case the reduction means that the number of broadcast stages (TS) is minimized and that a reduction bus RB is used to connect the outputs of the centremost space switches

1352 of the broadcast stages in parallel to the last switches

1353 of the space stage. Two different kinds of reduction can be used: the reduction of the broadcast degree in Figure 4 and the full reduction in Figure 5.

Broadcast reduction only involves broadcast stages. The last S stage of the full Benes network, S3 in Figure 5, is used fully. S3 performs the same action for all the TS stages, whereby S3 connects the signals bound to it to its targeted output. Thus for all the broadcast stages only one set of S3 switches is needed. The reduced network is non-blocking because the maximum amount of signals N for a given time slot can be switched with only one S3 subset. The reduced Benes network is multiple and a maximum of N signals can be routed to any output of the reduced Benes network. Thus there occurs no blocking when routing broadcasts provided that the degree x of the broadcast is smaller than or as large as the number of available parallel TS stages, n≥x. In the example in Figure 5, N=32 and n=3. The last T stage is not shown in Figure 5. In the same manner as in Figure 4, the space switches are of the size 16^*16.

Reduction can also be implemented in the full mode, as was already mentioned. Here, the output bus OB and the subset S3 that is common for the broadcast can be deleted. The reduction bus RB is then connected directly in between the second space stage S2 and the third space stage S3. Figure 6 shows the principle underlying full reduction, in which N=32 and n=3. The last T stage is not shown in Figure 6.

The basic problem of the configuration remains the same: the empty slots still reside in the same time slot but possibly on another "output" than in the above solutions. The last space stage (S3) of the Benes network of the TST part simply connects the signals to their target output, i.e. performs the last reordering. The empty slots before the space switches S3 - there may be a maximum of N of these empty slots in the same time slot - are accessible through an identical number of outputs of the reduced Benes network. The multiple Benes network makes possible access of broadcast signals (a maximum of N in the same time slot) to these outputs of the Benes network regardless of the source of the signal. By properly positioning the empty slots coming from the TS stage it is possible completely to avoid the routing contradictions that would cause blocking.

In the following the routing algorithm of the Benes network is discussed in greater detail. The algorithm presented in Figure 4 for the normal Benes network is in principle of the same kind as that already discussed in connection with Figures 2 and 3. Expansion of the Benes network of the space stage nevertheless leads to a more complex situation because the algorithm has to be developed to handle routing over the Benes network. The routing is not difficult per se but the extent of it slows down the execution.

The algorithms for reduced architectures are different than with a normal architecture. The main difference between these three algorithms of the above-described case is how much the TST and TS routings or the routings of the different TS stages depend on each other. The normal Benes architecture has the loosest connectivity, i.e. the TST and TS routings can be done mainly independently of each other. On the other hand, the fully reduced architecture has the tightest connectivity, i.e. there is a strong dependence between the TST routing and the routings of the different TS stages. The tighter the constraints imposed by the architecture, the more complex and slower the algorithm will be. The broadcast reduced architecture has the same loose connectivity between the TST and TS stages as does the normal Benes architecture, but the algorithm is nevertheless more complex because there is tighter connectivity between the TS stages.

The reduced broadcast differs from the routing of the normal full Benes network in respect of the routing done through the space stage. Because the Benes network is reduced, all the broadcast signals have to be switched via the same reduction bus RB. The bus RB does not constitute a capacity problem because the N line of the bus can accommodate a maximum of N signals. The routing is nevertheless not as free as in the normal Benes case in which an individual routing can be done in each TS stage. When using a reduction bus, all the broadcast stages must be routed, i.e. dealt with, in the same work phase. The normal Benes routing principle can be used but the problem is more extensive.

Figure 7 shows an example of the routing of the TS stages of a reduced architecture in respect of broadcasting when N=8 and n=3. In the fully reduced case, both the TST and TS stages have to be considered together. Here all the signals share the reduction bus RB. This means that in the TST part empty slots must be left in such positions that the TS stage can access this bus. The routing of the Benes network of the TST stage is nevertheless in principle the same as in the above reduced broadcast architecture. In fact, the routing example in Figure 7 represents a fully reduced architecture when n=2. The upper stage shows the TST stage.

From Figure 7 the output bus OB can be deleted and replaced with the last T switch stage 14 in order to implement a fully reduced architecture. Figure 7 also illustrates how the signals in the SI switch stage have to be routed correctly to avoid collisions on the reduction bus; in this example, a signal addressed to output 2 is shown as well as its wrong and right routing possibility in the SI switch.

One way to realize a "direct try" algorithm for the fully reduced case is to book the empty slots before routing to a specific broadcast signal; this is shown with the heavily outlined squares at the output of the S3 stage. These dummy signals are then normally routed through the TST stage, whereby they yield the target positions for the broadcast signals on the reduction bus RB. The TS stages route^"the broadcast signals to these positions. The booking of the empty slots has of course to take into account the contradictions of the TS routing and the common routing in the reduced Benes network of the broadcast stages.

In the following, "over-the-limit" broadcasting is examined. The algorithm of the "over-the-limit" broadcast degree meets with difficulties already in the normal Benes expansion. The S switch in the Benes form does not offer free copying to outputs. This is due to the fact that signals to be multiplied overlap in attempting to use the same network link in a network of space switches. But here too, as in the above, what is involved is how good the operation can be made. The variables to be used in the optimization are N, n, the traffic load, the Benes implementation and the broadcast size (l->x) .

In the following, an estimation of resources is examined for the architecture in accordance with the invention. Among the components of the example structure for the architecture is a T switch whose length is 63, i.e. there are 63 time slots. The size of the space switch is 16^*16. Each switch can be implemented with a single-chip architecture, whereby the number of chips is: a) Single chip:

(n+l)^*N^*T+n^*S

In the expanded architecture the numbers of chips are:

b) Normal Benes network (Full Benes) :

(n+1) ^*N^*T+n^*3^* (N/16) ^*S

c) Broadcast degree reduced (Broadcast) :

(n+1) ^*N^*T+n^*2+2) ^* (N/16) ^*S

d) Fully reduced (All reduced) :

(n+1) ^*N^*T+n^*2+l) ^* (N/16) ^*S

The above numbers can be compared with the T²S architecture (Sqr(T)S) , in which:

T²S: N^2*T+N^*S

Figure 8 gives comparison tables showing the numbers of chips with different values of the parameters. It can be seen that the number of chips with the architecture according to the invention is moderately small with a small degree of broadcast size (smaller than n) compared with the T²S architecture. In larger systems, i.e. N is large, the difference in favour of the architecture in accordance with the invention becomes all the more pronounced.

The way in which the TS modules, or chips, as well as the buses are implemented has a large effect on the feasibility. As structures, the buses are in and of themselves simple although the large size may cause problems. Nevertheless, compared with many other architectures, for example, the T²S structure, the bus in the system in accordance with the invention can be much more easily implemented when n is small. The number of signals of the TS routing part is relatively small. At the most, half of the load can be routed via the TS stage when n=2 and all the signals are broadcast signals (x=2) . In this case, the execution time remains clearly smaller than the normal execution time of a fully loaded TST algorithm.

The n(TS)T architecture in accordance with the invention is very modular in respect of the desired degree of broadcasting. Thanks to this modularity, the user of the DXC can expand and/or modify his DXC hardware as needed. The architecture accomplishes the desired broadcasts without blocking. The configuration algorithm is relatively straightforward and thus fast. The architecture can be used, as was mentioned above, to accomplish expansion advantageously up to a DXC size of 128^*128. When going over this size, for example, owing to the size of the space switch, a simple Benes network does not suffice, but it must be further expanded.

From the above discussion it can be noted, on the other hand, that the broadcast stages are not used very effectively except at the "over-the-limit" broadcast degree. With the "over-the- limit" broadcast degree the algorithm becomes complex and this results in a longer execution time and/or cases of blocking.

In the n(TS)T architecture in accordance with the invention, use is made of parallel broadcast stages by means of which processing of the broadcast algorithm can be realized with the smallest possible costs. The largest advantages of the architecture presented are obtained with small broadcast degrees (x is small) because in this case the costs caused by the number (n) of the parallel stages can be better exploited for processing the traffic.

Described here is a way of protecting SDH signals. Of course, other signals which have a similar structure, such as PDH signals, can use the same mode of protection.

Claims

1. In a digital cross-connect for implementing broadcasting and/or route protection, a TST architecture which comprises input interfaces and output interfaces of the signal lines as well as in between them time switches (T) , space switches (S) of the input side and time switches (T) of the output side, characterized in that in parallel with the basic TS series connection (TS) formed by the time stage (12) and the space stage (13) of the input side are connected one or more similar parallel TS series connections (TS) formed by the time stages and space stages, whereby from the input interface (13) the signals are connected via the input bus (IB) in parallel to the inputs of all the time switches (121...12n) of the input side and whereby the signals from the outputs of the space switches (13) are connected via the output bus (OB) in parallel to the inputs of the time switches (14) of the output side (Figure 1) .

2. A TST architecture in accordance with claim 1, characterized in that the space stage (131...13n) at any given time is expanded in the form of a full Benes network, whereby the expansion is of the form space-space-space (S1-S2-S3) and whereby from the output of each parallel TS series connection there is an access to each time slot of the time switches (T) of the output side (Figure 4) .

3. A TST architecture in accordance with claim 1, characterized in that the space stage (13) is expanded in the form of a reduced Benes network such that in the basic TS series connection (121, 131) and in the first parallel TS series connection (122, 132) the expansion is of the form space-space-space (S1-S2-S3) and in the other parallel TS series connections the expansion is of the form space-space- space (S1-S2) , whereby the outputs of the space stages (S2) of these last-mentioned parallel TS series connections are connected in parallel via a reduction bus (RB) to the inputs of the space stage (132/S3) of the output stage of the first parallel TS series connection (Figure 5) .

4. A TST architecture in accordance with claim 1, characterized in that the space stage (13) is expanded in the form of a fully reduced Benes network such that in the basic TS series connection (121, 131) the expansion is of the form space-space-space (S1-S2-S3) and in the parallel TS series connections (122...n, 132...n) the expansion is of the form space-space (S1-S2) , whereby the outputs of the space stages (S2) of the parallel TS series connections are parallel connected via the reduction bus to the inputs of the space stage (131/S3) of the output side of the basic TS series connection (Figure 6) .

5. An algorithm for routing a broadcast signal to x output time slots in a digital cross connect TST architecture in accordance with claim 1 or 2, in which TST architecture there is a parallel n basic and parallel TS series connection, whereby x ≤ n characterized in that the broadcast signal is copied to the inputs of the time switches (12) of the basic and parallel TS series connections, whereby the algorithm is used to search for the free slots, which are on the output bus (OB) , for broadcast signals (Figure 2) .

6. An algorithm in accordance with claim 5, characterized in that the total algorithm for the TST routing comprises a separate subalgorithm for the TS routing, whereby a feedback derived from the solution to the TS routing is brought to the TST total algorithm and whereby the TS routing is repeated with new parameters if the TST subalgorithm produces a blocking situation.

7. An algorithm according to claim 5 in the TST architecture in accordance with claim 3, characterized in that the algorithm solves all the routings of the TS series connections (12, 13) as a shared problem space (Figure 7) .

8. An algorithm in accordance with claim 5 in a TST architecture in accordance with claim 4, characterized in that the algorithm solves all the routings of the TS series connections (12, 13) as well as the routings of the TST entity (12, 13, 14) as a shared problem space.

9. An algorithm according to claim 8, characterized in that in the algorithm the free spaces are first booked from the output of the space stage (13/S3) for the broadcast signals, after which the algorithm solves all the routings of the TS series connections (12, 13) as well as the routings of the TST entity (12, 13, 14) as a shared problem space.