WO1996004712A1

WO1996004712A1 - Tuning amplifier

Info

Publication number: WO1996004712A1
Application number: PCT/JP1995/001526
Authority: WO
Inventors: Takeshi Ikeda; Tadataka Ohe; Tsutomu Nakanishi
Original assignee: Takeshi Ikeda; Tadataka Ohe; Tsutomu Nakanishi
Priority date: 1994-08-05
Filing date: 1995-08-01
Publication date: 1996-02-15
Also published as: AU3087395A

Abstract

A tuning amplifier which can be easily formed in an integrated circuit and whose tuning frequency and maximum damping quantity can be independently adjusted. The amplifier comprises two phase shifters (10C and 30C), each including an operational amplifier with its inverting input terminal connected with a resistor, a series circuit of a capacitor and a variable resistor across which an input signal voltage is applied, and a resistor for feeding back the output of the operational amplifier to the inverting input terminal; and an addition circuit including a feedback resistor (70) and an input resistor (90) to combine the output signal from the phase shift circuit (30C) of the post stage with the input signal to the input terminal (90) in a predetermined proportion.

Description

Description Tuning amplifier Technical field

The present invention relates to a tuning amplifier that can be easily integrated, and more particularly to a tuning amplifier that can arbitrarily adjust a tuning frequency and a maximum attenuation without interfering with each other. Background art

Various amplifier circuits using active elements and reactance elements have been proposed and put into practical use as tuning amplifiers.

In conventional tuning amplifiers, adjusting the tuning frequency changes the maximum attenuation, and adjusting the maximum attenuation changes the tuning frequency.Therefore, it is impossible to adjust the tuning frequency and the maximum attenuation without interfering with each other. It was extremely difficult.

Further, it has been difficult to form a tuned amplifier capable of adjusting the tuning frequency and the maximum attenuation by using an integrated circuit.

Therefore, the present invention has been conceived to solve such a problem. Disclosure of the invention

The tuned amplifier of the present invention comprises:

An input impedance element that receives an input signal at one end, and a feedback impedance element that receives a feedback signal at one end; an addition circuit that adds the input signal and the feedback signal;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit comprising a third resistor and a capacitor connected to the other end of the first resistor, wherein a connection portion of the third resistor and the capacitor is connected to the second resistor. Two connected to the non-inverting input terminal of the differential input amplifier A phase shift circuit;

The two phase-shift circuits are cascaded, and the signal added by the adder circuit is input to the preceding phase-shift circuit of the two cascade-connected two phase-shift circuits. A signal output from the phase shift circuit is input to one end of the return impedance element as the return signal, and the output of one of these two phase shift circuits is extracted as a tuning signal.

Also, the tuning amplifier of the present invention

An input impedance element to which an input signal is input to one end; a feedback impedance element to which a feedback signal is input to one end; an addition circuit for adding the input signal and the return signal;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit comprising a third resistor and a capacitor connected to the other end of the first resistor, wherein a connection portion of the third resistor and the capacitor is connected to the second resistor. Two phase shifters connected to the non-inverting input terminal of the differential input amplifier,

A non-inverting circuit that outputs the input AC signal without changing the phase,

A signal obtained by cascading each of the two phase shift circuits and the non-inverting circuit, and adding the first circuit of the plurality of cascade-connected circuits by the addition circuit. And the signal output from the last-stage circuit is input to one end of the feedback impedance element as the return signal, and the output of any of the plurality of circuits is extracted as a tuning signal.

Also, the tuning amplifier of the present invention

An input impedance element having an input signal input to one end thereof, and a feedback impedance element having a return signal input to one end thereof; an addition circuit for adding the input signal and the return signal;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor; and an inverting input terminal and an output terminal of the differential input amplifier. A second resistor connected between the first resistor and a second resistor connected to the other end of the first resistor; A series circuit comprising a third resistor and an inductor, and two phase-shift circuits having a connection between the third resistor and the inductor connected to a non-inverting input terminal of the differential input amplifier;

The two phase shift circuits are vertically connected, and the signal added by the adder circuit is input to the preceding phase shift circuit in the two vertically connected two phase shift circuits, A signal output from a subsequent phase shift circuit is input to one end of the feedback impedance element as the feedback signal, and the output of one of these two phase shift circuits is extracted as a tuning signal.

Also, the tuning amplifier of the present invention

An input impedance element to which an input signal is input to one end; and a return impedance element to which a return signal is input to one end; an addition circuit for adding the input signal and the return signal;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the first resistor, and a series circuit including a third resistor and an inductor connected to the other end of the first resistor. Two phase shifting circuits connected to the non-inverting input terminal of the differential input amplifier;

A signal obtained by cascade-connecting each of the two phase-shift circuits and the non-inverting circuit, and adding the first stage circuit of the plurality of cascade-connected circuits by the addition circuit. And a signal output from the last-stage circuit is input to one end of the feedback impedance element as the feedback signal, and the output of one of the plurality of circuits is extracted as a tuning signal.

Also, the tuning amplifier of the present invention

An input impedance element to which an input signal is input to one end; a feedback impedance element to which a feedback signal is input to one end; an addition circuit for adding the input signal and the feedback signal;

One end of a first resistor is connected to the inverting input terminal, and AC is supplied through the first resistor. A differential input amplifier to which a signal is input, a second resistor connected between an inverting input terminal and an output terminal of the differential input amplifier, and a third resistor connected to the other end of the first resistor. A first phase shift circuit including a series circuit including a third resistor and a capacitor, wherein a connection portion of the third resistor and the capacitor is connected to a non-inverting input terminal of the differential input amplifier;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit including a third resistor and an inductor connected to the other end of the first resistor, and a connection portion of the third resistor and the inductor. A second phase shift circuit connected to the non-inverting input terminal of the differential input amplifier;

The first and second phase shift circuits are cascaded, and the signal added by the adder circuit is input to the preceding phase shift circuit of the two cascade connected phase shift circuits. A signal output from a subsequent phase shift circuit is input to one end of the return impedance element as the feedback signal, and one of the outputs of the first and second phase shift circuits is used as a tuning signal. Taken out.

Also, the tuning amplifier of the present invention

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the first resistor, and a series circuit including a third resistor and a capacitor connected to the other end of the first resistor. A first phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input through the first resistor; and an inverting input terminal and an output terminal of the differential input amplifier. A second resistor connected between the first resistor and a second resistor connected to the other end of the first resistor; A second phase shift circuit including a series circuit including a third resistor and an inductor, wherein a connection between the third resistor and the inductor is connected to a non-inverting input terminal of the differential input amplifier;

Wherein each of the first and second phase shift circuits and the non-inverting circuit are cascaded, and the first circuit of the plurality of cascaded circuits is added by the adding circuit to the first circuit. The signal output from the last stage circuit is input to one end of the feedback impedance element as the feedback signal, and the output of one of the plurality of circuits is taken out as a tuning signal.

In each of the above-mentioned tunable amplifiers, the sum of the phase shift amounts to 0 ° due to the entirety of the two phase shift circuits or the entirety of the two phase shift circuits and the non-inverting circuit, and the amplification degree of each circuit is reduced. Perform tuning operation by adjusting and setting the loop gain to almost 1.

Also, the tuning amplifier of the present invention

An input impedance element to which an input signal is input to one end, and a return impedance element to which a return signal is input to one end; an addition circuit for adding the input signal and the return signal;

A phase inversion circuit that inverts the phase of the input AC signal and outputs the inverted signal;

A signal obtained by cascading each of the two phase shift circuits and the phase inverting circuit, and adding the first stage circuit of the plurality of cascaded circuits by the adding circuit. And a signal output from the last-stage circuit is input to one end of the feedback impedance element as the feedback signal, and the output of one of the plurality of circuits is extracted as a tuning signal. Also, the tuning amplifier of the present invention

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit including a third resistor and an ingector connected to the other end of the first resistor, wherein a connection portion of the third resistor and the inductor is connected to the second resistor. Two phase shifters connected to the non-inverting input terminal of the differential input amplifier,

A cascade connection of each of the two phase shift circuits and the phase inversion circuit, and a signal added by the addition circuit to a first-stage circuit of the plurality of cascade-connected circuits. At the same time, the signal output from the last-stage circuit is input to one end of the feedback impedance element as the feedback signal, and the output of one of the plurality of circuits is extracted as a tuning signal.

Also, the tuning amplifier of the present invention

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit comprising a third resistor and a capacitor connected to the other end of the first resistor, wherein a connection portion of the third resistor and the capacitor is connected to the second resistor. A first phase shift circuit connected to the non-inverting input terminal of the differential input amplifier;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a second resistor connected to the other end of the first resistor. A second phase shift circuit including a series circuit including a third resistor and an inductor, wherein a connection portion of the third resistor and the inductor is connected to a non-inverting input terminal of the differential input amplifier;

Wherein each of the first and second phase shift circuits and the phase inverting circuit are vertically connected, and an addition circuit is added by the addition circuit to a first stage circuit of the plurality of vertically connected circuits. And the signal output from the last-stage circuit is input to one end of the feedback impedance element as the feedback signal, and the output of t or any of the plurality of circuits is taken out as a tuning signal. It is.

In each of the tunable amplifiers described above, the total phase shift amount is 0 ° due to the entire two phase shift circuits and the phase inverting circuit, and the loop gain is set to almost 1 by adjusting the amplification of each circuit. Thus, a tuning operation is performed. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a circuit diagram showing a first embodiment of the tuning amplifier of the present invention,

FIG. 2 is a circuit diagram showing the configuration of the phase shift circuit of the preceding stage shown in FIG. 1,

FIG. 3 is a vector diagram showing a relationship between an input / output voltage of the phase shift circuit shown in FIG. 2 and a voltage appearing on a capacitor or the like;

FIG. 4 is a circuit diagram showing the configuration of the subsequent phase shift circuit shown in FIG. 1,

FIG. 5 is a vector diagram showing the relationship between the input and output voltages of the phase shift circuit shown in FIG.

FIG. 6 is a circuit diagram showing the tuned amplifier of the present invention using a transfer function K1, FIG. 7 is a circuit diagram obtained by converting the circuit shown in FIG. 6 according to Mira's theorem, and FIG. FIG. 1 is a characteristic curve diagram showing the relationship between the resistance ratio of the input resistance and the feedback resistance and the maximum attenuation in the tuned amplifier shown in FIG.

FIG. 9 is a circuit diagram showing a partially modified example of the tuning amplifier shown in FIG. 1,

FIG. 10 is a circuit diagram showing a second embodiment of the tuning amplifier of the present invention,

FIG. 11 is a circuit diagram showing the configuration of the phase shift circuit of the preceding stage shown in FIG. 10;

Fig. 12 shows the input / output voltages of the phase shift circuit shown in Fig. Vector diagram showing the relationship with pressure,

FIG. 13 is a circuit diagram showing the configuration of the subsequent phase shift circuit shown in FIG. 10;

FIG. 14 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit shown in FIG.

FIG. 15 is a circuit diagram showing a partially modified example of the tuning amplifier shown in FIG. 10, FIG. 16 is a circuit diagram showing a third embodiment of the tuning amplifier of the present invention,

FIG. 17 is a circuit diagram showing a fourth embodiment of the tuning amplifier of the present invention,

FIG. 18 is a circuit diagram showing a fifth embodiment of the tuning amplifier of the present invention,

FIG. 19 is a circuit diagram showing a sixth embodiment of the tuning amplifier of the present invention;

FIG. 20 is a circuit diagram showing a tuned amplifier according to a seventh embodiment of the present invention;

FIG. 21 is a circuit diagram showing an eighth embodiment of the tuning amplifier of the present invention,

FIG. 22 is a circuit diagram showing a ninth embodiment of the tuning amplifier of the present invention;

FIG. 23 is a circuit diagram showing a tenth embodiment of the tuning amplifier of the present invention,

FIG. 24 is a diagram showing a connection form between a phase shift circuit and a non-inverting circuit,

FIG. 25 is a diagram showing a connection form between a phase shift circuit and a phase inversion circuit,

FIG. 26 is a circuit diagram showing a configuration of a phase shift circuit in which the variable resistor of the CR circuit in the phase shift circuit is replaced by FET.

FIG. 27 is a circuit diagram showing a configuration of a phase shift circuit in which the variable resistor of the LR circuit in the phase shift circuit is replaced by FET.

FIG. 28 is a circuit diagram showing a configuration of a phase shift circuit in which a capacitor of a CR circuit in the phase shift circuit is replaced with a variable capacitance diode.

FIG. 29 is a circuit diagram showing the configuration of a phase shift circuit in which the ingk of the LR circuit in the phase shifting circuit is replaced with a variable ingkta.

FIG. 30 is a plan structural view of the variable inductor shown in FIG. 29,

FIG. 31 is a detailed structural diagram of the variable inductor shown in FIG. 30;

FIG. 32 is an enlarged sectional view taken along line A—A of FIG. 31;

FIG. 33 is a plan view showing a modification of the variable inductor shown in FIG. 30, FIG. 34 is a plan view showing another modification of the variable inductor shown in FIG. 30, and FIG. FIG. 5 is a plan view showing another modification of the variable inductor shown in FIG. 30, FIG. 36 is a plan view showing another example of the variable inductor shown in FIG. 29, FIG. 37 is a detailed view of the variable inductor shown in FIG. 36,

FIG. 38 is an enlarged sectional view taken along the line BB of FIG. 37,

FIG. 39 is a circuit diagram showing a configuration of a capacitance conversion circuit used in the tuning amplifier of the present invention,

FIG. 40 is a circuit diagram showing the capacitance conversion circuit shown in FIG. 39 using a transfer function K4.

FIG. 41 is a circuit diagram obtained by converting the circuit shown in FIG. 40 by Miller's theorem, FIG. 42 is a simplified circuit diagram of the capacitance conversion circuit shown in FIG. 39, and FIG. The figure is a circuit diagram showing the configuration of a capacitance conversion circuit using an emitter follower circuit in the first stage,

Fig. 44 is a circuit diagram showing the configuration of a capacitance conversion circuit using a source follower circuit in the first stage.

FIG. 45 is a circuit diagram showing a configuration of an inductance conversion circuit used in the tuning amplifier of the present invention;

FIG. 46 is a circuit diagram showing the configuration of an inductance conversion circuit in which the entire amplifier including the two operational amplifiers included in FIG. 45 is replaced with an emitter follower circuit. A circuit diagram showing a configuration in which the sense conversion circuit is realized by a source follower circuit;

FIG. 48 is a circuit diagram showing another example of the inductance conversion circuit.

FIG. 49 is a circuit diagram in which portions necessary for the operation of the phase shift circuit of the present invention are extracted from the configuration of the operational amplifier. BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment)

FIG. 1 is a circuit diagram showing a configuration of a tuned amplifier according to a first embodiment. Each of tuned amplifiers 1 shifts the phase of an input signal by a predetermined amount to obtain a total at a predetermined frequency. Two phase shift circuits 10 C and 30 C that perform a phase shift of 0 ° with the feedback resistor 70 and the input resistor 74 (the input resistor 74 has n times the resistance of the feedback resistor 70) A predetermined ratio between the signal output from the subsequent phase shift circuit 30 (return signal) and the signal input to the input terminal 90 (input signal). And an adder circuit for adding the values.

FIG. 2 is a circuit diagram extracted from the configuration of the preceding phase shift circuit 10 C shown in FIG. 1, and includes an operational amplifier (operational amplifier) 12, which is a type of differential input amplifier, and an input terminal 22. The capacitor 14 and the variable resistor 16 that shift the phase of the signal input to the non-inverting input terminal of the operational amplifier 12 by a predetermined amount, and the resistor inserted between the input terminal 22 and the inverting input terminal 18 and a resistor 20 inserted between the output terminal 24 of the operational amplifier 12 and the inverting input terminal.

In this specification, it is assumed that the operational amplifier 12 and the like operate ideally, and when a deviation from the ideal becomes a problem in the actual circuit design, an explanation will be added each time.

In the phase shift circuit 10C having such a configuration, when a predetermined AC signal is input to the input terminal 22, the voltage VR1 appearing at both ends of the variable resistor 16 is applied to the non-inverting input terminal of the operational amplifier 12. .

Also, since there is no potential difference between the two inputs (inverting input terminal and non-inverting input terminal) of the operational amplifier 12 shown in FIG. 2, the potential of the inverting input terminal of the operational amplifier 12, the capacity of the capacitor 14 and the variable resistor 16 It becomes equal to the potential of the connection point. Therefore, the same voltage VC1 appears at both ends of the resistor 18 as the voltage VC1 appearing at both ends of the capacitor 14.

Here, when the resistance values of the resistor 18 and the resistor 20 are equal, the same current flows through these two resistors 18 and 20, so that the voltage VC1 appears at both ends of the resistor 20. Moreover, the voltage VC1 appearing at each end of these two resistors 18 and 20 has the same direction in terms of the vector. Considering the inverting input terminal (voltage VR1) of the operational amplifier 12, the resistance The voltage obtained by adding the voltage VC1 between both ends of the circuit to the vector is the input voltage Ei, and the voltage obtained by subtracting the voltage VC1 of the resistor 20 from the vector becomes the output voltage Eo.

FIG. 3 is a vector diagram showing a relationship between an input / output voltage of the phase shift circuit 10C and a voltage appearing on a capacitor or the like.

As shown in this vector diagram, the voltage VR1 appearing across the variable resistor 16 and the voltage VC1 appearing across the capacitor 14 are 90 ° out of phase with each other. The sum of the input voltages becomes the input voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VR1 across the variable resistor 16 and the voltage VC1 across the capacitor 14 change along the circumference of the semicircle shown in FIG. .

The output voltage Eo is obtained by vectorically subtracting the voltage VC1 from the voltage VR1. Considering the voltage VR1 applied to the non-inverting input terminal, the input voltage Ei and the output voltage Eo differ only in the direction in which the voltage VC1 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and the phase of the input / output voltage can be represented by an isosceles triangle with the input voltage Ei and the output voltage Eo as hypotenuses and the base at twice the voltage VC1, and the amplitude of the output signal is Irrespective of the amplitude of the input signal, it can be seen that the phase shift amount is represented by 01 shown in FIG.

Also, as is apparent from FIG. 3, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR1 is theoretically It changes from 90 ° to 0 ° as it changes to ∞. The phase shift amount 01 of the entire phase shift circuit 10C is twice that, and changes from 180 ° to 0 ° according to the frequency.

Next, the relationship between the input and output voltages described above is quantitatively verified.

When the input voltage E i is applied to the input terminal 22, the current flowing from the input terminal 22 to the output terminal 24 through the resistors 18 and 20 through the resistors 18 and 20 is I, and the resistance values of the resistors 18 and 20 are equal. Assuming that r, the voltage across each of the resistors 18 and 20 is-I · r.

By the way, as described above, since there must be no potential difference between the two inputs of the operational amplifier 12 shown in FIG. Between

VRl = Eo- (I T)

= Eo + Ir

. •• E o = VRl— I · r… (: 1)

Also, in order to prevent a potential difference between the two inputs of the operational amplifier 12, the value obtained by adding the voltage VC1 across the capacitor 14 and the voltage across the resistor 18—Ir must be 0. VC1 + (-IT) = 0

.-. VC1 = IT ~ (2). From equations (1) and (2),

Eo = VRl-VCl （(3)

The voltage Ei applied to the input terminal 22 is the sum of the voltages VR1 and VC1 at both ends of the variable resistor 16 and the capacitor 14.Therefore, between these voltages,

Ei = VRl + VCl… (

There is a relationship. From equations (3) and (4),

Eo VR1-VC1

ET VR1 + VC1

1

R

_ VR1-VC1 11 C s

0 one VR1 + VC1 ^1- ~

R +

C s

₌ CR s-1 1-s

CR s + l 1 + T s

Becomes Here, C represents the capacitance of the capacitor 14, R represents the resistance of the variable resistor 16, and the time constant of the CR circuit composed of the capacitor 14 and the variable resistor 16 is T (= CR).

Substituting s = jω in equation (5) and transforming,

^ 1-j ωΤ

Εθ = -— -Τ- ~ "7 1

1 + j ωΤ

1— (ωΤ) ² — j · 2ωΤ

E (6)

1 + (ωΤ) ²

Becomes When the absolute value of the output voltage Εο is obtained from equation (6),

D. Is one (ωΤ) ² } ² + 4 (ωΤ) ² _

Εο | = —— ~ τ- ₂ Ε

1 + (ω I) ¹

1 + 2 (ωΤ) ² + (ωΤ) ⁴

1 + (ωΤ) ^{2 hl} = Ei "· ω

Becomes That is, equation (7) indicates that the phase shift circuit 10C of this embodiment has a constant amplitude of the output signal equal to the amplitude of the input signal no matter how the phase between the input and output rotates. ing.

Further, the phase shift amount 01 of the output voltage Εο with respect to the input voltage Ei is obtained from the equation (6).

01 = tan " ¹ {. ² °.}-(8). From this equation (8), for example, the phase shift amount 01 at a frequency such that ω is approximately 1 / T (= 1Z (CR)) is It is almost 90 °, and only the phase can be shifted by almost 90 ° without attenuating the amplitude of the input signal.Moreover, by varying the resistance value R of the variable resistor 16, the phase shift amount 01 becomes almost 90 °. Can be changed.

FIG. 4 is a circuit diagram extracted from the configuration of the phase shift circuit 30 C at the subsequent stage shown in FIG. 1, in which an operational amplifier 32 which is a kind of differential input amplifier and an input terminal 42 are inputted. A variable resistor 36 and a capacitor 34 that shift the signal phase by a predetermined amount and input to the non-inverting input terminal of the operational amplifier 32; a resistor 38 inserted between the input terminal 42 and the inverting input terminal of the operational amplifier 32; It comprises a resistor 40 inserted between the output terminal 44 of 32 and the inverting input terminal.

In the phase shift circuit 30C having such a configuration, when a predetermined AC signal is input to the input terminal 42, the voltage VC2 appearing across the capacitor 34 is applied to the non-inverting input terminal of the operational amplifier 32.

Also, since there is no potential difference between the two inputs (inverting input terminal and non-inverting input terminal) of the operational amplifier 32 shown in FIG. 4, the potential of the inverting input terminal of the operational amplifier 32 and the connection of the variable resistor 36 and the capacitor 34 It is equal to the potential at the point. Therefore, the same voltage VR2 appears at both ends of the resistor 38 as the voltage VR2 appearing at both ends of the variable resistor 36.

Here, if the respective resistance values of the resistor 38 and the resistor 40 are equal, the same current flows through these two resistors 38 and 40, so that the voltage VR2 appears at both ends of the resistor 40. The voltage VR2 that appears at each end of these two resistors 38 and 40 is vector-wise pointing in the same direction. Considering the inverting input terminal (voltage VC2) of the operational amplifier 32 as a reference, the vector sum of the voltage VR2 across the resistor 38 is the input voltage Ei, and the voltage R2 across the resistor 40 is the sum. The output voltage Eo is the result of the subtraction.

FIG. 5 is a vector diagram showing the relationship between the input / output voltage of the subsequent phase shift circuit 30C and the voltage appearing on a capacitor or the like.

As shown in this vector diagram, the voltage VC2 appearing across the capacitor 34 and the voltage VR2 appearing across the variable resistor 36 are 90 ° out of phase with each other. Is the input voltage E i. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VC2 across the capacitor 34 and the voltage V R2 across the variable resistor 36 along the circumference of the semicircle shown in FIG. Change.

Further, as described above, the output voltage Eo is obtained by vectorically subtracting the voltage VR2 from the voltage VC2. Considering the voltage VC2 applied to the non-inverting input terminal, the input voltage Ei and the output voltage Eo differ only in the direction in which the voltage VR2 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and the phase of the input / output voltage can be represented by an isosceles triangle with the input voltage Ei and the output voltage Eo as hypotenuses and the base at twice the voltage VR2, and the amplitude of the output signal varies with the frequency. Regardless of the amplitude of the input signal, it is understood that the phase shift amount is represented by 02 shown in FIG.

Also, as is clear from FIG. 5, since the voltage VC2 and the voltage VR2 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VC2 is theoretically It changes from 0 ° to 90 ° as it changes to ∞. The shift amount 02 of the entire phase shift circuit 30C is twice that, and changes from 0 ° to 180 ° according to the frequency.

As in the case of the preceding phase shift circuit 10C, when the voltage E i is applied to the input terminal 42, the current flowing from the input terminal 42 to the output terminal 44 through the resistors 38 and 40 is represented by I and the resistor 38. Assuming that the resistance values of the resistors 40 are equal and the value is r, the voltage across each of the resistors 38 and 40 is 1 Ir.

Since there must be no potential difference between the two inputs of the operational amplifier 32 shown in FIG. 4, the voltage VC2 across the capacitor 34 applied to the non-inverting input terminal of the operational amplifier 32 and the output Between the voltage Eo

VC2 = Eo- (-Ir)

= Eo + Ir

... Eo = — I · r + VC2 — (9)

In addition, in order to prevent a potential difference between the two inputs of the operational amplifier 32, the value obtained by adding the voltage VR2 across the variable resistor 36 and the voltage Ir across the resistor 38 must be 0.

VR2 + (-I τ) = 0

.-. VR2 = I-r… (: 10) From equations (9) and (10),

Eo = -VR2 + VC2

=-(VR2-VC2)-(11).

The voltage Ei applied to the input terminal 42 is the sum of the voltages VC2 and VR2 at both ends of the capacitor 34 and the variable resistor 36.Therefore, between these voltages,

Ei = VR2 + VC2-(12) From equations (11) and (12),

Eo _VR2-VC2

~ ΕΪ VR2 + VC2

R—

_ VB2-VC2 C s

E

0 one—VR2 + VC2 ~

R +

C s

=-Ei = Ei-(13)

CRs + 1 1 + Ts

Becomes Here, C represents the capacitance of the capacitor 34, and R represents the resistance value of the variable resistor 36, and the time constant of the CR circuit composed of the capacitor 34 and the variable resistor 36 is the same as that in the case of the preceding phase shift circuit 10C. Similarly, T (= CR) was set.

Substituting s = jω in equation (13), 1-j ωΤ

Eo = Ei

1 + j ωΤ

(1 j ωΤ) ²

1 + (ωΤ) ²

1 one (ωΤ) ² — j · 2ωΤ

Ei (14)

1+ (ωΤ) ²

Becomes

Equations (13) and E (14) described above are used for equations (5) and

i

And only the sign differs from equation (6). Therefore, for the absolute value of the output voltage Εο, equation (7) can be applied as it is, and no matter how the phase between the input and output rotates, the amplitude of the output signal is It can be seen that the amplitude is constant.

Further, when the phase shift amount 02 of the output voltage Εο with respect to the input voltage Ei is obtained from Expression (14),

2ωΤ

02 = t an " ¹ {; ₁ }… ()

(T) ^!

Becomes From this equation (15), for example, the phase shift amount 02 at a frequency where ω is approximately 1ZT (= 1 / (CR)) is approximately 90 °, and only the phase can be approximately reduced without attenuating the amplitude of the input signal. Can be shifted 90 °. Moreover, by varying the resistance value R of the variable resistor 36, the frequency ω at which the phase shift amount 02 becomes substantially 90 ° can be changed.

Thus, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10C and 30C. As shown in FIGS. 3 and 5, the relative phase relationship between the input and output voltages in each of the phase shift circuits 10C and 30C is in the opposite direction, and two at a given frequency. A signal with a phase shift amount of 0 ° is output by the entire phase shift circuits 10C and 30C.

The output of the subsequent phase shift circuit 30C is fed back to the input side of the previous phase shift circuit 10C via the feedback resistor 70, and the feedback signal and the signal input via the input resistor 74 Are added, and the voltage of the added signal is applied to the input terminal (the input terminal 22 shown in FIG. 2) of the phase shift circuit 10C. To form such a feedback loop By setting the loop gain at this time to approximately 1, the phase shift amount of the signal that goes around the return loop at a certain frequency becomes 0 °, and a predetermined tuning operation is performed.

FIG. 6 is a circuit diagram in which the entire two phase shift circuits 10C and 30C having the above-described configuration are replaced with a circuit having a transfer function K1, and a feedback resistor having a resistor R0 in parallel with the circuit having the transfer function K1. 70 is connected in series with an input resistor 74 having a resistance value (nRO) n times as large as the feedback resistor 70. FIG. 7 is a circuit diagram obtained by converting the circuit shown in FIG. 6 by Miller's theorem, and the transfer function A of the whole circuit after the conversion is

Can be represented by

By the way, as is clear from equation (5), the transfer function Κ2 of the preceding phase shift circuit 10C is

1-Ts

K2 =-(17)

+ Τ s

As is clear from equation (13), the transfer function K3 of the subsequent phase shift circuit 30C is

1—T s

K3 = (18)

1 + Τ s

It is. Therefore, the overall transfer function K1 when the phase shift circuits 10C and 30C are vertically connected in two stages is

(1— Ts) ²

Kl =-

(1 + Ts) ²

^{l + (Ts) 2 - 2T} s

(19)

1 + (T s) ² + 2T s

Becomes Substituting equation (19) into equation (16) above gives

l + (Ts) ² -2Ts

A =-

(2n + l) {l + (Ts) ² } + 2Ts

1 l + (Ts) ² —2Ts

(20)

2n + l 2T s

1 + (T s) ² +

2 n + 1

Becomes

According to this equation (20), when ω = 0 (DC region), Α = —1Ζ (2η + 1) Which gives the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Further, when the respective even when ω = 1 ΖΤ tuning point of the (two each time constant of the phase shifting circuit 10C, 30 C is different to the T ,, T ₂ is, ω = 1 / VT! Τ 2 At the tuning point of ()), A = 1 and is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74. In other words, as shown in FIG. 8, even if the value of n is changed, the tuning point does not shift, and the attenuation of the tuning point does not change. Since the actual operational amplifiers 12 and 32 deviate from the ideal, even if the resistors 18 and 20 or the resistors 38 and 40 are set to the same resistance value, the signal amplitude is slightly attenuated. Therefore, to set the overall gain of the closed loop to almost 1, the value of resistor 20 is slightly larger than the value of resistor 18 or the value of resistor 40 is slightly larger than the value of resistor 38. There is a need to.

As described above, according to the tuning amplifier 1 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even when the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the above-mentioned resistance ratio n, when the tuning frequency is changed by changing the resistance value of the variable resistor 16 or 36 in each phase shift circuit 10C, 30C. This does not affect the maximum attenuation, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

In addition, the tuning amplifier 1 of this embodiment is configured by combining an operational amplifier, a capacitor, or a resistor. Since any component can be formed on a semiconductor substrate, the tuning frequency and the maximum attenuation are adjusted. It is easy to form the entire tunable amplifier 1 on a semiconductor substrate to obtain an integrated circuit.

In the tuned amplifier 1 of the first embodiment described above, the phase shift circuit 10C is arranged in the preceding stage and the phase shift circuit 30C is arranged in the subsequent stage, respectively. Since it is sufficient that the phase shift amount is 0 °, the phase shift circuit 30C may be arranged at the front stage and the phase shift circuit 10C may be arranged at the rear stage, and the tuning amplifier may be configured.

Further, the tuning amplifier 1 of the first embodiment described above performs a predetermined tuning operation when the phase shift amount becomes 0 ° by the entire two phase shift circuits 10 C and 30 C. A non-inverting circuit that does not shift the phase may be added. FIG. 9 is a circuit diagram showing a configuration of a tuning amplifier 1A in which a non-inverting circuit 50 is added to the tuning amplifier 1 shown in FIG. The non-inverting circuit 50 includes an operational amplifier 52 having an inverting input terminal grounded via a resistor 54 and a resistor 56 connected between the inverting input terminal and the output terminal. It functions as a buffer having a predetermined amplification determined by the resistance ratio of 54 and 56. The non-inverting circuit 50 having such a configuration outputs the input signal without changing its phase. By adjusting the amplification degree, the loop gain of the tuned amplifier 1A can be set to almost 1. It will be easier.

(Second embodiment)

FIG. 10 is a circuit diagram showing a configuration of a tuning amplifier according to a second embodiment of the present invention. Each of the tuning amplifiers 2 shifts the phase of an input signal by a predetermined amount. Two phase shift circuits that provide a total phase shift of 0 ° at a given frequency.10, 30 L, return resistor 70 and input resistor 74 (input resistor 74 is n times the resistance of feedback resistor 70) The signal (feedback signal) output from the subsequent phase shift circuit 30L and the signal (input signal) input to the input terminal 90 are determined by passing through each of the signals. And an adding circuit for adding at the ratio of FIG. 11 is a circuit diagram extracted from the configuration of the preceding-stage phase shift circuit 10 L shown in FIG. 10. The preceding-stage phase shift circuit 10 L is an operational amplifier (OP) which is a type of differential input amplifier. An operational amplifier) 12, a variable resistor 16 and an inductor 17, which shift the phase of the signal input to the input terminal 22 by a predetermined amount and input to the non-inverting input terminal of the operational amplifier 12, and an inversion of the input terminal 22 and the operational amplifier 12. It comprises a resistor 18 inserted between the input terminal and an output terminal 24 of the operational amplifier 12 and a resistor 20 inserted between the inverting input terminal.

In the phase shift circuit 10L having such a configuration, when a predetermined AC signal is input to the input terminal 22, the voltage V L1 appearing across the inductor 17 is applied to the non-inverting input terminal of the operational amplifier 12. You.

Since there is no potential difference between the two inputs (inverting input terminal and non-inverting input terminal) of the operational amplifier 12 shown in FIG. 11, the potential of the inverting input terminal of the operational amplifier 12 is The potential at the connection point between the resistor 16 and the intagter 17 becomes equal. Therefore, the same voltage VR3 that appears at both ends of the resistor 18 appears at both ends of the variable resistor 16.

Here, when the resistance values of the resistor 18 and the resistor 20 are equal, the same current flows through these two resistors 18 and 20, so that the voltage VR3 appears at both ends of the resistor 20. In addition, the voltage VR3 appearing at each end of these two resistors 18 and 20 has the same direction in terms of the vector. Considering the inverting input terminal of the operational amplifier 12 (voltage VL1), The output voltage Eo is the input voltage Ei obtained by vectorwise addition of the voltage VR3 across the 18 terminals and the output voltage Eo obtained by vectorwise addition of the voltage VR3 of the resistor 20.

FIG. 12 is a vector diagram showing the relationship between the input / output voltage of the phase shift circuit 10L and the voltage appearing at the intagter and the like.

As shown in this vector diagram, the voltage VL1 appearing at both ends of the intagta 17 and the voltage VR3 appearing at both ends of the variable resistor 16 are 90 ° out of phase with each other, and these are vector-wise added. Is the input voltage E i. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the voltage VL1 across the inductor 17 and the voltage VR3 across the variable resistor 16 along the circumference of the semicircle shown in FIG. Change.

The output voltage Eo is the result of the vector subtraction of the voltage VR3 from the voltage VL1. Considering the voltage VL1 applied to the non-inverting input terminal, the input voltage Ei and the output voltage Eo differ only in the direction in which the voltage VR3 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and the phase of the input / output voltage can be expressed by an isosceles triangle with the input voltage Ei and the output voltage Eo as hypotenuses and the base at twice the voltage VR3, and the amplitude of the output signal is the frequency It is understood that the amplitude is the same as the amplitude of the input signal irrespective of, and the phase shift amount is represented by 03 shown in FIG.

Also, as is clear from FIG. 12, since the voltage VL1 and the voltage VR3 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VL1 is determined by the fact that the frequency ω is 0 It changes from 90 ° to 0 ° as it changes from ∞ to ∞. Then, the phase shift amount 03 of the entire phase shift circuit 10L is twice that, and varies from 180 ° to 0 ° according to the frequency.

When the input voltage E i is applied to the input terminal 22, it is output from the input terminal 22 through the resistors 18 and 20. Assuming that the current flowing toward the force end 24 is I and the resistances of the resistors 18 and 20 are equal and the value is r, the voltage across each of the resistors 18 and 20 is 1 Ir.

By the way, 1) As described above, if there is no potential difference between the two inputs of the operational amplifier 12 shown in FIG. 11, there is no IRL, so the voltage across the inductor 17 applied to the non-inverting input terminal of the operational amplifier 12 Between VLS1 and the output voltage Eo,

VLl = Eo- (-Ir)

= Eo + Ir

Εο =-I · r + VL1 There is a relation of (21).

Also, in order for a potential difference not to occur between the two inputs of the operational amplifier 12, the value obtained by adding the voltage VR3 across the variable resistor 16 and the voltage across the resistor-Ir must be 0.

VR3 + (-Ir) = 0

.VR3 = I-r ~ (22) From equations (21) and (22),

Eo = — VR3 + VL1

=-(VR3-VLl)-(23)

Further, since the voltage Ei applied to the input terminal 22 is the sum of the voltages VL1 and VR3 across the inductor 17 and the variable resistor 16, the voltage between these voltages is:

Ei = VR3 + VLl There is a relation of (24). From equations (23) and (24),

Eo _ VR3-VL1

Ei VR3 + VL1

' ⁰ — VR3 + VL1 ^ R + Ls ¹ one T s

Ei = E (25)

, ^ L 1 + Ts

1 ⁺ R ^S Becomes Here, L represents the inductance of the inductor 17, and R represents the resistance value of the variable resistor 16, and the time constant of the LR circuit composed of the ingktor 17 and the variable resistor 16 is represented by the phase shift circuit 10 C shown in FIG. As in the case, T (= L / R) was set.

The calculation result of the equation (25) is the same as the calculation result of the equation (5) shown in the first embodiment, and the phase shift circuit 10 L of this embodiment has the structure shown in FIG. It can be seen that the input / output voltage has the same relationship as the phase circuit 10 C. Therefore, no matter how the phase between the input and output signals rotates, the amplitude of the output signal of the phase shift circuit 10L is constant. In addition, the phase shift amount 03 of the output voltage E o with respect to the input voltage is the same as 01 expressed by the above equation (8). For example, at a frequency where ω becomes approximately 1 ZT (= R / L). The phase shift is about 90 °. Moreover, by varying the resistance value R of the variable resistor 16, the frequency ω at which the phase shift amount becomes approximately 90 ° can be changed.

FIG. 13 is a circuit diagram extracted from the configuration of the subsequent phase shift circuit 30 L shown in FIG. 10. The latter phase shift circuit 30 L is an operational amplifier 32 which is a type of differential input amplifier. Between the input terminal 42 and the inverting input terminal of the operational amplifier 32, and the inductor 37 and the variable resistor 36, which shift the phase of the signal input to the input terminal 42 by a predetermined amount and input to the non-inverting input terminal of the operational amplifier 32. A resistor 38 is inserted between the output terminal 44 of the operational amplifier 32 and the inverting input terminal.

In the phase shift circuit 30L having such a configuration, when a predetermined AC signal is input to the input terminal 42, the voltage VR4 appearing at both ends of the variable resistor 36 is applied to the non-inverting input terminal of the operational amplifier 32. .

Also, since there is no potential difference between the two inputs (inverting input terminal and non-inverting input terminal) of the operational amplifier 32 shown in FIG. 13, the potential of the inverting input terminal of the operational amplifier 32, the inductor 37 and the variable resistor It becomes equal to the potential of the connection point of 36. Therefore, the same voltage VL2 appears at both ends of the resistor 38 as the voltage VL2 appearing at both ends of the inductor 37.

Here, if the respective resistance values of the resistor 38 and the resistor 40 are equal, the same current flows through these two resistors 38 and 40, so that the voltage VL2 appears at both ends of the resistor 40. The voltage VL2 appearing at both ends of these two resistors 38 and 40 is vector-wise oriented in the same direction. Considering the inverting input terminal (voltage VR4) of the operational amplifier 32, The resistance of 38 The voltage obtained by adding the voltage VL2 between both ends in vector is the input voltage Ei, and the voltage obtained by subtracting the voltage L2 between both ends of the resistor 40 in vector is the output voltage Eo.

FIG. 14 is a vector diagram showing a relationship between an input / output voltage of the subsequent phase shift circuit 30L and a voltage appearing in an inductor or the like.

As shown in this vector diagram, the voltage VR4 appearing at both ends of the variable resistor 36 and the voltage VL2 appearing at both ends of the inductor 37 are 90 ° out of phase with each other. Is the input voltage E i. Accordingly, when the amplitude of the input signal is constant and only the frequency changes, the voltage V R4 across the variable resistor 36 and the voltage V L2 across the inductor 37 along the circumference of the semicircle shown in FIG. Changes.

As described above, the output voltage Eo is obtained by vectorwise subtracting the voltage VL2 from the voltage VR4. Considering the voltage VR4 applied to the non-inverting input terminal as a reference, the input voltage Ei and the output voltage Eo differ only in the direction in which the voltage VL2 is synthesized, and their absolute values are equal. Therefore, the relationship between the magnitude and the phase of the input / output voltage can be represented by an isosceles triangle with the input voltage Ei and the output voltage Eo as hypotenuses and the base at twice the voltage VL2, and the amplitude of the output signal depends on the frequency. Regardless of the amplitude of the input signal, it can be seen that the phase shift amount is represented by 04 shown in FIG.

Also, as is clear from FIG. 14, since the voltage VK4 and the voltage VL2 intersect at right angles on the circumference, theoretically, the phase difference between the input voltage Ei and the voltage VR4 is The angle changes from 0 ° to 90 ° as the angle changes. The shift amount 04 of the entire phase shift circuit 30L is twice that, and varies from 0 ° to 180 ° according to the frequency.

As with the 10-L phase shift circuit in the preceding stage, when the voltage E i is applied to the input terminal 42, the current flowing from the input terminal 42 to the output terminal 44 through the resistors 38 and 40 is expressed as I and resistance. Assuming that the resistance values of the resistor 38 and the resistor 40 are equal and the value is r, the voltage between both ends of the resistors 38 and 40 is 1 Ir.

Since there must be no potential difference between the two inputs of the operational amplifier 32 shown in Fig. 13, the voltage between the voltage VR4 across the variable resistor 36 applied to the non-inverting input terminal of the operational amplifier 32 and the output voltage Eo In VR4 = Eo- (-IT)

= Eo + Ir

. •• Eo = VR4—There is a relationship of I · r to (26).

Also, in order for a potential difference not to occur between the two inputs of the operational amplifier 32, the value obtained by adding the voltage VL2 across the inductor 37 and the voltage Ir across the resistor 38 must be 0.

VL2 + (-Ir) = 0

. '. VL2 = I-r ~ (27). From equations (26) and (27),

Eo = VR4-VL2-(28)

The voltage Ei applied to the input terminal 42 is the sum of the voltages VR4 and VL2 at both ends of the variable resistor 36 and the integrator 37.Therefore, between these voltages,

Ei = VR4 + VL2 There is a relationship of (29). From equations (28) and (29),

Eo VR4-VL2

¥ i VR4 + VL2

. ^ VR4-VL2 _p ._ RL s…

•• ^{h0 =} VR4 + VL2 ^Ll "R + L s ^Ll

L _g

^R Ei =! ~ I ^S Ei-(30)

. ^ L-1 + Ts

1 ⁺ R ^S

Becomes Here, L represents the inductance of the Inkkuta 37, and R represents the resistance value of the variable resistor 36.The time constant of the LR circuit consisting of the inductor 37 and the variable resistor 36 is the same as in the case of the preceding phase shift circuit 10L. T (= L / R).

The calculation result of equation (30) is the same as the calculation result of equation (13) shown in the first embodiment. The phase shift circuit 30L of this embodiment is different from the phase shift circuit of the first embodiment. It can be seen that there is the same input-output voltage relationship as 30C. Therefore, the phase shift circuit 30L No matter how the phase of the force signal rotates, the amplitude of the output signal is constant.

In addition, as the phase shift amount 04 of the output voltage Eo with respect to the input voltage, 02 expressed by the above equation (15) is applied as it is. For example, the phase shift at a frequency such that ω becomes approximately 1 ZT (= RZL) The amount is almost 90 °. Moreover, by varying the resistance value R of the variable resistor 36, the frequency ω at which the phase shift amount becomes approximately 90 ° can be changed.

Thus, the phase is shifted by a predetermined amount in each of the two phase shift circuits 10L and 30L. As shown in FIGS. 12 and 14, the relative phase relationship between the input and output voltages in each of the phase shift circuits 10L and 30L is in the opposite direction, and two at a given frequency. The phase shift amount is 0 due to the entire 10 L and 30 L phase shift circuits. Is output.

The output of the subsequent phase shift circuit 30 L is fed back to the input side of the preceding phase shift circuit 10 L via the feedback resistor 70, and is input to the input signal via the input signal and the resulting signal. And the added voltage is applied to the input terminal (input terminal 22 shown in FIG. 11) of the phase shift circuit 10L. By forming such a return loop and setting the loop gain at this time to approximately 1, the phase shift amount of a signal that goes around the return loop at a certain frequency becomes 0 °, and a predetermined tuning operation is performed. Is performed.

By the way, when the tuning amplifier 2 of the second embodiment including the two phase shift circuits 10 L and 30 L described above is entirely replaced with a circuit having a transfer function K1, the case of the first embodiment Similarly, it can be represented by the circuit diagram shown in FIG. Therefore, the conversion can be represented by the circuit diagram shown in FIG. 7 by performing the conversion according to the Miller's theorem, and the transfer function A of the whole circuit after the conversion can be represented by the equation (16).

Further, as is clear from the equations (25) and (30), the transfer functions of the two phase shift circuits 10L and 30L of this embodiment are represented by the two phase shift circuits 10C of the first embodiment. , And 30 C, and the same transfer function as shown in equation (19) can be applied as it is to the overall transfer function K 1 connecting the two phase shift circuits 10 L and 30 L. Therefore, the transfer function of the entire tuned amplifier 2 according to the second embodiment can also be applied to A shown in Expression (20) as it is. Therefore, the tuned amplifier 2 of the second embodiment has the same characteristics as the tuned amplifier 1 of the first embodiment. When ω = 0 (DC region), A = —l / (2 η + 1), giving the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Further, omega = tuning point of 1Zetatau (when two phase shifting circuits 10L, respectively in a case where the time constant of 30L are different T, and T ₂ are, ω = 1 / ^ {Ύ ! Τ 2) At the tuning point), A = 1 and is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74. Even if the value of n is changed as shown in Fig. 8, the tuning point does not shift. , And the amount of attenuation at the tuning point does not change.

As described above, according to the tuning amplifier 2 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even when the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, when the tuning frequency is changed by changing the resistance value of the variable resistor 16 or 36 in each of the phase shift circuits 10L and 30L. This does not affect the maximum attenuation, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Also, the inductors 17 and 37 can be formed on a semiconductor substrate by forming a spiral-shaped conductor by a photo engraving method or the like, but by using such inductors 17 and 37, In addition, it is easy to form the entire tuned amplifier 2 together with the other components (the operational amplifier and the resistor) on a semiconductor substrate to form an integrated circuit. In particular, when the tuning amplifier 2 is formed as an integrated circuit, it is easy to increase the frequency ω (= R / L) by reducing the inductance of the ingukators 17 and 37, and to increase the tuning frequency. Are suitable.

In the tuned amplifier 2 of the second embodiment described above, the phase shift circuit 10L is arranged in the preceding stage and the phase shift circuit 30L is arranged in the subsequent stage, respectively. Since it is only necessary that the phase shifter is 0 °, the phase shift circuit 30L may be arranged in the front stage and the phase shift circuit 10L may be arranged in the subsequent stage to replace the front and rear sides, thereby forming a tuning amplifier.

In the tuning amplifier 2 of the second embodiment, the phase shift amount becomes 0 ° by the entire 30 L and the predetermined tuning operation is performed. Therefore, as shown in FIG. 15, a non-inverting circuit 50 that does not shift the phase may be added to configure the tuning amplifier 2A.

(Third embodiment)

FIG. 16 is a circuit diagram showing a configuration of a tuning amplifier according to the third embodiment. Each of the tuning amplifiers 3 shifts the phase of an input signal by a predetermined amount to obtain a total of 0 ° at a predetermined frequency. Phase shift circuits 10C and 30 L, and a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times the resistance value of the feedback resistor 70) , And a signal (return signal) output from the subsequent phase shift circuit 30 L and a signal (input signal) input to the input terminal 90 at a predetermined ratio. ing.

As described in the first and second embodiments described above, the phase is shifted by a predetermined amount by each of the two phase shift circuits 10C and 30L included in the tuning amplifier 3 of the third embodiment. As shown in FIGS. 3 and 14, the relative phase relationship between the input and output voltages in each of the phase shift circuits 10 C and 30 L is opposite, and two phase shifts are performed at a certain frequency. A signal having a phase shift amount of 0 ° is output by the entire circuit 10C and 30L.

Also, the output of the subsequent phase shift circuit 30 L is fed back to the input side of the phase shift circuit 10 C via the feedback resistor 70, and this feedback signal and the signal input via the input resistor 74 are mixed. The added signal is input to the input terminal (the input terminal 22 shown in FIG. 2) of the preceding phase shift circuit 10C. By forming such a feedback loop and setting the loop gain at this time to approximately 1, the phase shift amount of a signal that goes around the feedback loop at a certain frequency becomes 0 °, and a predetermined tuning operation is performed. Is performed. By the way, when the tuning amplifier 3 of the third embodiment including the above-described two phase shift circuits 10C and 30L is entirely replaced with a circuit having a transfer function K1, the tuning amplifier 3 of the first embodiment As in the case, it can be represented by the circuit diagram shown in FIG. Therefore, by converting according to Mira's theorem, it can be represented by the circuit diagram shown in FIG. The transfer function A of the entire circuit after conversion can be expressed by equation (16).

Further, as is apparent from Equation (30), the transfer function of the subsequent phase shift circuit 30L of this embodiment is the same as the transfer function of the subsequent phase shift circuit 30C of the first embodiment. As the overall transfer function K1 when the phase shift circuits 10C and 30L are connected, the one shown in equation (19) can be applied as it is. Therefore, the transfer function A of the tunable amplifier 3 of the third embodiment as a whole can be directly applied to A shown in the equation (20).

Therefore, the tuning amplifier 3 of the third embodiment has the same characteristics as the tuning amplifier 1 of the first embodiment. When ω = 0 (DC region), A = —1Z (2 η + 1), which gives the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Furthermore, the tuning point of ω = 1 （(If the time constants of the two phase shift circuits 10C and 30L are different from each other and T! And Τ ₂ respectively, ω = l Z ^ CT! T At the tuning point of ^), A = l, which is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74, and the tuning point is shifted even if the value of n is changed as shown in Fig. 8. And the attenuation at the tuning point does not change.

As described above, according to the tuning amplifier 3 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even if the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, the case where the tuning frequency is changed by changing the resistance value of the variable resistor 16 or 36 in each of the phase shift circuits 10C and 30L. However, the maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

In addition, as described in the second embodiment described above, the inccutor 37 is a force that can be formed on a semiconductor substrate by forming a spiral conductor by photolithography or the like. By using a simple inductor 37, it is easy to form the entire tuning amplifier 3 on a semiconductor substrate together with other components (such as an operational amplifier and a resistor) on a semiconductor substrate to form an integrated circuit.

In addition, the time constant T of the CR circuit of the preceding phase shift circuit 10C is CR, and the time constant T of the LR circuit of the subsequent phase shift circuit 30L is LZR. For example, the entire tuning amplifier 3 is formed on a semiconductor substrate In addition, when each of the variable resistors 16 and 36 is formed by an FET, it is possible to use a so-called temperature compensation, which suppresses fluctuation of a tuning frequency with respect to a temperature change of a resistance value of each variable resistor.

In the tuned amplifier 3 of this embodiment, the phase shift circuit 10C is arranged in the preceding stage, and the phase shift circuit 30L is arranged in the subsequent stage. Therefore, the phase shift circuit 30L may be arranged at the front stage and the phase shift circuit 10C may be arranged at the subsequent stage to form a tuned amplifier. Further, as shown in FIG. 9 or FIG. 15, a non-inverting circuit 50 for outputting the input signal without shifting the phase may be connected to the output side of the phase shift circuit 30L.

(Fourth embodiment)

FIG. 17 is a circuit diagram showing a configuration of a tuning amplifier according to a fourth embodiment. Each of the tuning amplifiers 4 shifts the phase of an input signal by a predetermined amount to obtain a total of 0 ° at a predetermined frequency. Two phase shift circuits 10 and 30 C, each of which has a feedback resistor 70 and an input resistor 74 (the input resistor 74 has n times the resistance value of the feedback resistor 70) A signal (feedback signal) output from the phase shift circuit 30C and a signal (input signal) input to the input terminal 90 are added at a predetermined ratio.

As described in the first and second embodiments described above, the phase is shifted by a predetermined amount by each of the two phase shift circuits 10 L and 30 C included in the tuned amplifier 4 of the fourth embodiment. You. As shown in FIGS. 12 and 5, the relative phase relationship between the input and output voltages in each of the phase shift circuits 10L and 30C is opposite, and at a certain frequency, two phase shift circuits are used. A signal with a phase shift of 0 ° is output by the entire 10 L and 30 C.

Further, the output of the subsequent phase shift circuit 30 C is fed back to the input side of the phase shift circuit 10 L via the feedback resistor 70, and this feedback signal and the signal input via the input resistor 74 are Are added, and the added signal is input to the input terminal (the input terminal 22 shown in FIG. 11) of the preceding phase shift circuit 10L. By forming such a feedback loop and setting the loop gain at this time to approximately 1, the feedback loop at a certain frequency is obtained. When the phase shift amount of the signal that goes around the loop reaches 0 °, a predetermined tuning operation is performed.

By the way, when the tuning amplifier 4 of the fourth embodiment including the two phase shift circuits 10 L and 30 C described above is replaced with a circuit having a transfer function K 1 as a whole, the tuning amplifier 4 of the first embodiment As in the case, it can be represented by the circuit diagram shown in FIG. Therefore, by performing conversion according to Mira's theorem, it can be represented by the circuit diagram shown in FIG. 7, and the transfer function A of the whole circuit after the conversion can be represented by equation (16).

Further, as is apparent from the equation (25), the transfer function of the preceding phase shift circuit 10L of the present embodiment is the same as the transfer function of the preceding phase shift circuit 10C of the first embodiment. As shown in equation (19), the entire transfer function K1 when two phase shift circuits 10L and 30C are connected can be applied as it is. Therefore, the transfer function of the entire tuned amplifier 4 of the fourth embodiment can be directly applied to A shown in Expression (20).

Therefore, the tuned amplifier 4 of the fourth embodiment has the same characteristics as the tuned amplifier 1 of the first embodiment, the tuned amplifier 3 of the third embodiment, and the like. ), Α = —1 Ζ (2 η + 1), which gives the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Furthermore, the tuning point of ω = 1 （(When the time constants of the two phase shifters 10 L and 30 C are different, and T, and Τ ₂ respectively,

In this case, A = 1 and is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74, and the tuning point does not shift even if the value of n is changed, as shown in Fig. 8, and The attenuation of the point does not change.

Thus, according to the tuning amplifier 4 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even when the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, when the tuning frequency is changed by changing the resistance value of the variable resistor 16 or 36 in each phase shift circuit 10 L and 30 C, Even so, the maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Further, as described in the second embodiment described above, the inductor 17 is By forming a spiral-shaped conductor by a method or the like, it is possible to form the conductor on a semiconductor substrate. By using such an inductor 17, it is possible to tune it with other components (operational amplifier, resistor, etc.). It is also easy to form the whole of the amplifier 4 on a semiconductor substrate to form an integrated circuit.

In addition, the time constant T of the LR circuit of the preceding phase shift circuit 10 L is L ZR, and the time constant T of the CR circuit of the subsequent phase shift circuit 30 C is CR. Since R is divided into a denominator and a numerator, for example, when the entire tuning amplifier 4 is formed on a semiconductor substrate and the variable resistors 16 and 36 are formed by FETs, the temperature of the resistance value of each variable resistor This enables so-called temperature compensation, which suppresses fluctuations of the tuning frequency with respect to changes.

In the tuned amplifier 4 of this embodiment, the phase shift circuit 10 L is arranged at the preceding stage and the phase shift circuit 30 C is arranged at the subsequent stage. Therefore, it is also possible to arrange the phase shift circuit 30C at the front stage and the phase shift circuit 10L at the rear stage to form a tuned amplifier. Further, as shown in FIG. 9 or FIG. 15, a non-inverting circuit 50 that outputs the input signal without shifting the phase may be connected to the output side of the phase shift circuit 30C.

(Fifth embodiment)

The tunable amplifier of each of the above-described embodiments is configured by combining two phase shift circuits in which the relative phase relationship between input and output signals is opposite, as shown in FIGS. 3 and 5. A tunable amplifier may be configured by combining two phase shift circuits having the same general phase relationship.

FIG. 18 is a circuit diagram showing the configuration of a tuned amplifier according to a fifth embodiment. The tuned amplifier 5 includes two phase shift circuits 10C having a configuration shown in FIG. And a phase inverting circuit 80 for further inverting the phase of the output signal, and a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times the resistance value of the feedback resistor 70). And an adder circuit that adds a signal (feedback signal) output from the phase inversion circuit 80 and a signal (input signal) input to the input terminal 90 at a predetermined ratio. The phase inversion circuit 80 is connected between an inverting input terminal via a resistor 84 and an inverting input terminal via a resistor 84 and a non-inverting input terminal is grounded. And a resistor 86 connected to the resistor 86. When an AC signal is input to the inverting input terminal of the operational amplifier 82 via the resistor 84, an inverted signal having an inverted phase is output from the output terminal of the operational amplifier 82. Is output from the output terminal 92 of the tuning amplifier 5 shown in FIG. Further, the phase inversion circuit 80 has a predetermined amplification determined by the resistance ratio of the two resistors 84 and 86.

By the way, as described in the above-described first embodiment, each of the two phase shift circuits 10C changes the phase shift amount from 180 ° to 0 as the frequency ω of the input signal changes from 0 to ∞. Up to °. For example, assuming that the time constants of the CR circuits in the two phase shift circuits 10 C are the same, and let Τ be the phase at each of the two phase shift circuits 10 C at the frequency of ω = 1 ΖΤ The shift amount is 90 °. Therefore, the phase is shifted by 180 ° by the entire two phase shift circuits 10C, and the phase is inverted by the phase inverting circuit 80 provided at the subsequent stage. A signal in which the phase shift amount becomes 0 ° in a loop is output from the phase inversion circuit 80.c The output of the phase inversion circuit 80 is fed back to the input side of the preceding phase shift circuit 10C via the feedback resistor 70. This feedback signal and the signal input via the input resistor 74 are added, and the voltage of the added signal is input to the input terminal of the preceding phase shift circuit 10C (the input terminal shown in FIG. 2). 22) is applied.

By forming such a feedback loop, at a certain frequency, the phase is shifted by 180 ° by the two phase shift circuits 10 C, and the phase is inverted by the phase inverting circuit 80, and the circuit loops around the feedback loop as a whole. The phase shift amount of the signal becomes 0 °. At this time, a predetermined tuning operation is performed by adjusting the amplification degree of the phase inversion circuit 80 and setting the loop gain of the entire tuning amplifier 5 to substantially 1.

Since the transfer function of the two phase shift circuits 10 C is expressed by Κ2 shown in Equation (17) when the time constant of the CR circuit is given, the two phase shift circuits 10 C and the phase inversion circuit 80 are cascaded. The overall transfer function K1 for the case is

Kl = K2 x K2x (-1) (1 Ts):

(1 + Ts) ²

l + (Ts) ² — 2Ts

(31) l + (Ts) ² + 2Ts

Becomes The right side of the equation (31) is equal to the calculation result shown in the equation (19) in the first embodiment. Therefore, A shown in Expression (20) can be applied as it is to the transfer function of the entire tuning amplifier 5 of the fifth embodiment.

Therefore, the tuned amplifier 5 of the fifth embodiment has the same characteristics as the tuned amplifier 1 of the first embodiment and the like. When ω = 0 (DC region), Α = —1 (2 η + 1), giving the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. In addition, the tuning point of ω = 1ΖΤ (when the time constants of the two phase shift circuits 10C are different and それぞれ, and T ₂ respectively, the tuning of ω = \ / (Τ, Τζ) ), A = 1 and is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74, and the tuning point does not shift even if the value of n is changed, as shown in Fig. 8. In addition, the amount of attenuation at the tuning point does not change.

As described above, according to the tuning amplifier 5 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even when the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, even if the tuning frequency is changed by changing the resistance value of the variable resistor 16 in the two phase shift circuits 10C, The maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without overlapping each other.

In addition, the tuning amplifier 5 of this embodiment is configured by combining an operational amplifier, a capacitor, or a resistor, and any of the components can be formed on a semiconductor substrate. Therefore, the tuning frequency and the maximum attenuation are adjusted. It is easy to form the entire tunable amplifier 5 on a semiconductor substrate to form an integrated circuit.

(Sixth embodiment)

FIG. 19 is a circuit diagram showing a configuration of a tuning amplifier according to a sixth embodiment. The amplifier 6 includes two phase shift circuits 30 C whose configuration is shown in FIG. 4, a phase inversion circuit 80 for further inverting the phase of the output signal of the subsequent phase shift circuit 30 C, a feedback resistor 70 and an input resistor 74 (The input resistor 74 has a resistance value which is n times the resistance value of the feedback resistor 70), and the signal output from the phase inversion circuit 80 (return signal) and the input terminal 90 And an adder circuit for adding a signal (input signal) input to the at a predetermined ratio.

As described in the fifth embodiment, the phase inversion circuit 80 inverts the phase of an input signal, and outputs a signal obtained by amplifying the input signal by a predetermined amplification at the same time as the phase inversion.

By the way, as described in the first embodiment described above, each of the two phase shift circuits 30C changes the phase shift amount from 0 ° to 18 as the frequency ω of the input signal changes from 0 to ∞. Changes up to 0 °. For example, assuming that the time constants of the CR circuits in the two phase shift circuits 30 C are the same, and this is Τ, at a frequency of ω = 1 位相, the phase in each of the two phase shift circuits 30 C The shift amount is 90 °. Therefore, the phase is shifted by 180 ° by the entire two phase shift circuits 30C, and the phase is inverted by the phase inverting circuit 80 provided at the subsequent stage. A signal in which the phase shift amount becomes 0 ° in one cycle is output from the phase inversion circuit 80.c The output of the phase inversion circuit 80 is fed back to the input side of the preceding phase shift circuit 30C via the feedback resistor 70. This feedback signal is added to the signal input through the input resistor 74, and the voltage of the added signal is input to the input terminal of the preceding phase shift circuit 30C (the input terminal shown in FIG. 4). Applied to terminal 42).

By forming such a return loop, at a certain frequency, the phase is shifted by 180 ° by the two phase shift circuits 30C, and the phase is inverted by the phase inversion circuit 80. The phase shift amount of the shifted signal becomes 0 °. At this time, a predetermined tuning operation is performed by adjusting the amplification degree of the phase inverting circuit 80 and setting the loop gain of the entire tuning amplifier 6 to substantially 1.

The transfer function of the two phase shift circuits 30 C is represented by Κ3 shown in equation (18) when the time constant of the CR circuit is given, so the two phase shift circuits 30 C and the phase inversion circuit 80 are cascaded. The total transfer function K1 when connected is equal to the calculation result of the above-mentioned equation (31). others Therefore, the transfer function A of the tuned amplifier 6 according to the sixth embodiment can be applied to A as shown in the expression (20).

Therefore, the tuned amplifier 6 of the sixth embodiment has the same characteristics as the tuned amplifier 1 of the first embodiment and the like. When ω = 0 (DC region), Α = — 1 / ( 2 η + 1), which gives the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Furthermore, the tuning point of ω = 1 Ζ （(when the time constants of the two phase shift circuits 30 C are different and それぞれ, and Τ ₂ respectively, ω = 1 / (7 _{At 2} ), the tuning point shifts even if the value of η is changed as shown in Fig. 8 because A = l and is independent of the resistance ratio η between the feedback resistor 70 and the input resistor 74. And the attenuation at the tuning point does not change.

As described above, according to the tuning amplifier 6 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even if the resistance ratio η between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the above-described resistance ratio η, even when the tuning frequency is changed by changing the resistance value of the variable resistor 36 in the two phase shift circuits 30C. However, this maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

In addition, the tuning amplifier 6 of this embodiment is configured by combining an operational amplifier, a capacitor, or a resistor. Since any component can be formed on a semiconductor substrate, the tuning frequency and the maximum attenuation are adjusted. It is easy to form the entire tunable amplifier 6 on a semiconductor substrate to form an integrated circuit.

(Seventh embodiment)

FIG. 20 is a circuit diagram showing a configuration of a tuned amplifier according to a seventh embodiment. The tuned amplifier 7 includes two phase shift circuits 10 L whose configuration is shown in FIG. Circuit 10 A phase inversion circuit 80 for further inverting the phase of the output signal, a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance η times the resistance of the feedback resistor 70. ), The signal output from the phase inversion circuit 80 (feedback signal) and the signal input to the input terminal 90 (input signal) are added by a predetermined divider. It is composed of

As described in the above-described second embodiment, each of the two phase shift circuits 10L changes the phase shift amount from 180 ° to 0 ° as the frequency ω of the input signal changes from 0 to ∞. . For example, assuming that the time constants of the LR circuits in the two phase shift circuits 10L are the same, and let this be Τ, the phase shift amount in each of the two phase shift circuits 10L at the frequency of ω = 1ΖΤ Becomes 90 °. Therefore, the phase is shifted by 180 ° by the entire two phase shift circuits 10L, and the phase is inverted by the phase inverting circuit 80 provided at the subsequent stage. A signal having the angle of 0 ° is output from the phase inversion circuit 80. The output of the phase inversion circuit 80 is fed back to the input side of the preceding phase shift circuit 10L via the return resistor 70, and the returned signal and the signal input via the input resistor 74 are compared with the output signal. Are added, and the voltage of the added signal is applied to the input terminal (input terminal 22 shown in FIG. 11) of the preceding phase shift circuit 10L.

By forming such a feedback loop, at a certain frequency, the phase is shifted by 180 ° by the two phase shift circuits 10L, and the phase is inverted by the phase inversion circuit 80. The phase shift 'amount becomes 0 °. At this time, a predetermined tuning operation is performed by adjusting the amplification degree of the phase inversion circuit 80 and setting the loop gain of the entire tuning amplifier 7 to substantially 1.

As described in the second embodiment, each of the two phase shift circuits 10L has the same input-output voltage relationship as the phase shift circuit 10C whose configuration is shown in FIG. The number can be represented by Κ2 shown in equation (17). Therefore, the entire transfer function when the two phase shift circuits 10L and the phase inverting circuit 80 are connected can be represented by K1 expressed by the equation (31).伝達 shown in equation (20) can be applied as it is to the transfer function of.

Therefore, the tuned amplifier 7 of the seventh embodiment has the same characteristics as the tuned amplifier 1 and the like of the first embodiment. When ω = 0 (DC region), A = −1Z (2 η + 1), giving the maximum attenuation. Also, it can be seen that the maximum attenuation is given when ω = ∞. Further, the tuning point of ω = 1ΖΤ (When the time constants of the two phase shift circuits 10L are different and each is set to Th T ₂ , ω = 1 / Γ (Τ, Τ 2) tuning point), A = 1 and is independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74, and the value of n as shown in Fig. 8 Even if is changed, the tuning point does not shift, and the attenuation of the tuning point does not change.

As described above, according to the tuning amplifier 7 of this embodiment, the tuning frequency and the gain at the time of tuning are constant even if the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, even if the tuning frequency is changed by changing the resistance value of the variable resistor 16 in the two phase shift circuits 10L. However, this maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Further, as described in the second embodiment, the inductor 17 can be formed on the semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an inductor 17, it is easy to form the entire tuned amplifier 7 on a semiconductor substrate together with the other components (the operational amplifier and the resistor) to form an integrated circuit. In particular, when the tuning amplifier 7 is formed as an integrated circuit, it is easy to increase the frequency ω (= R / L) by reducing the inductance of the inductor 17, which is suitable for increasing the tuning frequency.

(Eighth embodiment)

FIG. 21 is a circuit diagram showing a configuration of a tuned amplifier according to an eighth embodiment. The tuned amplifier 8 includes two phase shift circuits 30 L having the configuration shown in FIG. A phase inverting circuit 80 for further inverting the phase of the output signal of the circuit 30 L; a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times the resistance value of the feedback resistor 70; And an adder circuit that adds a signal (feedback signal) output from the phase inverting circuit 80 and a signal (input signal) input to the input terminal 90 at a predetermined ratio. .

By the way, in each of the two phase shift circuits 30L, the phase shift amount changes from 0 ° to 180 ° as the frequency ω of the input signal changes from 0 to ∞. For example, assuming that the time constants of the LR circuits in the two phase shift circuits 30 L are the same, In other words, at the frequency of ω = 1 ZT, the phase shift amount in each of the two phase shift circuits 30 L is 90 °. Accordingly, the phase is shifted by 180 ° by the entire two phase shift circuits 30L, and the phase is inverted by the phase inverting circuit 80 provided at the subsequent stage. A signal having a phase shift amount of 0 ° is output from the phase inversion circuit 80. The output of the phase inverting circuit 80 is returned to the input side of the preceding phase shift circuit 30L via the feedback resistor 70, and the returned signal and the signal input via the input resistor 74 are separated. The voltage of the added signal is applied to the input terminal (input terminal 42 shown in FIG. 13) of the phase shift circuit 30 L in the preceding stage.

By forming such a feedback loop, at a certain frequency, the phase is shifted by 180 ° by the two phase shift circuits 30L, and the phase is inverted by the phase inversion circuit 80. The phase shift of the signal becomes 0 °. At this time, a predetermined tuning operation is performed by adjusting the amplification degree of the phase inversion circuit 80 and setting the loop gain of the entire tuning amplifier 8 to substantially 1.

As described in the second embodiment, each of the two phase shift circuits 30L has the same input-output voltage relationship as the phase shift circuit 30C whose configuration is shown in FIG. Can be represented by K3 shown in equation (18). Since this transfer function K3 differs from the transfer function K2 shown in equation (17) only in sign, the overall transfer function when two phase shift circuits 30 L and a phase inversion circuit 80 are connected is expressed by equation (31) Can be expressed by K1 shown in the above, and the transfer function of the entire tuned amplifier 8 of the eighth embodiment can also be applied to A shown in the equation (20) as it is.

Therefore, the tuned amplifier 8 of the eighth embodiment has the same characteristics as the tuned amplifier 1 of the first embodiment and the like. When ω = 0 (DC region), A = −1 Z ( 2 η + 1), which gives the maximum attenuation. Also, it can be seen that the maximum attenuation is given when = ∞. Further, the tuning point of ω = 1 （(when the time constants of the two phase shift circuits 30 L are different and それぞれ, and T ₂ respectively, ω =

It is 1 and independent of the resistance ratio n between the feedback resistor 70 and the input resistor 74.As shown in Fig. 8, even if the value of n is changed, the tuning point does not shift and the attenuation of the tuning point is It does not change.

Thus, according to the tuned amplifier 8 of this embodiment, the feedback resistance 70 and the input resistance 74 Even if the resistance ratio n is changed, the tuning frequency and the gain at the time of tuning are constant, and only the maximum attenuation can be changed. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, even when the tuning frequency is changed by changing the resistance value of the variable resistor 36 in the two phase shift circuits 30L. However, this maximum attenuation is not affected, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Further, as described in the second embodiment, the inductor 37 can be formed on the semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an inductor 37, it is easy to form the entire tuning amplifier 8 together with the other components (the operational amplifier and the resistor) on a semiconductor substrate to form an integrated circuit. In particular, when the tuned amplifier 8 is formed as an integrated circuit, it is easy to increase the frequency ω (= R / L) by reducing the inductance of the integrator 37, which is suitable for increasing the tuned frequency.

(Ninth embodiment)

FIG. 22 is a circuit diagram showing the configuration of a tuned amplifier according to the ninth embodiment. The tuned amplifier 9A includes phase shift circuits 10C and 10L having the configuration shown in FIG. 2 or FIG. And a phase inverting circuit 80 for further inverting the phase of the output signal of the subsequent phase shift circuit 10 L, a feedback resistor 70 and an input resistor 74 (the input resistor 74 has a resistance value n times the resistance value of the feedback resistor 70). ), The signal output from the phase inversion circuit 80 (return signal) and the signal input to the input terminal 90 (input signal) are added at a predetermined ratio. And a circuit.

As described in the first embodiment or the second embodiment, each of the phase shift circuits 10 C and 10 L shifts the phase as the frequency ω of the input signal changes from 0 to ∞. The angle changes from 180 ° to 0 °. For example, assuming that the time constant of the CR circuit in the phase shift circuit 10C is the same as the time constant of the LR circuit in the phase shift circuit 10L, and that this is Τ, the phase shift at the frequency of ω = 1ΖΤ The phase shift amount in each of the circuits 10C and 10L is 90 °. Accordingly, the phase is shifted by 180 ° by the entire two phase shift circuits 10C and 10L, and the phase shifter provided at the subsequent stage is provided. Since the phase is inverted by the inverting circuit 80, a signal whose phase shifts to 0 ° as a whole is output from the phase inverting circuit 80. The output of the phase inverting circuit 80 is returned to the input side of the preceding phase shift circuit 10 C via the feedback resistor 70, and the feedback signal and the signal input via the input resistor 74 Are added, and the voltage of the added signal is applied to the input terminal (the input terminal 22 shown in FIG. 2) of the preceding phase shift circuit 10C.

By forming such a return loop, at a certain frequency, the phase is shifted by 180 ° by the two phase shift circuits 10 C and 10 L, and further, the phase is inverted by the phase inversion circuit 80, and the return as a whole is performed. The phase shift of the signal that goes around the loop is 0 °. At this time, by adjusting the amplification degree of the phase inversion circuit 80 and setting the loop gain of the entire tuning amplifier 9A to substantially 1, the same tuning operation as the tuning amplifier of each of the above-described embodiments is performed. .

That is, according to the tuning amplifier 9A of this embodiment, the tuning frequency and the gain at the time of tuning are constant even if the resistance ratio n between the return resistor 70 and the input resistor 74 is changed, and only the maximum attenuation is changed. Can be. Conversely, since the maximum attenuation is determined by the above-described resistance ratio n, the case where the tuning frequency is changed by changing the resistance value of the variable resistor 16 in the two phase shift circuits 10C and 10L is considered. This does not affect the maximum attenuation, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Further, as described in the second embodiment, the inductor 17 has a force that can be formed on a semiconductor substrate by forming a spiral conductor by photolithography or the like. By using the inductor 17, it is easy to form the entire tuned amplifier 9A on a semiconductor substrate together with the other components (the operational amplifier, the resistor, etc.) to form an integrated circuit.

The time constant T of the CR circuit of the preceding phase shift circuit 10C is CR, and the time constant T of the LR circuit of the subsequent phase shift circuit 10L is LZR. For example, when the tuning amplifier 9A is formed entirely on a semiconductor substrate and two variable resistors 16 are formed by FETs, the tuning of the resistance value of each variable resistor against temperature change Suppress frequency fluctuations, so-called temperature compensation It works.

In the tunable amplifier 9A of the ninth embodiment described above, the phase shift circuit 10C is arranged in the preceding stage and the phase shift circuit 10L is arranged in the subsequent stage. Since the shift amount only needs to be 180 °, it is possible to construct a tuned amplifier by exchanging the order before and after these by arranging the phase shift circuit 10L in the front stage and the phase shift circuit 10C in the subsequent stage. Good.

(10th embodiment)

FIG. 23 is a circuit diagram showing the configuration of the tuned amplifier of the tenth embodiment. The tuned amplifier 9B includes a phase shift circuit 30L having the configuration shown in FIG. 13 or FIG. 30 C and a subsequent phase shift circuit A phase inverting circuit 80 for further inverting the phase of the output signal of the 30 C, a feedback resistor 70 and an input resistor 74 (the input resistor 74 is n times the resistance of the feedback resistor 70. The signal (return signal) output from the phase inversion circuit 80 and the signal (input signal) input to the input terminal 90 are added by a predetermined splitter And an adder circuit.

As described in the above-described second embodiment or the first embodiment, each of the phase shift circuits 30 L and 30 C has a phase shift amount as the frequency ω of the input signal changes from 0 to ∞. It varies from 0 ° to 180 °. For example, assuming that the time constant of the LR circuit in the phase shift circuit 30L is the same as the time constant of the CR circuit in the phase shift circuit 30C, and this is denoted by Τ, the phase shift at the frequency of ω = 1 ZT The phase shift amount in each of the circuits 30L and 30C is 90 °. Therefore, the phase is shifted by 180 ° by the entire two phase shift circuits 30 L and 30 C, and the phase is inverted by the phase inversion circuit 80 provided at the subsequent stage. Is completed, and a signal in which the phase shift amount becomes 0 ° is output from the phase inversion circuit 80. The output of the phase inversion circuit 80 is fed back to the input side of the preceding phase shift circuit 30 L via the feedback resistor 70, and the signal fed back and the signal input via the input resistor 74 are The voltage of the added signal is applied to the input terminal (the input terminal 42 shown in FIG. 13) of the preceding phase shift circuit 30L.

By forming such a feedback loop, two phases shift at t at a certain frequency. The phase is shifted by 180 ° by the circuits 30L and 30C, and the phase is inverted by the phase inverting circuit 80, so that the phase shift amount of the signal that goes through the return loop as a whole becomes 0 °. At this time, by adjusting the amplification degree of the phase inversion circuit 80 and setting the loop gain of the entire tuning amplifier 9B to substantially 1, the same tuning operation as that of the tuning amplifier of each embodiment described above is performed. .

That is, according to the tuning amplifier 9B of this embodiment, the tuning frequency and the gain at the time of tuning are constant even if the resistance ratio n between the feedback resistor 70 and the input resistor 74 is changed, and only the maximum attenuation can be changed. it can. Conversely, since the maximum attenuation is determined by the resistance ratio n described above, when the tuning frequency is changed by changing the resistance value of the variable resistor 36 in the two phase shift circuits 30L and 30C. This does not affect the maximum attenuation, and the tuning frequency, the gain at the tuning frequency, and the maximum attenuation can be adjusted without interfering with each other.

Further, as described in the second embodiment, the inductor 37 can be formed on the semiconductor substrate by forming a spiral conductor by a photolithography method or the like. By using such an integrator 37, it is easy to form an integrated circuit by forming the entire tuning amplifier 9B on a semiconductor substrate together with other components (such as an operational amplifier and a resistor).

The time constant T of the LR circuit of the preceding phase shift circuit 30L is L ZR, and the time constant T of the CR circuit of the subsequent phase shift circuit 30C is CR. For example, if the entire tuning amplifier 9B is formed on a semiconductor substrate and two variable resistors 36 are formed by FETs, the variation of the tuning frequency with respect to the temperature change of the resistance value of each variable resistor In other words, the so-called temperature compensation can be suppressed.

In the tuned amplifier 9B of the tenth embodiment described above, the phase shift circuit 30L is arranged in the preceding stage and the phase shift circuit 30C is arranged in the subsequent stage, respectively. It is sufficient that the phase shift amount of the phase shifter is 180 °, so that the phase shift circuit 30C is arranged at the front stage and the phase shift circuit 30L is arranged at the subsequent stage, and the tuned amplifier is constituted. It may be. (Other modes for carrying out the invention)

By the way, the tuning amplifier of each of the above-described embodiments is configured by two phase shift circuits or two phase shift circuits and a non-inverting circuit or a phase inverting circuit. Thus, a predetermined tuning operation is performed by setting the total phase shift amount to 0 ° at a predetermined frequency. Therefore, focusing only on the amount of phase shift, the order in which a plurality of circuits are connected has a certain degree of freedom, and the connection order can be determined as necessary.

FIG. 24 is a diagram showing a connection state when a tuned amplifier is configured by combining two phase shift circuits and a non-inverting circuit. In these figures, the feedback impedance element 70a and the input impedance element 74a are for adding the output signal and the input signal of each tuned amplifier at a predetermined ratio, and most commonly, As shown in FIG. 1 and the like, a feedback resistor 70 is used as a feedback impedance element 70a, and an input resistor 74 is used as an input impedance element 74a.

However, the return impedance element 70a and the input impedance element 74a only need to be able to be added without changing the phase relationship of the signals input to the respective elements. The return impedance element 70a and the input impedance element 74a may both be formed by an inductor together with the capacitor 74a. Alternatively, each impedance element may be formed by combining resistors, capacitors, or inductors so that the ratio of the real number and the imaginary number of the impedance can be simultaneously adjusted.

FIG. 24 (A) shows a configuration in which a non-inverting circuit 50 is arranged at a stage subsequent to two phase shift circuits. This configuration corresponds to the tuning amplifier 1A shown in FIG. 9 and the tuning amplifier 2A shown in FIG. As described above, when the non-inverting circuit 50 is arranged at the subsequent stage, a large output current can be taken out by providing the non-inverting circuit 50 with an output buffer function.

FIG. 24 (B) shows a configuration in which a non-inverting circuit 50 is arranged between two phase shift circuits. In this way, when the non-inverting circuit 50 is disposed in the middle, mutual interference between the preceding phase shift circuit and the subsequent phase shift circuit can be completely prevented. FIG. 24 (C) shows a configuration in which a non-inverting circuit 50 is arranged in front of two phase shift circuits. As described above, when the non-inverting circuit 50 is arranged in the preceding stage, the influence of the return impedance element 70a and the input impedance element 74a on the preceding-stage phase shift circuit can be minimized.

Similarly, FIG. 25 is a diagram showing a connection state when a tuned amplifier is configured by combining two phase shift circuits and a phase inversion circuit. As described with reference to FIG. 24, the return impedance element 70a and the input impedance element 74a are for adding the output signal and the input signal of each tuned amplifier on a predetermined split base. Most commonly, the feedback resistor 70 is used as the feedback impedance element 70a, and the input resistor 74 is used as the input impedance element 74a, as shown in FIG. However, the return impedance element 70a and the input impedance element 74a only need to be able to be added without changing the phase relationship of the signals input to the respective elements, and therefore may be formed by a capacitor or the like.

FIG. 25 (A) shows a configuration in which a phase inversion circuit 80 is arranged at a stage subsequent to two phase shift circuits. This configuration corresponds to the tuning amplifier 5 shown in FIG. 18, the tuning amplifier 6 shown in FIG. 19, and the like. As described above, when the phase inversion circuit 80 is arranged at the subsequent stage, a large output current can be taken out by providing the phase inversion circuit 80 with an output buffer function.

FIG. 25 (B) shows a configuration in which a phase inversion circuit 80 is arranged between two phase shift circuits. As described above, when the phase inversion circuit 80 is arranged in the middle, mutual interference between the two phase shift circuits can be completely prevented.

FIG. 25 (C) shows a configuration in which a phase inversion circuit 80 is arranged in front of two phase shift circuits. As described above, when the phase inverting circuit 80 is arranged in the preceding stage, the influence of the feedback impedance element 70a and the input impedance element 74a on the preceding phase shifting circuit can be minimized.

Further, the phase shift circuit shown in each of the above embodiments includes the variable resistor 16 or 36. Specifically, these variable resistors 16 and 36 can be realized by using a junction type or MOS type FET.

Figure 26 shows two types of phase shift circuits with CR circuits. FIG. 10 is a circuit diagram showing the configuration of a phase shift circuit in the case where the anti-resistance 16 or 36 is replaced with an FET. FIG. 26 (A) shows a configuration in which the variable resistor 16 is replaced with an FET in the phase shift circuit 10C. FIG. 26 (B) shows a configuration in which the variable resistor 36 is replaced with an FET in the phase shift circuit 30C.

Similarly, FIG. 27 is a circuit diagram showing a configuration of a phase shift circuit in which the variable resistor 16 or 36 in the two types of phase shift circuits 10 L or 30 L having the LR circuit is replaced with FET. FIG. 27 (A) shows a configuration in which the variable resistor 16 is replaced by an FET in the phase shift circuit 10L. FIG. 27 (B) shows a configuration in which the variable resistor 36 is replaced with an FET in the phase shift circuit 30L.

In this way, if the channel formed between the source and drain of the FET is used as a resistor and used instead of the variable resistor 16 or 36, the gate voltage is variably controlled and this channel resistance is controlled within a certain range. The phase shift amount in each phase shift circuit can be changed arbitrarily. Therefore, since the frequency at which the phase shift amount of the signal that makes a round in each tuning amplifier becomes 0 ° can be changed, the tuning frequency of the tuning amplifier can be arbitrarily changed.

In each phase shift circuit shown in Fig. 26 or Fig. 27, the variable resistor is composed of one FET, that is, a p-channel or n-channel FET, but the channel FET and the n-channel FET are connected in parallel. They may be connected to form one variable resistor. To change the resistance value, the magnitude of the gate voltage may be changed. In this way, by combining two FETs to form a variable resistor, the non-linear region of the FET can be improved, and the distortion of the tuned output can be reduced.

Further, the phase shift circuit 10C or 30C shown in each of the above-described embodiments is a phase shifter that changes the resistance value of 36, where t is a variable resistor 16 connected in series with 34, Although the overall tuning frequency is changed by changing the amount, the capacitors 14 and 34 may be formed by variable capacitance elements, and the overall tuning frequency may be changed by changing the capacitance. .

FIG. 28 shows the configuration of the phase shift circuit in the case where the capacitor 14 or 34 in the phase shift circuit 10C or 30C shown in each embodiment is replaced with a variable capacitance diode. FIG. FIG. 28 (A) shows a configuration in which the variable resistor 16 is replaced with a fixed resistor and the capacitor 14 is replaced with a variable capacitance diode in one of the phase shift circuits 10 C shown in FIG. 1 and the like. . FIG. 28 (B) shows a configuration in which the variable resistor 36 is replaced with a fixed resistor and the capacitor 34 is replaced with a variable capacitance diode in the other phase shift circuit 30 C shown in FIG. 1 and the like. .

In FIGS. 28 (A) and (B), the capacitor connected in series with the variable capacitance diode applies its direct current when a reverse bias voltage is applied between the anode and cathode of the variable capacitance diode. The impedance is extremely small at the operating frequency, that is, has a large capacitance. Also, since the potentials at both ends of the capacitor shown in FIGS. 28 (A) and (B) are constant when the DC component is viewed, a reverse noise voltage larger than the amplitude of the AC component is applied to the anode and cathode. By applying the voltage between them, each variable capacitance diode can function as a variable capacitance capacitor.

In this way, the capacitor 14 or 34 is composed of a variable capacitance diode, and the magnitude of the reverse bias voltage applied between the anode and the cathode is variably controlled so that the capacitance of the variable capacitance diode is within a certain range. The phase shift amount in each phase shift circuit can be changed arbitrarily. Therefore, it is possible to change the frequency at which the phase shift amount of the looping signal becomes 0 ° in each tuning amplifier, and arbitrarily change the tuning frequency of the tuning amplifier.

By the way, in FIGS. 28 (A) and (B) described above, a variable capacitance diode was used as the variable capacitance element, but the source and the drain were connected to a fixed potential in a DC manner and a variable voltage was applied to the gate. FETs may be used. As described above, since the potentials at both ends of the variable capacitance diodes shown in FIGS. 28 (A) and (B) are fixed in a DC manner, these variable capacitance diodes need only be replaced with the FETs described above. By changing the voltage applied to the gate, the gate capacitance, that is, the capacitance of the FET can be changed.

Although only the capacitance of the variable capacitance diode is varied in FIGS. 28 (A) and (B) described above, the resistance of the variable resistor 16 or 36 may be varied simultaneously. FIG. (C) shows a variable resistor 16 in one phase shift circuit 10 C shown in FIG. In this example, a capacitor 14 is replaced with a variable capacitance diode. FIG. 28 (D) shows a configuration in which a variable resistor 36 is used and the capacitor 34 is replaced with a variable capacitance diode in the other phase shift circuit 30C shown in FIG. 1 and the like. Of course, in these, the variable capacitance diode may be replaced with a variable gate capacitance FET.

It goes without saying that the variable resistors shown in FIGS. 28 (C) and (D) can be formed by utilizing the channel resistance of FET as shown in FIG. In particular, if a p-channel FET and an n-channel FET are connected in parallel to form a single variable resistor, the nonlinear region of the FET can be improved, thus reducing distortion of the tuning signal. be able to.

As described above, even when the phase shift circuit is configured by combining the variable resistor and the variable capacitance element, each phase shift is performed by arbitrarily changing the resistance value of the variable resistance and the capacitance of the variable capacitance element within a certain range. The amount of phase shift in the circuit can be changed. Therefore, the frequency at which the phase shift amount of the signal circulating in each tuning amplifier becomes 0 ° can be changed, and the tuning frequency of the tuning amplifier can be arbitrarily changed. Similarly, the phase shift circuit 10L or 30L shown in each of the above-described embodiments changes the phase shift amount by changing the resistance value of the variable resistor 16 or 36 connected in series with the inductor 17 or 37. Although the whole tuning frequency is changed by the above, the whole tuning frequency may be changed by changing the inductance by forming the intagters 17 and 37 by a variable ingotter.

FIG. 29 is a diagram showing a configuration of a phase shift circuit when the inductor 17 or 37 in the phase shift circuit 10L or 30L shown in each embodiment is replaced with a variable inductor.

FIG. 29 (A) shows a configuration in which the variable resistor 16 is replaced by a fixed resistor and the inductor 17 is replaced by a variable ingector 17a in one of the phase shift circuits 10L shown in FIG. 10 and the like. It is shown. FIG. 29 (B) shows a configuration in which the variable resistor 36 is replaced with a fixed resistor and the ingktor 37 is replaced with a variable inductor 37a in the other phase shift circuit 30L shown in FIG. 10 and the like. ing.

Thus, the inductor 17 or 37 is placed on the variable inductor 17a or 37a. In other words, the phase shift amount in each phase shift circuit can be changed by arbitrarily changing the inductance of the phase shift circuits. Therefore, it is possible to change the frequency at which the phase shift amount of the signal circulating in each tuning amplifier becomes 0 °, and arbitrarily change the tuning frequency.

By the way, in FIGS. 29 (A) and (B) described above, only the inductance of the variable integrator 17a or 37a is changed, but the resistance of the variable resistor 16 or 36 may be changed at the same time. . FIG. 29 (C) shows a configuration in which the variable resistor 16 is used and the inductor 17 is replaced with a variable inductor 17a in the phase shift circuit 10L shown in FIG. 10 and the like. FIG. 29 (D) shows a configuration in which the variable resistor 36 is used and the inductor 37 is replaced by a variable inductor 37a in the phase shift circuit 30L shown in FIG. 10 and the like.

It goes without saying that the variable resistors shown in FIGS. 29 (C) and (D) can be formed using the channel resistance of FET as shown in FIG. In particular, if a p-channel FET and an n-channel FET are connected in parallel to form a single variable resistor, the nonlinear region of the FET can be improved, thus reducing distortion of the tuning signal. be able to.

As described above, even when a phase shift circuit is configured by combining a variable resistor and a variable inductor, the phase shift circuit is configured by arbitrarily changing the resistance value of the variable resistor and the inductance of the variable inductor within a certain range. The amount of phase shift in the circuit can be changed. Therefore, the frequency at which the phase shift amount of the signal circulating in each tuning amplifier becomes 0 ° can be changed, and the tuning frequency can be arbitrarily changed.

In addition, as described above, in addition to the case of using a variable inqector, a variable resistor or a variable capacitance element, t, is prepared by preparing a plurality of resistors / capacitors or inductors having different element constants and switching the switches. One or a plurality of these elements may be selected. In this case, the element constant can be switched discontinuously depending on the number of elements connected by switch switching and the connection method (series connection, parallel connection, or a combination thereof).

For example, instead of a variable resistor, prepare a plurality of resistors in the series of 2 n, such as R, 2 R, 4 R,…, and select one or an arbitrary number to connect in series. By continuing, switching of the resistance value at equal intervals can be easily realized with a smaller number of elements. Similarly, instead of the capacity, prepare a plurality of capacitors of the series of 2 n, such as C, 2 C, 4 C,…, and select one or an arbitrary number of capacitors. By connecting in parallel, switching of the capacitance at equal intervals can be easily realized with a smaller number of elements. Therefore, the tuning amplifier of each embodiment is applied to a circuit having a plurality of tuning frequencies, for example, an AM radio, and is suitable for an application in which one station is selected and received from a plurality of broadcasting stations.

FIG. 30 is a diagram showing a specific example of the variable inductor 17a shown in FIG. 29, and schematically shows a planar structure formed on a semiconductor substrate. The structure of the variable inductor 17a shown in FIG. 30 can be applied to the variable inductor 37a as it is.

The variable inductor 17a shown in FIG. 30 includes a spiral-shaped inductor conductor 112 formed on a semiconductor substrate 110, a control conductor 114 formed so as to go around the outer periphery thereof, and these inductor conductors 112 and An insulating magnetic body 118 is formed so as to cover both the control conductors 114.

The above-described control conductor 114 is connected to a variable voltage power supply 116 for applying a variable bias voltage to both ends of the control conductor 114, and variably controls the DC bias voltage applied by the variable voltage power supply 116. The bias current flowing through the control conductor 114 can be changed.

The semiconductor substrate 110 is, for example, an n-type silicon substrate (n-Si substrate) or another semiconductor material (for example, an amorphous material such as germanium or amorphous silicon). Further, the inductor conductor 112 is formed of a metal thin film such as aluminum or gold, or a semiconductor material such as polysilicon in a spiral shape.

Note that, in addition to the variable inductor 17a, other components of the tuning amplifier shown in FIG. 10 and the like are formed on the semiconductor substrate 110 shown in FIG.

FIG. 31 is a diagram showing the shapes of the inductor conductor 112 and the control conductor 114 of the variable inductor 17a shown in FIG. 30 in more detail.

As shown in FIG. 31, the inductor conductor 112 located on the inner peripheral side is formed in a spiral shape having a predetermined number of turns (for example, about 4 turns), and two ends are provided at both ends. The child electrodes 122 and 124 are connected. Similarly, the control conductor 114 located on the outer peripheral side is formed in a spiral shape having a predetermined number of turns (for example, about two turns), and two control electrodes 126 and 128 are connected to both ends.

FIG. 32 is an enlarged cross-sectional view taken along the line AA of FIG. 31 and shows a cross section of an insulating magnetic body 118 including an inductor conductor 112 and a control conductor 114.

As shown in FIG. 32, an inductor conductor 112 and a control conductor 114 are formed on the surface of a semiconductor substrate 110 via an insulating magnetic film 118a, and an insulating magnetic film is further formed on the surface thereof. 118b has been formed. The two magnetic films 118a and 118b form the insulating magnetic material 118 shown in FIG.

For example, various magnetic films such as gamma-fluorite-barium-ferrite can be used as the magnetic films 118a and 118b. Various materials and methods for forming these magnetic films are conceivable. For example, a method of forming a magnetic film by vacuum-depositing Fe 0 or the like, and other methods such as molecular beam epitaxy (MBE) , A chemical vapor deposition method (CVD method), a method of forming a magnetic film using a sputtering method, and the like. Note that the insulating film 130 is formed of a non-magnetic material, and covers the space between each of the inductor conductor 112 and the control conductor 114. By eliminating the magnetic films 118a and 118b between the orbital portions in this way, the leakage magnetic flux generated between the orbital portions can be minimized, so that the magnetic flux generated by the inductor conductor 112 is reduced. The variable inductor 17a having a large inductance can be effectively used to realize the variable inductor 17a.

Thus, in the variable ingktor 17a shown in FIG. 30, etc., the insulating magnetic material Π8 (magnetic film 118a, 118b) is formed so as to cover the inductor conductor 112 and the control conductor 114. By variably controlling the DC bias current flowing through the control conductor 114, the saturation magnetization characteristics of the inductor conductor 112 having the above-described insulating magnetic body 118 as a magnetic path change, and the inductance of the inductor conductor 112 is changed. Changes.

Accordingly, the inductance itself of the inductor conductor 112 can be directly changed, and the inductor conductor 112 can be formed on the semiconductor substrate 110 using a thin film forming technique or a semiconductor manufacturing technique, thereby facilitating the manufacturing. Further, since other components of the tuning amplifier can be formed on the semiconductor substrate 110, the tuning of each embodiment It is suitable when the whole amplifier is integrally formed by integration.

Note that the variable inductor 17a shown in FIG. 30 and the like is configured to alternately circulate the ink conductor 112 and the control conductor 114, as shown in FIG. 33 or FIG. And the control conductor 114 may be overlapped. In any case, the saturation magnetization characteristics of the insulating magnetic material 118 can be changed by changing the DC bias current flowing through the control conductor 114, and the inductance of the inductor conductor 112 can be changed within a certain range. Can be changed.

In addition, the variable inctor 17a shown in FIG. 30 and the like has been described by taking as an example the case where the inductor conductor 112 and the like are formed on the semiconductor substrate 110, but the variable inctor 17a is provided on various insulating or conductive substrates such as ceramics. It may be formed.

Further, although an insulating material is used as the magnetic films 118a and 118b, a conductive material such as metal powder (MP) may be used. However, if such a conductive magnetic film is used in place of the above-mentioned insulating magnetic film 118a or the like, each orbital portion of the inductor conductor 112 or the like is short-circuited and does not function as an inductor conductor. It is necessary to electrically insulate the inductor conductor from the conductive magnetic film. As the insulating method, there are a method of forming an insulating oxide film by oxidizing the ink conductor 112 and the like, and a method of forming a silicon oxide film or a nitride film by a chemical vapor method or the like.

In particular, conductive materials such as metal powder have a higher magnetic permeability than insulating materials such as gamma-light, and therefore have the advantage of securing a large inductance.

In addition, in the variable ingktor 17a shown in FIG. 30, etc., both the inductor conductor 112 and the control conductor 114 are entirely covered with the insulating magnetic material 118. May be formed.

As shown in FIG. 35, a variable inctor partially formed with an insulating magnetic body 118, the insulating magnetic body 118 is formed so as to cover a part of the inductor conductor 112 and a part of the control conductor 114. A magnetic path is formed by the insulating magnetic material 118 formed partially. In this way, when the insulating magnetic material (or conductive magnetic material) 118 serving as a magnetic path is partially formed, the magnetic path is narrowed, so that the inductor conductor 112 and the inductor conductor 112 are formed. And the magnetic flux generated by the control conductor 114 is likely to be saturated. Therefore, even when a small bias current flows through the control conductor 114, the magnetic flux is saturated, and the inductance of the inductor conductor 112 can be changed by variably controlling the bias current with a small t. For this reason, the circuit configuration of the control system can be simplified. The variable inductor 17a shown in FIG. 30 and the like is formed by winding an inductor conductor 112 and a control conductor 114 concentrically, and these conductors are formed adjacent to the surface of the semiconductor substrate 110. Then, magnetic coupling between them may be performed by a magnetic path formed of an insulating or conductive magnetic material.

As shown schematically in the plan view of FIG. 36, a variable inductor 17b in which an inductor conductor and a control conductor are formed adjacent to each other, a spiral inductor formed on a semiconductor substrate 110 is formed. A conductor 112a, a spiral-shaped control conductor 114a formed at a position adjacent to the inductor conductor 112a, and an insulation formed to cover each spiral center of the inductor conductor 112a and the control conductor 114a. Magnetic material (or conductive magnetic material) 119.

As with the variable inductor 17a shown in FIG. 30 and the like, a variable voltage power supply 116 is connected to both ends of the control conductor 114a to apply a variable bias voltage. By controlling the applied bias voltage variably, a predetermined bias current flowing through the control conductor 114a can be changed. FIG. 37 is a diagram showing the shapes of the inductor conductor 112a and the control conductor 114a of the variable inductor 17b shown in FIG. 36 in more detail.

As shown in FIG. 37, the ingkuta conductor 112a is formed in a spiral shape having a predetermined number of turns (for example, about 4 turns), and two terminal electrodes 122 and 124 are connected to both ends thereof. Similarly, the control conductor 114a disposed adjacent to the inductor conductor 112a is formed in a spiral shape having a predetermined number of turns (for example, about two turns), and has two control electrodes 126 at both ends. 128 are connected.

FIG. 38 is an enlarged cross-sectional view taken along the line BB of FIG. 37, and shows a cross section of the insulating magnetic body 119 including the ink conductor 112a and the control conductor 114a.

As shown in FIG. 38, an insulating magnetic film 119a and an insulating non-magnetic film 132 are formed on the surface of the semiconductor substrate 110, and the inductor conductors 112a and 112a are formed on the surface thereof. Control conductors 114a are respectively formed. An insulating magnetic film 119b is further formed on the surface so as to penetrate through the center of each of the ink conductor 112a and the control conductor 114a. The two magnetic films 119a and 119b form an annular magnetic body 119 serving as a common magnetic path between the inductor conductor 112a and the control conductor 114a.

The insulating non-magnetic film 132 shown in FIG. 38 has substantially the same thickness as the magnetic film 119a, and further has an inductor conductor 112a and a control conductor 114a on their surfaces. Are formed at substantially the same height. Therefore, when a slight step may be formed between the inductor conductor 112a and the control conductor 114a, the inductor conductor 112a and the control conductor 114a are directly formed on the semiconductor substrate 110 without forming the nonmagnetic film 132. A portion of 114a may be formed.

Also, an insulating film 130 is formed between the orbiting conductor 112a and the control conductor 114a on the surface of the magnetic film 119a between the respective orbiting portions, similarly to the variable inductor 17a shown in FIG. 30 and the like. I have. By partially filling the insulating film 130 and eliminating the magnetic films 119a and 119b between the orbital portions, it is possible to minimize the leakage magnetic flux generated between the orbital portions. Therefore, most of the magnetic flux generated by the inductor conductor 112a crosses the control conductor 114a through the magnetic films 119a and 119b. Therefore, by reducing the leakage magnetic flux, a large inductance can be obtained by effectively utilizing the magnetic flux generated by the inductor conductor 112a. As described above, the above-described variable ingector 17b is formed with the annular insulating magnetic material 119 (magnetic film 119a, 119b) so as to pass through the center of each spiral of the inctor conductor 112a and the control conductor 114a. ing. Therefore, by variably controlling the DC bias current flowing through the control conductor 114a, the saturation magnetization characteristics of the inductor conductor 112a having the magnetic body 119 as a magnetic path change, and the Inductance also changes.

When the tuning amplifier 1 or the like of each of the above embodiments is formed on a semiconductor substrate, it is not possible to set a very large capacitance as the capacitor 14 or 34 in the phase shift circuits 10C and 30C. Therefore, the small capacitance of the capacitor actually formed on the semiconductor substrate can be apparently increased by devising the circuit. For example, it is convenient to set the time constant T to a large value to lower the tuning frequency.

FIG. 39 is a view showing a modified example in which the capacitors 14 or 34 used in the phase shift circuits 10C and 30C shown in FIG. It functions as a capacitance conversion circuit that makes the capacitance of the capacitor formed on it look larger. The entire circuit shown in FIG. 39 corresponds to the capacitor 14 or 34 included in the phase shift circuit 10C or 30C.

The capacitance conversion circuit 14a shown in FIG. 39 includes a capacitor 210 having a predetermined capacitance CO, two operational amplifiers 212 and 214, and four resistors 216, 218, 220, and 222. ing.

In the first-stage operational amplifier 212, a resistor 218 (this resistance is R18) is connected between the output terminal and the inverting input terminal, and the inverting input terminal is connected to the resistor 216 (this resistance value). Is assumed to be R16).

Between the voltage E1 applied to the non-inverting input terminal of the operational amplifier 212 of the first stage and the voltage E2 appearing at the output terminal,

D 1 O

E2 = (1+) -Ei There is a relation of (32). The first-stage operational amplifier 212 mainly functions as a buffer that performs impedance conversion, and may have a gain of 1. When the gain is 1, R18 is set to R16-0, that is, R16 is set to infinity (the resistor 216 can be removed), or R18 can be set to 0Ω (the connection can be made directly).

The second-stage operational amplifier 214 has a resistor 222 connected between the output terminal and the inverting input terminal (the resistance value of R is denoted by R22), and the inverting input terminal and the output of the operational amplifier 212 described above. A resistor 220 (this resistance is R20) is connected between this terminal and the non-inverting input terminal.

Assuming that the voltage appearing at the output terminal of the second-stage operational amplifier 214 is E3, the voltage between this voltage E3 and the voltage E2 appearing at the output terminal of the first-stage operational amplifier 212 is

^{^{^{E3 = - fi E2 "· (}}} 33) There is a relationship. Thus, the second-stage operational amplifier 214 functions as an inverting amplifier, and the first-stage operational amplifier 212 is used to set its input side to high impedance.

As described above, the capacitor 210 having a predetermined capacitance is provided between the non-inverting input terminal of the first-stage operational amplifier 212 and the output terminal of the second-stage operational amplifier 214. It is connected.

In the capacitance conversion circuit 14a shown in FIG. 39, assuming that the transfer function of the entire circuit except for the capacitor 210 is K4, the capacitance conversion circuit 14a can be represented by a circuit diagram shown in FIG. Fig. 41 is a circuit diagram obtained by converting this using Mira's theorem.

Using the impedance Z0 shown in FIG. 40 to represent the impedance Z1 shown in FIG. 41,

Zl =--(34)

丄一

Becomes Here, in the case of the capacitance conversion circuit 14a shown in FIG. 39, the impedance Z0 = 1Z (jωΟΟ) is substituted into the equation (34) to obtain j wCO

Zl =

1-K4

•• (35) j ω {(1-K4) CO}

C = (1-K4) CO (36)

Becomes Equation (36) indicates that the capacitance CO of the capacitor 210 in the capacitance conversion circuit 14a has apparently increased by (1−K4) times.

Therefore, when the gain K4 is negative, (1-1 K4) is always larger than 1, so the capacitance CO can be changed to the larger one.

By the way, the gain of the amplifier in the capacitance conversion circuit 14a shown in FIG. 39, that is, the gain K4 of the amplifier composed of the operational amplifiers 212 and 214 as a whole, is given by the following equations (32) and (33). Becomes Substituting this equation (37) into equation (36) gives c = ^{{1+ (1 +} ϋ) ϋ ^{} co} · '· ⁽³⁸⁾ . Therefore, the apparent capacitance C between the two terminals 224, 226 can be increased by setting the resistance values of the four resistors 216, 218, 220, 222 to predetermined values.

When the gain of the first-stage operational amplifier 212 is 1, that is, when R16 is set to infinity (the resistor 216 is removed) as described above, or when R18 is set to 0Ω and R18ZR16 = 0 Then, the above equation (38) is simplified to c ⁼ (1 + ϋ) ⁰ to ⁽³⁹⁾ .

FIG. 42 is a diagram showing a configuration of a capacitance conversion circuit 14b in which the resistor 216 connected to the inverting input terminal of the first operational amplifier 212 shown in FIG. 39 is removed. In this case, since the capacitance C appearing between the terminals 224 and 226 is represented by the equation (39), the CO can be changed to the larger one only by changing the ratio of R22 and R20. As described above, the capacitance conversion circuit 14a or 14b described above has a resistance ratio R22ZR20 between the resistor 220 and the resistor 222, and the resistance ratio R18ZR16 between the resistor 216 and the resistor 218 is changed. However, the capacitance C 0 of the capacitor 210 actually formed on the semiconductor substrate can be converted to an apparently larger one. Therefore, a capacitor 210 having a small capacitance CO is formed on a semiconductor substrate in a field base on which the entire tuning amplifier 1 shown in FIG. 1 and the like is formed on a semiconductor substrate. The circuit shown in Fig. 39 or Fig. 42 can be converted to a large capacitance C, which is convenient for integration.

In addition, at least one of the resistors 216, 218, 220, and 222 (at least one of the resistors 220 and 222 in the case of the capacitance conversion circuit 14b shown in FIG. 42) is formed by a variable resistor. , Specifically, mounting type or MOS type FET or p-channel F By connecting the ET and the n-channel FET in parallel to form a variable resistor, it is possible to easily form a capacitance conversion circuit having a variable capacitance. Therefore, by using this capacitance conversion circuit instead of the variable capacitance diode shown in FIG. 28, the amount of phase shift can be arbitrarily changed within a certain range. For this reason, the frequency at which the phase shift amount of the looping signal becomes 0 ° in the tuning amplifier can be changed, and the tuning frequency of the tuning amplifier of each embodiment can be arbitrarily changed.

Since the first-stage operational amplifier 212 is used as a buffer for increasing the input impedance as described above, the operational amplifier 212 may be replaced with an emitter follower circuit or a source follower circuit.

FIG. 43 is a circuit diagram showing a configuration of a capacitance conversion circuit 14c using an emitter-follower circuit in the first stage. The capacitance conversion circuit 14c has the structure shown in FIG. It has a configuration in which the operational amplifier 212 and the two resistors 216 and 218 at the stage are replaced by an emitter follower circuit 228 composed of a bipolar transistor and a resistor.

FIG. 44 is a circuit diagram showing a configuration of a capacitance conversion circuit 14 d using a source follower circuit in the first stage. The capacitance conversion circuit 14 d is a single stage shown in FIG. It has a configuration in which the op-amp 212 and the two resistors 216 and 218 are replaced with a source-hollow circuit 230 including a FET and a resistor.

Further, each of the above-mentioned capacitance conversion circuits 14 c and 14 d changes the apparent capacitance between the terminals 224 and 226 by changing the resistance ratio of the resistors 220 and 222 connected to the operational amplifier 214. The point that C can be changed arbitrarily is the same as the capacitance conversion circuit 14a shown in FIG. 39 and the like. Therefore, by replacing at least one of the resistors 220 and 222 with a junction-type or MOS-type FET or a variable resistor in which a p-channel FET and an n-channel FET are connected in parallel, a variable capacitance capacitance conversion circuit By using this capacitance conversion circuit instead of the variable capacitance diode shown in FIG. 28, the phase shift amount can be arbitrarily changed within a certain range. For this reason, the frequency at which the phase shift amount of the looping signal becomes 0 ° in each tuning amplifier can be changed, and the tuning frequency of the tuning amplifier of each embodiment can be arbitrarily changed. By the way, in FIGS. 39 to 44 described above, by combining an amplifier having a predetermined gain and a capacitor, the apparent capacitance is actually larger than the capacitance of the capacitor element. However, it is also possible to use an inductor instead of a capacitor to increase the inductance of the inductor.

That is, as described above, when the impedance Z1 shown in FIG. 41 is represented using the impedance Z0 shown in FIG. 40, the equation (34) is obtained. Here, in the case of the inductor having the inductance L0, the impedance Z0 = j wLO, and this is substituted into the equation (34) to obtain

j wLO

Zl =

1-K4

^{= j} ^ T¾4- ⁽⁰⁾

Becomes Equation (41) shows that the inductance of the inductor element actually increased by 1Z (1-K4) times, and when the gain K4 was set between 0 and 1, the apparent It can be seen that the inductance increases.

FIG. 45 is a diagram showing a modified example in which the inductors 17 or 37 used in the phase shift circuits 10L and 30L shown in FIG. It functions as an inductance conversion circuit that makes the inductance of the inguta element (inductor conductor) formed on the surface look large. The entire circuit shown in FIG. 45 corresponds to the inductor 17 or 37 included in the phase shift circuits 10L and 30L.

The inductance conversion circuit 17c shown in FIG. 45 includes an inductor 260 having a predetermined inductance L0, two operational amplifiers 262 and 264, and two resistors 266 and 268.

The first stage operational amplifier 262 is a non-inverting amplifier having a gain of 1 and an output terminal connected to the inverting input terminal, and mainly functions as a buffer for performing impedance conversion. Similarly, the output terminal of the second-stage operational amplifier 264 is connected to the inverting input terminal, and functions as a non-inverting amplifier having a gain of 1. Further, a voltage dividing circuit composed of resistors 266 and 268 is inserted between these two non-inverting amplifiers.

Thus, by inserting the voltage dividing circuit between the two, the gain of the whole amplifier including the two non-inverting amplifiers can be freely set between zero and one.

In the inductance conversion circuit 17c shown in FIG. 45, assuming that the transfer function of the entire circuit (amplifier) except for the inductor 260 is K4, the gain K4 is a voltage dividing circuit composed of the resistors 266 and 268. It is determined by the voltage division ratio of

Κ4 = ~ ^{R 6S} ... (42)

R66 + R68 ^K

Becomes By substituting this gain Κ4 into Eq. (41) and calculating the apparent inductance L,

L0

L =

+ R68

R66 + R68

= _{{1 +} || _} . _L. -(43) Therefore, by increasing the resistance ratio R68ZR66 resistor 266 and 268, _c for example it is possible to increase the Indakutansu L apparent between the two terminals 254, 256, in the case of R68 = R66 is (43) From the equation, the inductance L can be made twice as large as L 0.

As described above, the inductance conversion circuit 17c described above changes the voltage division ratio of the voltage division circuit inserted between the two non-inverting amplifiers to reduce the inductance L0 of the inductor 260 actually connected. It can be increased in appearance. Therefore, when forming the entirety of the tuned amplifier 2 shown in FIG. 10 on a semiconductor substrate, for example, an inductor 260 having a small inductance L 0 is formed on the semiconductor substrate by a spiral conductor or the like. In this case, the inductance can be converted to a large inductance L by the inductance conversion circuit shown in FIG. 45, which is convenient for integration. In particular, if a large inductance can be secured in this way, The tuning frequency of the tuning amplifier 2 and the like shown in FIG. 10 is relatively low (<, it is easy to lower to the frequency domain. In addition, by integrating, the mounting area of the entire tuning amplifier can be reduced. As a result, material costs can be reduced.

In addition to the case where the voltage dividing ratio of the voltage dividing circuit by the resistors 266 and 268 is fixed, at least one of these two resistors 266 and 268 is formed by a variable resistor, specifically, a junction type or a MOS type. This voltage division ratio may be continuously changed by forming a variable resistor by connecting the same FET or a ρ-channel FET and an n-channel FET in parallel. In this case, the gain of the entire amplifier constituted by the operational amplifiers 262 and 264 shown in FIG. 45 changes, and the inductance L between the terminals 254 and 256 also changes continuously. Therefore, by using the inductance conversion circuit 17c instead of the variable inductor 17a or 37a shown in FIG. 29, the phase shift amount in each phase shift circuit can be arbitrarily set within a certain range. Can be changed. Therefore, it is possible to change the frequency at which the phase shift amount of the looping signal becomes 0 ° in the tuning amplifier, and arbitrarily change the tuning frequency of the tuning amplifier.

In the inductance conversion circuit 17c shown in FIG. 45, since the gain of the whole amplifier including the two operational amplifiers 262 and 264 is set to 1 or less, the whole is replaced with an emitter follower circuit or a source follower circuit. It may be.

FIG. 46 is a diagram showing a configuration of an inductance conversion circuit in which the entire amplifier including the operational amplifiers 262 and 264 is replaced by an emitter-follower circuit. The inductance conversion circuit 17d shown in FIG. 46 (A) is composed of a bipolar transistor 278 in which two resistors 274 and 276 are connected to an emitter, a voltage dividing point by these two resistors 274 and 276, and a transistor. It comprises an inductor 260 connected between the base of the capacitor 278 and a capacitor 280 for blocking DC current. The impedance of the capacitor 280 inserted at one end of the inductor 260 is extremely small at the operating frequency, that is, set to a large capacitance so as not to affect the frequency characteristics.

The gain of the emitter-follower circuit described above is mainly determined by the resistance ratio of the two resistors 274 and 276, and the gain is always less than 1. Therefore, as can be seen from equation (41), the inductor 260 actually The inductance L0 possessed can be increased apparently. In addition, only one emitter follower circuit is used, and the circuit configuration is It can be simplified and the maximum operating frequency can be set higher.

FIG. 46 (B) is a diagram showing a modified example thereof, and is different in that the two resistors 274 and 276 in FIG. 46 (A) are replaced by variable resistors 282. By using the variable resistor 282 in this manner, the gain can be arbitrarily and continuously changed, and the apparent inductance L can also be arbitrarily and continuously changed. By using the conductance conversion circuit 17e instead of the variable inctor 17a or the like shown in FIG. 29, the phase shift amount in each phase shift circuit can be arbitrarily changed within a certain range. Therefore, it is possible to change the frequency at which the phase shift amount of the looping signal becomes 0 ° in the tuning amplifier, and it is possible to arbitrarily change the tuning frequency of the tuning amplifier.

Note that the inductance conversion circuit 17e shown in FIG. 46 (B) replaces the two resistors 274 and 276 in FIG. 46 (A) with one variable resistor 282. At least one of 274 and 276 may be constituted by a variable resistor. FIG. 47 is a diagram in which each of the inductance conversion circuits 17 d and 17 e shown in FIGS. 46 (A) and (B) is realized by a source follower circuit, and the bipolar transistor 278 is replaced by FET284. It is a thing. FIG. 47 (A) corresponds to FIG. 46 (A), and FIG. 47 (B) corresponds to FIG. 46 (B).

FIG. 48 is a diagram showing a modification of the inductance conversion circuit 17c shown in FIG. The inductance conversion circuit 17f shown in FIG. 48 includes an npn-type bipolar transistor 286 and a resistor 290 connected to its emitter, a pnp-type bipolar transistor 288 and a resistor 292 connected to its emitter, Ingotta 260 having L 0.

A first emitter follower circuit is formed by the one transistor 286 and the resistor 290 described above, and a second emitter follower circuit is formed by the other transistor 288 and the resistor 292, which are cascaded. Since the npn-type transistor 286 and the pnp-type transistor 288 are used, the base potential of the transistor 286, which is one end of the inductor 260, and the emitter potential of the transistor 288 should be set to be almost the same. This eliminates the need for a DC blocking capacitor.

Note that various modifications are possible in each of the embodiments described above. For example, in each of the tuned amplifiers shown in FIG. 1 and the like, a feedback resistor 70 having a fixed resistance value is used as a feedback impedance element, and an input resistor 74 having a fixed resistance value is used as an input impedance element. At least one of the resistors may be constituted by a variable resistor so that the maximum attenuation can be arbitrarily changed. In this case, it goes without saying that the variable resistor can be formed by using the channel resistance of the FET as shown in FIG. In particular, when a p-channel FET and an n-channel FET are connected in parallel to form a single variable resistor, the nonlinear region of the FET can be improved, thus reducing distortion of the tuning signal. be able to.

Similarly, when the return impedance element and the input impedance element are capacitors, at least one of them may be constituted by a variable capacitance diode and a variable gate capacitance FET so that the maximum attenuation can be arbitrarily changed. .

Also, the tuning amplifier 1 and the like in each of the above-described embodiments include two phase shift circuits. When the tuning frequency is varied, the CR circuit or the LR circuit included in both phase shift circuits is used. In addition to changing the element constant of at least one of the resistor and the capacitor or the inductor constituting the resistor, the resistor and the capacitor or the inductor of the inductor constituting the CR circuit or the LR circuit included in one of the phase shift circuits are changed. It can be changed. Alternatively, the variable resistors 16, 36 and the like in each of the phase shift circuits shown in FIG. 1 and the like may be replaced with resistors having a fixed resistance value to form a tuning amplifier having a fixed tuning frequency.

Also, in each of the above-described embodiments, a highly stable circuit can be formed by configuring the phase shift circuits 10C, 10L, 30C, and 30L using the operational amplifier. Since the offset voltage and the voltage gain are not required to be so high when used in a proper way, a differential input amplifier with a specified amplification should be used instead of the operational amplifier in each phase shift circuit. You may.

FIG. 49 is a circuit diagram in which components necessary for the operation of the phase shift circuit of each embodiment are extracted from the configuration of the operational amplifier, and the whole operates as a differential input amplifier having a predetermined amplification degree. The differential input amplifier shown in FIG. 49 has a differential input stage 100 composed of FETs, a constant current circuit 102 for supplying a constant current to the differential input stage 100, and a predetermined bias voltage applied to the constant current circuit 102. Connected to the differential input stage 100 and the bias circuit 104 And an output amplifier 106. As shown in FIG. 49, the configuration of the differential input amplifier can be simplified and a wider band can be achieved by omitting the multistage amplifier circuit for gaining the voltage gain included in the actual operational amplifier. In this way, by simplifying the circuit, the upper limit of the operating frequency can be increased, and accordingly, the upper limit of the operating frequency of the tuned amplifier 1 and the like configured using the differential input amplifier is increased accordingly. Can be higher. Industrial applicability

As is clear from the description based on the best mode for carrying out the present invention, according to the tuned amplifier of the present invention, the constituent elements can be formed by an integrated circuit manufacturing method. The whole amplifier can be formed in small form as an integrated circuit on a semiconductor wafer, and can be manufactured at low cost by mass production.

In particular, the channel between the source and drain of the FET is used as a variable resistor that constitutes the CR circuit or LR circuit of each phase shift circuit, and the control voltage applied to the gate of this FET is changed to change the channel resistance. With such a configuration, it is possible to avoid the effect of the inductance of the wiring to which the control voltage is applied divided by the capacitance, and it is possible to obtain a tuned amplifier having ideal characteristics substantially as designed.

In the tuning amplifier of the present invention, the maximum attenuation is determined by the resistance ratio between the input impedance element and the feedback impedance element, and the tuning frequency is determined by the time constant of the CR circuit or LR circuit in each phase shift circuit. The amount and tuning frequency and gain at the tuning frequency can be set without interfering with each other.

Also, when the capacitor forming the CR circuit in the phase shift circuit is formed by a capacitance conversion circuit, or the inductor forming the LR circuit in the phase shift circuit is formed by an inductance conversion circuit, the capacitance inductance becomes smaller. Can be easily increased, so that the tuning frequency can be reduced and the mounting area of the entire tuning amplifier can be reduced.

Furthermore, in a tuning amplifier using LC resonance, since the tuning frequency ω is 1 ZLC, if the capacitance C or the inductance L is changed to adjust the tuning frequency, the tuning frequency becomes the square root of the change. Changes in proportion to According to the tuning amplifier of the present invention, it is possible to change the resistance in proportion to the resistance value of the resistors included in the two phase shift circuits, and it is possible to greatly adjust the tuning frequency.

Claims

The scope of the claims

1. an input impedance element having an input signal input to one end thereof; and a feedback impedance element having a return signal input to one end thereof; and an addition circuit for adding the input signal and the return signal. ,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the first resistor, and a series circuit including a third resistor and a capacitor connected to the other end of the first resistor, and a connection portion of the third resistor and the capacitor. Two phase shifting circuits connected to the non-inverting input terminal of the differential input amplifier;

The two phase-shift circuits are cascaded, and the signal added by the adder circuit is input to the preceding phase-shift circuit of the two cascade-connected two phase-shift circuits. A tuned amplifier, wherein a signal output from a phase shift circuit is input to one end of the feedback impedance element as the feedback signal, and an output of one of the two phase shift circuits is taken out as a tuned signal.

2. The tuned amplifier according to claim 1, wherein a connection method of a third resistor and a capacitor constituting the series circuit is reversed in the two phase shift circuits.

3. The tuned amplifier according to claim 1, wherein the differential input amplifier is an operational amplifier.

4. Each of the input impedance element and the feedback impedance element is a resistor. At least one of the resistors is formed by a variable resistor, and the maximum is obtained by changing the resistance ratio of the input impedance element and the feedback impedance element. The tuning according to claim 1, wherein the amount of attenuation is changed.

5. The variable resistance is formed by connecting a p-channel type FET and an n-channel type FET in parallel, and changing the magnitude of a gate voltage to change the channel resistance. A tuned amplifier according to claim 1.

6. The third resistor included in at least one of the two phase shift circuits is a variable resistor 2. The tuning amplifier according to claim 1, wherein the tuning frequency is changed by changing a resistance value of the variable resistor.

7. The variable resistor is formed by connecting a p-channel FET and an n-channel FET in parallel, and the tuning frequency is changed by changing the gate resistance by changing the gate voltage of each FET. The same as described in claim 6

8. The tuning according to claim 1, wherein the capacitor included in at least one of the two phase shift circuits is formed by a variable capacitance element, and a tuning frequency is changed by changing the capacitance. amplifier.

9. The capacitor included in at least one of the two phase shift circuits is a capacitance conversion circuit including an amplifier having a negative gain, and a capacitor element connected in parallel between the input and output of the amplifier. The tuned amplifier according to claim 1, wherein the tuned amplifier is formed by:

10. An input impedance element that receives an input signal at one end and a return impedance element that receives a return signal at one end, and adds the input signal and the return signal. An addition circuit;

A cascade connection of each of the two phase shift circuits and the non-inverting circuit, and a signal added by the addition circuit to a first-stage circuit of the plurality of cascade-connected circuits. And inputting a signal output from a circuit at the last stage to one end of the feedback impedance element as the feedback signal, and extracting an output from any of the plurality of circuits as a tuning signal. Tuning amplifier.

1 1. How to connect the third resistor and capacitor that constitute the series circuit The tuned amplifier according to claim 10, wherein the two phase shift circuits are reversed.

12. The tuned amplifier according to claim 10, wherein the differential human amplifier is an operational amplifier.

1 3. Each of the input impedance element and the feedback impedance element is a resistor, and at least one of these resistors is formed by a variable resistor, and a resistance ratio of the input impedance element and the feedback impedance element is changed. The tunable amplifier according to claim 10, wherein the maximum attenuation is changed by:

1 4. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and the tuning frequency is changed by changing the resistance value of the variable resistor. A tuned amplifier according to 0.

1 5. An input circuit including an input impedance element to which an input signal is input to one end, and a feedback impedance element to which a feedback signal is input to one end, and an adding circuit for adding the input signal and the feedback signal; ,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the other end of the first resistor, and a series circuit including a third resistor and an ingector connected to the other end of the first resistor. Two phase shifters connected to the non-inverting input terminal of the differential input amplifier,

16. The tunable amplifier according to claim 15, wherein the connection of the third resistor and the intagter constituting the series circuit is reversed in the two phase shift circuits.

17. The tuned amplifier according to claim 15, wherein the differential input amplifier is an operational amplifier.

1 8. Each of the input impedance element and the return impedance element is a resistor. At least one of these resistors is formed by a variable resistor, and the resistance ratio of the input impedance element and the return impedance element is changed. Thereby, the maximum attenuation is changed, and the tuning according to claim 15 is characterized in that:

1 9. The variable resistor is formed by connecting a channel-type F Ε Τ and an η-channel-type F Ε 、 in parallel, and changing the magnitude of the gate voltage to change the channel resistance. A tuned amplifier according to claim 18.

20. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. 6. The tuning amplifier according to 5.

2 1. The variable resistor is formed by connecting a ρ-channel FET and an η-channel FET in parallel, and the tuning frequency is changed by changing the channel resistance by changing the gate voltage of each FET. 20. The tuned amplifier according to claim 20, wherein:

22. The tuning amplifier according to claim 15, wherein a tuning frequency is changed by changing an inductance of the inductor included in at least one of the two phase shift circuits.

2 3. The aforementioned intagta is formed on a semiconductor substrate, has two spirally-shaped electrodes magnetically coupled to each other via a magnetic material, and has a magnitude of a DC bias current flowing through one of the electrodes. 23. The tunable amplifier according to claim 22, wherein the inductance is changed by changing the inductance.

2 4. An inductance that includes the inductor included in at least one of the two phase shift circuits, an amplifier having a gain set between 0 and 1, and an inductor element connected in parallel between the input and output of the amplifier. 16. The tuning amplifier according to claim 15, wherein the tuning amplifier is formed by a conversion circuit.

2 5. When the input signal is input to one end and the feedback signal is A feedback impedance element input to one end, an adding circuit for adding the input signal and the feedback signal,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the other end of the first resistor, and a series circuit including a third resistor and an ingector connected to the other end of the first resistor. Two phase shifting circuits connected to the non-inverting input terminal of the differential input amplifier;

A signal obtained by cascading each of the two phase shift circuits and the non-inverting circuit, and adding the first circuit of the plurality of cascade-connected circuits by the addition circuit. And inputting a signal output from a circuit at the last stage to one end of the feedback impedance element as the feedback signal, and extracting an output from any of the plurality of circuits as a tuning signal. Tuning amplifier.

26. The tuned amplifier according to claim 25, wherein the connection of the third resistor and the inductor constituting the series circuit is reversed in the two phase shift circuits.

27. The tuning amplifier according to claim 25, wherein the differential input amplifier is an operational amplifier.

2 8. Each of the input impedance element and the feedback impedance element is a resistor, and at least one of these resistors is formed by a variable resistor, and a resistance ratio of the input impedance element and the feedback impedance element is changed. The maximum attenuation is changed by the following method.

2 9. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. 6. The tuning amplifier according to 5.

30. An input impedance element that receives an input signal at one end, and a feedback impedance element that receives a feedback signal at one end. An adding circuit for adding the feedback signal,

Wherein the first and second phase shift circuits are vertically connected, and added to the preceding phase shift circuit of the two cascade-connected two phase shift circuits by the addition circuit. And a signal output from a subsequent phase shift circuit is input to one end of the feedback impedance element as the return signal, and an output of one of the first and second phase shift circuits is output. As a tuning signal.

3 1. The method of connecting the reactance element comprising the capacitor or the inductor constituting the series circuit and the third resistor in the two phase shift circuits is reversed. A tuned amplifier according to 0.

32. The tuning amplifier according to claim 30, wherein the differential input amplifier is an operational amplifier.

3 3. Each of the input impedance element and the return impedance element is a resistor, and at least one of these resistors is formed by a variable resistor, and a resistance ratio of the input impedance element and the feedback impedance element is changed. 31. The tuning tea§ according to claim 30, wherein the maximum attenuation is changed by:

3 4. The third resistor included in at least one of the two phase shift circuits is a variable resistor. 30. The tuning amplifier according to claim 30, wherein the tuning frequency is changed by changing a resistance value of the variable resistor.

3 5. An addition circuit that includes an input impedance element to which an input signal is input to one end and a return impedance element to which a feedback signal is input to one end, and adds the input signal and the feedback signal. When,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit including a third resistor and an inductor connected to the other end of the first resistor, and a connection part of the third resistor and the inductor. A second phase shift circuit connected to the non-inverting input terminal of the differential input amplifier;

The first and second phase shift circuits and the non-inverting circuit are vertically connected, and the adder circuit adds the first stage circuit of the plurality of cascade-connected circuits to the first circuit. And inputting the signal output from the last-stage circuit as the feedback signal to one end of the feedback impedance element, and extracting the output of one of the plurality of circuits as a tuning signal. Characteristic tuning amplification

3. The method of connecting the reactance element comprising the capacitor or the inductor constituting the series circuit and the third resistor in the two phase shift circuits in the opposite manner. 6. The tuning amplifier according to 5.

3 7. The tuning amplifier according to claim 35, wherein the differential input amplifier is an operational amplifier.

3 8. Each of the input impedance element and the feedback impedance element is a resistor, at least one of these resistors is formed by a variable resistor, and the resistance ratio of the input impedance element and the return impedance element is changed. As a result, the maximum attenuation is changed, as defined in claim 35.

3 9. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. 6. The tuning amplifier according to 5.

40. An addition circuit that includes an input impedance element to which an input signal is input to one end, and a feedback impedance element to which a feedback signal is input to one end, and adds the input signal and the feedback signal. ,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit including a third resistor and a capacitor connected to the other end of the first resistor, and a connection portion of the third resistor and the capacitor. Two phase shifting circuits connected to the non-inverting input terminal of the differential input amplifier;

Wherein each of the two phase shift circuits and the phase inversion circuit is cascaded, and the first circuit of the plurality of cascade-connected circuits is added by the addition circuit. Receiving a signal, inputting a signal output from a circuit at the last stage to the one end of the feedback impedance element as the feedback signal, and extracting an output of any of the plurality of circuits as a tuning signal. Tuned amplifier.

41. The tunable amplifier according to claim 40, wherein a connection of the third resistor and the capacitor constituting the series circuit is the same in the two phase shift circuits.

42. The tuning amplifier according to claim 40, wherein the differential input amplifier is an operational amplifier.

4 3. Each of the input impedance element and the feedback impedance element Wherein at least one of these resistors is formed by a variable resistor, and a maximum attenuation is changed by changing a resistance ratio of the input impedance element and the feedback impedance element. Same as described in range 40

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4. The variable resistance is formed by connecting a ρ-channel type FET and an η-channel type FET in parallel, and changing the magnitude of the gate voltage to change the channel resistance. 43. The tuning amplifier according to item 3.

4 5. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. A tuned amplifier according to 0.

4 6. The variable resistor is formed by connecting a ρ channel type FET and an η channel type FET in parallel, and the tuning frequency is changed by changing the gate voltage of each FET and changing the channel resistance. The tunable amplifier according to claim 45, wherein:

47. The capacitor included in at least one of the two phase shift circuits is formed by a variable capacitance element, and a tuning frequency is changed by changing the capacitance. Tuning amplifier.

4 8. A capacitance conversion circuit comprising an amplifier having a negative value of gain and a capacitor element connected in parallel between the input and output of the amplifier, wherein the capacitor included in at least one of the two phase shift circuits is provided. The tuning amplifier according to claim 40, wherein the tuning amplifier is formed by:

4 9. An addition circuit that includes an input impedance element to which an input signal is input to one end and a feedback impedance element to which a feedback signal is input to one end, and that adds the input signal and the feedback signal. ,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier And a series circuit including a third resistor and an inductor connected to the other end of the first resistor, and a connection portion between the third resistor and the inductor. Two connected to the non-inverting input terminal of the differential input amplifier A phase shift circuit;

Wherein each of the two phase shift circuits and the phase inversion circuit is cascaded, and the first circuit of the plurality of vertically connected circuits is added by the addition circuit. A signal output from the last stage circuit is input to one end of the return impedance element as the return signal, and the output of any of the plurality of circuits is extracted as a tuning signal. A tuned amplifier characterized.

50. The tuned amplifier according to claim 49, wherein a connection method of the third resistor and the inductor constituting the series circuit is the same in the two phase shift circuits.

5 1. The tuning amplifier according to claim 49, wherein the differential input amplifier is an operational amplifier.

5 2. Each of the input impedance element and the feedback impedance element is a resistor, and at least one of these resistors is formed by a variable resistor, and a resistance ratio of the input impedance element and the feedback impedance element is changed. 49. The tuning apparatus according to claim 49, wherein the maximum attenuation is changed by:

5. The variable resistor is formed by connecting a p-channel FET and an n-channel FET in parallel, and changing the magnitude of a gate voltage to change a channel resistance. 52. The tuning amplifier according to 2.

5 4. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. 10. The tuned amplifier according to 9.

5 5. The variable resistor is formed by connecting a P-channel FET and an n-channel FET in parallel, and the tuning frequency is changed by changing the gate voltage of each FET and changing the channel resistance. The tunable amplifier according to claim 54, wherein:

5 6. The tuning frequency is changed by changing the inductance of the inductor included in at least one of the two phase shift circuits. 49. The tuning amplifier according to item 9.

5 7. The intagta is formed on a semiconductor substrate and has two spiral electrodes that are magnetically coupled to each other via a magnetic material. The magnitude of the DC bias current flowing through one of the electrodes is The tuning amplifier according to claim 56, wherein the inductance of the other electrode is changed by changing the length.

5 8. The intagter included in at least one of the two phase shift circuits is constituted by an amplifier having a gain set between 0 and 1, and an inductor element connected in parallel between the input and output of the amplifier. The tunable amplifier according to claim 49, wherein the tuned amplifier is formed by a conductance conversion circuit.

5 9. An input impedance element for inputting an input signal to one end, and a feedback impedance element for inputting a feedback signal to one end, an adding circuit for adding the input signal and the feedback signal, ,

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input through the first resistor; and an inverting input terminal and an output terminal of the differential input amplifier. A second resistor connected between the first resistor and a series circuit composed of a third resistor and a capacitor connected to the other end of the first resistor; and a connection part of the third resistor and the capacitor. A first phase shift circuit connected to a non-inverting input terminal of the differential input amplifier;

One end of a first resistor is connected to the inverting input terminal, and a differential input amplifier to which an AC signal is input via the first resistor, and between the inverting input terminal and the output terminal of the differential input amplifier A second resistor connected to the other end of the first resistor, and a series circuit including a third resistor and an ingector connected to the other end of the first resistor. A second phase shift circuit connected to the non-inverting input terminal of the differential input amplifier;

Wherein the first and second phase shift circuits and the phase inverting circuit are cascaded, respectively, and added to the first stage circuit of the cascade-connected plurality of circuits by the adding circuit. And the signal output from the last-stage circuit is input to one end of the feedback impedance element as the feedback signal. A tuning method characterized in that one of the outputs of a plurality of circuits is taken out as a tuning signal.

60. The method of connecting the reactance element comprising the capacitor or the inductor constituting the series circuit and the third resistor is the same in the two phase shift circuits. Tuning amplifier according to range 59.

6 1. The tuning amplifier according to claim 59, wherein the differential input amplifier is an operational amplifier.

6 2. Each of the input impedance element and the return impedance element is a resistor. At least one of these resistors is formed by a variable resistor, and the resistance ratio of the input impedance element and the feedback impedance element is changed. And the maximum attenuation is changed according to (9) Tffl ₀

6 3. The third resistor included in at least one of the two phase shift circuits is a variable resistor, and a tuning frequency is changed by changing a resistance value of the variable resistor. 10. The tuned amplifier according to 9.

6 4. The tuning amplifier according to any one of claims 1 to 63, wherein the tuning amplifier is formed as a semiconductor integrated circuit.