WO1996007971A1

WO1996007971A1 - Method and apparatus for automatically configuring an interface

Info

Publication number: WO1996007971A1
Application number: PCT/US1995/010525
Authority: WO
Inventors: David J. Warman; Mark A. Lacas
Original assignee: Medialink Technologies Corporation
Priority date: 1994-09-09
Filing date: 1995-08-17
Publication date: 1996-03-14

Abstract

Method and apparatus for allowing an electronic device (16) to communicate with one or more other electronic devices (14, 18, 22, 24, 52) via various communication protocols. The apparatus includes an I/O board (30) and a processor board (32). The I/O board (30) includes a plug (64, 66) for connecting to a particular type of transmission medium (10) and an electronic identifier (76) providing an identification of a first communication protocol with which the I/O board (30) is constructed to be used. The I/O board (30) and the processor board (32) are coupled together by a detachable connector (71). The processor board (32) includes a processor (90) and memory (90, 92). By disconnecting the I/O board (30) from the processor board (32), another I/O board (58) that is constructed to be used with a second communication protocol can be coupled to the processor board (32). The memory (90, 92) on the processor board (32) stores two units of program code (134, 136), one of which is used to communicate according to the first communication protocol and the other of which is used to communicate according to the second communication protocol. To automatically configure itself, the processor board (32) reads the electronic identifier (76) on the I/O board (32, 58) connected to the processor board (32), and based thereon selects the appropriate unit of program code (134, 136) so that the electronic device (16) communicates according to the specified communication protocol.

Description

METHOD AND APPARATUS FOR AUTOMATICALLY CONFIGURING AN INTERFACE

Field of the Invention This invention relates to methods and apparatus for interfacing an electronic device with one or more other electronic devices and, more particularly, methods and apparatus for providing a network interface or a point-to-point interface.

Background of the Invention

Electronic devices are being interconnected with increasing frequency. For example, in the music industry, amplifiers, equalizers, musical instruments, and various other devices are commonly interconnected to a control panel that can control the various devices. The various devices can also be interconnected to allow the devices to communicate with one another. Various transmission media such as fiber optic cables, coaxial cables, ribbon cables, and twisted wire pair cables can be used to interconnect electronic devices to allow the devices to communicate with one another. Furthermore, various communication protocols exist.

Typically, an interface card is included in an electronic device to allow the electronic device to communicate with other devices via a particular type of transmission medium and a particular communication protocol. That is, the interface card is constructed for use with a particular type of transmission medium and a particular type of communication protocol. As a result, if it is desired that an electronic device communicate via a different transmission medium or a different communication protocol than the one in use, the device's interface card must be changed to one dedicated to the desired type of transmission medium and communication protocol. Unfortunately, interface cards are expensive because typical interface cards include numerous electronic components including processors, drivers, memory, clocks, and connectors. Thus, in addition to the inconvenience of having to replace the interface card to change to a different transmission medium or communication protocol, such a change is costly. Interface cards that are compatible with more than one type of transmission medium and communication protocol do exist. Such multiple use interface cards include drivers and connectors for each type of transmission medium supported. While multiple use interface cards are more flexible than interface cards that are dedicated to a particular transmission medium and communication protocol, multiple use interface cards are more expensive because of the extra hardware and software they include. Furthermore, if a transmission medium or communication protocol that is not supported by a multiple use interface card is to be used, a new interface card is again required.

To reduce the cost of changing to a different transmission medium or communication protocol, interface cards divided into two separate boards have recently been developed. One of the boards includes a processor, memory, a clock, etc. The memory on this processor board typically includes read only memory (ROM) that contains program code in the form of firmware for communicating with a particular communication protocol. Another board (I/O board) includes connector plugs for connecting to a particular type of transmission medium and drivers for receiving and supplying signals on the plugs. The benefit of dividing an interface card into two boards is that changing to a different type of transmission medium may only require replacing the I O board. However, changing to a different communication protocol requires replacing the firmware on the processor board. This requires replacing ROM chips and, if as is generally the case, part of the firmware is contained within the processor chip on the processor board, the processor chip must also be replaced.

To solve the foregoing and other shortcomings in the prior art, an interface card that can easily and inexpensively accommodate various transmission media and communication protocols is needed. Furthermore, the interface card should automatically configure itself for the appropriate communication protocol. As explained in the following, the present invention provides an interface card that meets these criteria and solves other problems in the prior art.

Siimmarv of the Invention In accordance with this invention, an interface apparatus for allowing an electronic device to communicate with one or more other electronic devices via various communication protocols is provided. The apparatus includes an I/O board and a processor board. The I/O board includes a plug, a driver, an electronic identifier, and a connector. The I/O board is connectable to a particular type of transmission medium via the plug. The driver is coupled to the plug for producing signals on the transmission medium. The electronic identifier provides an identification of a first communication protocol with which the I/O board is constructed to be used. The processor board includes a connector, memory, and a processor coupled to the memory and the connector. The processor board and I/O board are coupled together by connecting their connectors. Disconnecting the I/O board from the processor board allows another I/O board that is constructed to be used with a second communication protocol to be coupled to the processor board.

The memory on the processor board stores two units of program code, one of which is used to communicate according to the first communication protocol and the other of which is used to communicate according to the second communication protocol. The processor reads the electronic identifier on the I/O board connected to the processor board, and analyzes the identification provided by the electronic identifier to determine which of the two communication protocols is to be followed. The processor then selects the appropriate unit of program code in the memory, i.e., if the identification specifies the first communication protocol, the corresponding program code is selected. The processor executes this. unit of program code so that the electronic device communicates with one or more other devices according to the specified communication protocol.

In accordance with further aspects of the invention, the first communication protocol is a bus network communication protocol and the second communication protocol is a point-to-point communication protocol. Furthermore, in one preferred embodiment of the invention, the I O board that is constructed to be used with the first communication protocol is connectable to a fiber optic cable. The second I/O board that is constructed to be used with the second communication protocol is connectable to a RS232 cable. In accordance with further aspects of the invention, the processor included on the processor board requires no program code from the I/O board.

In accordance with still further aspects of the invention, the electronic identifier comprises a dip switch.

In accordance with still further aspects of the invention, the identification provided by the electronic identifier on the I O board also identifies the baud rate at which the I/O board is intended to be used. The processor on the processor board analyzes the identification to determine the appropriate baud rate and executes one of the two units of program code so that the electronic device with which the interface apparatus is used communicates according to the specified communication protocol at the specified baud rate. As will be appreciated from the foregoing brief summary, the invention also provides a method for execution by the processor on the processor board for automatically configuring the processor board based upon the I O board connected to the processor board. The method includes reading the electronic identifier on the I/O board, analyzing the identification provided by the electronic identifier to determine the specified communication protocol, and selecting the unit of program code that corresponds to the specified communication protocol. The selected unit of program code is then executed so that the electronic device with which the interface apparatus is used communicates with one or more other electronic devices according to the specified communication protocol. In accordance with further aspects of the invention, the method is performed during a start-up initialization of the electronic device.

As will be appreciated from the foregoing brief summary, the present invention provides a method and apparatus for allowing an electronic device to communicate with one or more other devices via various communication protocols and various transmission media. To change between transmission media and/or communication protocols, only the I/O board needs to be changed. Because the I/O boards provided by the present invention contain very few components, the I O boards are inexpensive. For example, because the processor on the processor board requires no program code from the I/O board, no memory is required on the I O board for storing program code. Furthermore, because memory included on the processor board includes a unit of program code for each communication protocol, no physical change, e.g., replacing components, is needed to the processor board when the communication protocol is changed. As will be still further appreciated from the foregoing brief, summary, the method of the present invention automatically configures the processor board to use the appropriate communication protocol and baud rate. As a result, no human intervention is required to reconfigure the processor board.

Brief Description of the Drawings The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIGURE 1 is a pictorial diagram of electronic devices interconnected in a bus network configuration with which the present invention can be used; FIGURE 2 is a block diagram of the electronic devices and bus network shown in FIGURE 1;

FIGURE 3 is a block diagram representation of two electronic devices interconnected in a point-to-point configuration with which the present invention can be used; FIGURE 4 is a block diagram of an amplifier including a processor board and an I/O board formed in accordance with the invention;

FIGURE 5 is a block diagram representation of a software firmware paradigm that is preferably used in the processor board provided by the present invention; and FIGURE 6 is a flow diagram of a method of automatically configuring the processor board based upon the I/O board that is connected to the processor board, in accordance with the invention.

Detailed Description of the Preferred Embodiment FIGURES 1 and 2 illustrate a bus network 10 interconnecting various electronic devices 12 with which the present invention can be used so that they can be controlled by signals on the network. The electronic devices shown include two audio amplifiers 14, 16, an audio equalizer 18, and two personal computers 22, 24. Other devices necessary to a complete sound system and their interconnection to the illustrated devices are not shown since they do not form part of this invention.

As shown in FIGURE 2, the personal computers 22, 24 are connected to the bus network 10 by way of bridges 26. In contrast, the amplifiers 14, 16 and the equalizer 18 each include an I/O board 30 and a processor board 32 formed in accordance with the invention to allow the devices to be directly connected to the bus network 10. The I/O board 30 is specifically constructed for use with the bus network configuration and a particular type of transmission medium, whereas the processor board 32 can be used with different communication configurations and transmission media. The processor board 32 is coupled to the I/O board 30 by way of connectors so that the I/O board 30 can be easily connected to and disconnected from the processor board 32. By disconnecting the I O board 30 from the processor board 32, another I/O board constructed for use with a different communication configuration and or transmission media can be connected to the processor board 32. FIGURE 3 illustrates a point-to-point configuration in which an amplifier 50 is connected to personal computer 52 by way of a cable 54 so that the personal computer can control the operation of the amplifier. For communicating with the personal computer 52, the amplifier 50 includes a processor board 32 and an I/O board 58. The processor board 32 is the same type of processor board that is included in the devices 14, 16, 18 shown in FIGURE 2, and accordingly the same reference numeral is used. The I/O board 58 is specifically constructed for use with the point-to-point configuration and a particular type of transmission medium.

Each of the processor boards 32 shown in FIGURES 2 and 3 determines the type of I O board to which it is connected, and based thereon, selects a unit of program code so that the appropriate communication protocol is used. In particular, the I/O boards 30, 58 include an electronic identifier 76, 80 that identifies the type of communication protocol with which the I/O boards 30, 58 should be used. Each processor board 32 stores units of program code for different communication protocols. The processor board 32 reads the electronic identifier on the I/O board that is connected to the processor board 32 to determine the appropriate communication protocol. Then, the processor board 32 executes the corresponding unit of program code. For example, in one preferred embodiment, the processor board 32 contains a unit of program code for use with the bus network configuration of FIGURE 2. This unit of program code is selected for execution by the processor board 32 if the I/O board 30 shown in FIGURE 2 is present. The processor board 32 also contains a separate unit of program code for use with the point-to-point configuration of FIGURE 3, which is selected if the I/O board 58 shown in FIGURE 3 is present, as explained in detail in the following. Inter-Device Communication

With respect to FIGURE 2, the processor board 32 controls the communication of the devices 14, 16, 18 over the bus network 10. For example, if the equalizer 18 wants to send data, a command, or program code (collectively referred to herein as data), the processor board 32 housed in the equalizer 18 constructs a packet of data representing the desired information. The processor board 32 determines the time at which the bus network 10 is available for sending the packet. The processor board 32 sends the packet to the I/O board 30 at the appropriate time, and upon receipt of the packet, the I/O board transmits the packet onto the bus network 10. At the amplifier 16, the I/O board 30 receives the packet over the bus network 10, and sends the packet to the processor board 32. Upon receipt of the packet, the processor board 32 processes the packet and performs any appropriate function, possibly including sending a response packet back to the equalizer 18.

The processor boards 32 in the devices 14, 16, 18 are connected to other components in the devices to either control the devices directly or to control the devices in conjunction with other processors or controllers within the devices. For example, the amplifier 16 can include various analog electronics that are controlled by the processor board 32 based upon packets received over the bus network 10. Furthermore, while the processor board 32 is illustrated as a separate board, the components of the processor board 32 could be integrated into a larger board in the device, or the processor board 32 could be a section of a larger board.

The personal computers 22, 24 are not directly connected to the bus network 10. Rather, the personal computers 22, 24 are connected via RS232 interfaces 34 and the bridges 26. Standard personal computers typically include an RS232 card 36 for communicating with external devices such as printers. RS232 is an interface standard that specifies signal voltage levels, etc. RS232 is also a byte- level communication protocol that specifies start bits, stop bits, etc. for sending bytes of data. Generally, a higher level communication protocol is used on top of the RS232 byte-level communication protocol.

As show in FIGURE 2, the personal computers 22, 24 each include an RS232 interface card 36 and an RS232 cable 38. The personal computers 22, 24 also include software defining a point-to-point communication protocol that is used on top of the RS232 byte-level protocol. The bridges 26 provide the interface between the RS232 cables 38 and the bus network 10. Each bridge 26 includes a RS232 I/O card 40 for connecting to the RS232 cable 38, and a second I/O card 42 that is constructed for connecting to the transmission medium of the bus netwoik 10. The bridges 26 include a bridge processor board 44 connected to each of the I/O boards 40, 42, to translate between the point-to-point communication protocol and the bus network communication protocol used on the bus network 10.

The bus network 10 shown in FIGURES 1 and 2 can be formed of various transmission media such as glass or plastic fiber optic cables, coaxial cables, twisted wire pair cables, ribbon cables, etc. In the music industry it is generally preferable to use fiber optic cables, as fiber optic cables are highly immune to electromagnetic interference and ground loops, and are capable of carrying signals over long distances without significant attenuation. As described herein, the bus network 10 represents fiber optic cables. Accordingly, the I/O board 30 shown in FIGURE 2 is constructed for use with fiber optic cables. As previously explained, the I/O board 30 can be easily connected and disconnected from the processor board 32. If the transmission medium of the bus network 10 is changed, e.g., to coaxial cables, the I/O boards 30 are disconnected from the processor boards 32 and replaced with I/O boards that are constructed for connecting to coaxial cables. The processor boards 32 remain unchanged. With respect to the bridges 26, the I/O card 42 would be changed.

Various network communication protocols can be used to communicate over the bus network 10. The particular network communication protocol used is dictated by the program code utilized by the processor boards 32 and the bridge processor boards 44. The communication protocol can be changed by changing the program code. In one preferred embodiment of the invention, the network communication protocol used to communicate over the bus network 10 is that described in U.S. Patent No. 5,245,604, entitled "Communication System", assigned to the assignee of the present application. The contents of U.S. Patent No. 5,245,604 are hereby incorporated by reference, and the network communication protocol described by U.S. Patent No. 5,245,604 is referred to herein as the MediaLink protocol.

In this preferred embodiment, the processor boards 32 contains program code for communicating over the bus network 10 in accordance with the MediaLink network communication protocol. The advantage of the MediaLink communication protocol is that it provides an upper limit on the amount of time it takes to communicate over the bus network 10. This is important in real-time environments such as a music performance stage, where unpredictable delay would result in unacceptable sound quality. As all network communication protocols must, the MediaLink protocol includes a netwoik resource sharing and management algorithm such that only one device communicates over the bus network 10 at any one given time and such that each device has sufficient access to the bus network 10.

A resource and access management is obviously not needed when two devices are interconnected in a point-to-point configuration as shown in FIGURE 3. As previously described, in the point-to-point configuration shown in FIGURE 3 the amplifier 50 is connected to the personal computer 52 via the RS232 cable 54. The personal computer 52 includes the RS232 card 56 for communicating over the RS232 cable 54. The personal computer includes software that defines a high level, point-to- point communication protocol, which is used on top of the RS232 byte-level communication protocol. In one preferred embodiment, the point-to-point communication protocol used is the same as the MediaLink network protocol, except that resource and access management of the MediaLink network protocol is excluded. This point-to-point communication protocol is referred to herein as the MediaWAN protocol.

With respect to FIGURE 3, the amplifier 50 includes the I O board 58 and the processor board 32, which is identical to the processor boards 32 illustrated in FIGURE 2. The I/O board 58 is similar to the I/O boards 30 shown in FIGURE 2, except that the I/O board 58 is constructed for use with a RS232 cable. The processor board 32 included in the amplifier 50 controls the communication of the amplifier 50 using separate program code for communicating in accordance with the MediaWAN point-to-point communication protocol. With respect to FIGURE 2, the bridge processor boards 44 include program code for both the MediaWAN point-to-point communication protocol and the MediaLink bus network communication protocol. The MediaWAN and MediaLink protocols are simultaneously used to provide the interface from the RS232 cables 38 to the bus network 10. The amplifier 50 shown in FIGURE 3 can be connected to the bus network 10 illustrated in FIGURE 2 by simply replacing the I/O board 58 with an I/O board 30, which is constructed for use with the bus network 10. As briefly explained above and as explained in detail below, the processor board 32 includes hardware and program code so that the processor board automatically senses the type of communication protocol to use based upon an identifier on the I/O board that is connected to the processor board 32.

Processor Board and I/O Board FIGURE 4 illustrates in greater detail the I/O board 30 and the processor board 32 in the amplifier 16 shown in FIGURES 1 and 2. The I/O board 30 includes two sets of plugs 64, 66, two drivers 72, 74, an electronic identifier 76, a shift register 75, and an application specific integrated circuit (ASIC) 73. The I/O board 30 is coupled to the processor board 32 by a ribbon cable 71. The processor board 32 includes a processor 90, an electronically erasable and programmable read¬ only memory (EEPROM) 92, a random access memory (RAM) 94, an application specific integrated circuit (ASIC) 73, and a timing clock (i.e., oscillator) 96.

With respect to the I/O board 30, the plugs 64, 66 are constructed to receive two fiber optic cables 68, 70, as shown in FIGURE 1. The drivers 72, 74 are respectively coupled to the plugs 64, 66 to produce light signals at the plugs to which the drivers are connected. The two sets of plugs 64, 66 are provided to allow the I/O board 30 to be used on a bus network 10, as illustrated in block diagram form in FIGURE 2. With fiber optic cables it is generally not possible to tap off of the cable. Rather, a fiber optic cable is connected at each of its ends to a device without any taps along the length of the cable. To form a bus network configuration, the devices are "chained" together by fiber optic cables, as shown in FIGURE 1. Except for the two devices at the ends of the "chain" of devices, two fiber optic cables are connected to each device, connecting the device to adjacent devices in the chain. Whenever a device communicates, the device produces light signals on both fiber optic cables. Similarly, if a device receives light signals on one cable, the device produces duplicate signals on the other cable. Functionally, the result is the bus network shown in FIGURE 2. As is well known by those skilled in the pertinent art, a fiber optic cable consists of a send strand for sending signals and a receive strand for receiving signals. Each set of plugs 64, 66 includes a receive plug 61, 63 to which a receive strand is connected and a send plug 67, 69 to which a send strand is connected. The receive plugs 61, 63 include light sensors that produce corresponding electrical signals, and the send plugs 67, 69 include light emitters. The drivers 72, 74 are connected to the send plugs 67, 69.

The ASIC 73 is connected to the drivers 72, 74 and the receive plugs 61, 63. During normal operation, the ASIC 73 couples the receive plugs 61, 63 to the drivers 72, 74, such that when light signals (representing serial data) are received at the receive plug of one of the sets of plugs 64, 66, duplicate signals are produced at the send plug of the other set of plugs. Also during normal operation, serial data received at the receive plugs 61, 63 is "piped" through the ASIC 73 to the processor 90, via the ribbon cable 71. The processor 90 includes a serial universal asynchronous receiver/transmitter (SUART) that receives the serial data. The SUART converts the serial data to parallel bytes of data which are processed by the processor 90.

When the amplifier 16 wants to send data to other devices on the bus network, the processor board 32 generates a packet of data that consists of several bytes of data. The bytes of data are converted into a serial stream of digital electrical signals by the SUART. The serial data produced by the SUART is sent to the ASIC 73, which pipes the serial data to both drivers 72, 74, so that the data is simultaneously sent out each of the send plugs 67, 69.

The ASIC 73 is also provided to allow for various test modes, e.g., an internal loop-back mode, and an external loop-back mode. For example, during a internal loop-back mode, the ASIC 73 sends any received serial data signals from the processor 90 back to the processor 90, instead of to the send plugs 67, 69. The mode of the ASIC 73 is controlled by the processor 90 via the shift register 75. The shift register 75 is used to allow a serial control line of the processor 90 to control the ASIC 73, which requires parallel control lines. For example, in one preferred embodiment, the ASIC 73 requires four parallel lines (bits) to select its mode. The shift register 75 shifts four bits sent over the serial control line of the process 90 into four bits, which are applied to the ASIC 73.

The electronic identifier 76 included on the I/O board 30 identifies the communication protocol and the baud rate with which the I/O board 30 is constructed to be used. In one preferred embodiment, the electronic identifier 76 is a dip switch set to identify the baud rate and the communication protocol. However, those skilled in the pertinent art will readily recognize that other devices could easily be used to serve as the identifier 76. For example, the electronic identifier 76 could be formed of electronic circuitry wired to uniquely identify the baud rate and communication protocol. The identifier 76 could also be formed of a small memory device storing one or more bytes of data to uniquely identify the baud rate and communication protocol. With respect to the use of a dip switch for the electronic identifier 76, multiple pins on the dip switch must be read to determine the identification provided by the dip switch. The shift register 75 is connected to these pins, and converts the parallel data into serial data that is sent to the processor 90.

In one preferred embodiment, one end of the ribbon cable 71 is secured to the processor board 32 and the I/O board 30 includes a connector to which the other end of the ribbon cable 71 can be connected. The ribbon connector 71 can be disconnected from the I O board 30, so that a different I/O board can be connected to the processor board 32. In one preferred embodiment of the invention, at least two types of I/O boards are provided, one for use with a bus network communication protocol (e.g., the MediaLink protocol) and the other for use with a point-to-point communication protocol (e.g., the MediaWAN protocol). The I/O board 30 shown in FIGURE 4 is constructed for use with a bus network communication protocol at a 125k baud rate, with the bus netwoik 10 formed of fiber optic cables.

The I O board 58 shown in FIGURE 3 is constructed for use with a point-to- point communication protocol, with the transmission medium formed of the RS232 cable 54. The I/O board 58 contains the same basic components as the I/O board 30, except as follows. The I O board 58 has a single plug 82, to which the RS232 cable 54 is connected. Because there is only a single plug 82, the I O board 58 includes only one driver 84 (a RS232 driver), which is connected to the plug. As with respect to the I/O board 30, the I/O board 58 includes a shift register 81 and an ASIC 83, and is connected to the pr ΪJSSOΓ board 32 by a ribbon cable 87. The I/O board 58 includes an electronic identifier 80 that identifies the point-to-point communication protocol and the baud rate with which the I/O board is constructed to be used. In one preferred embodiment of the invention, two types of I/O boards for use with the RS232 cable are provided: one running at 125k baud; and the other running at 9600 baud.

With respect to the processor board 32, the processor 90 preferably includes read-only memory (ROM) that stores program code for controlling the communication of the amplifier 16 with other devices. The EEPROM 92 on the processor board 32 contains application program code for use by the processor 90 for controlling the functionality of the amplifier 16. The RAM 94 is used by the processor 90 during operation to temporarily store data and some program code. The clock 96 generates a timing signal upon which the operation of the processor 90 is based. The ASIC 83 on the processor board 32 decodes address lines from the processor 90 to control the processor's access to the EEPROM 92 and RAM 94. During startup initialization of the processor board 32, the processor board 32 reads the electronic identifier 76 on the I/O board 30 to determine the baud rate and the communication protocol that are to be used, and selects the corresponding program code stored within the processor 90. In one preferred embodiment of the invention, the processor board 32 supports the MediaLink bus network communication protocol and the MediaWAN point-to-point communication protocol. The MediaLink bus network communication protocol is used with the bus network 10 shown in FIGURES 1 and 2, and the MediaWAN communication protocol is used with the point-to-point configuration shown in FIGURE 3. Thus, if the processor board 32 determines during startup initialization that the I/O board 30 is present, the MediaLink bus network communication protocol is followed, and if the I/O board 58 is present, the MediaWAN communication protocol is followed.

Readily available digital and analog electronic components can be used to form the components of the I/O boards 30, 58 and the processor board 32 shown in FIGURES 3 and 4. For example, in one preferred embodiment, the processor 90 is one of the HC11 family of chips manufactured by Motorola, in particular, the 68HC711E9, which includes on-board ROM for storing program code used by the processor 90 for communication. The EEPROM 92 can be an KM28C64-20 chip mamrfactured by Samsung, which is desirable because it can be reprogrammed using standard digital voltages. Persons skilled in the relevant art will readily recognize that some additional electronics not shown, e.g., resistors, capacitors, latches, etc. are needed to implement the I/O boards 30, 58 and the processor board 32 at the circuit level. Such persons will also readily know how to interconnect the various components at the circuit level. Accordingly, to avoid unduly complicating the present disclosure, these details are omitted.

Bridge The circuitry of the bridges 26 illustrated in block diagram form in FIGURE 2 includes many of the same components as the processor board 32 and the I/O cards 30, 58. The bridge processor board 44 includes a processor chip 100, e.g., one of the HC11 family of Motorola processors. The bridge processor board 44 also includes a timing clock 102, a RAM 104, and a EEPROM 106. The I/O board 42 is similar in structure to the I/O board 30, and the I/O board 40 is similar in structure to the I/O board 58. Each of the I/O boards 40, 42 include appropriate plugs for connecting to the type of external cable to which they are intended to be connected. The I/O board 42 includes fiber optic cable plugs for connecting to the bus network 10, and the I/O board 40 has an RS232 plug for connecting to the RS232 cable 38. The I/O board 40 includes a RS232 driver 108, and the I/O board 42 includes two fiber drivers 110 and 112. The processor chip 100 includes a UART port that is used to send and receive serial data from the I/O board 42. The bridge processor board 44 also includes an external UART (not shown) for sending and receiving serial data from the I/O board 40. The I/O boards 40, 42 also include electronic identifiers (not shown) to identify the transmission medium and communication protocol with which the I/O boards 40, 42 are intended to be used. At start-up initialization of the bridge 26, the bridge processor board 44 determines the type of I/O boards present and selects the appropriate program code, as described with respect to the processor board 30. To make the bridge 26 compatible with a different transmission medium and/or communication protocol, the I/O board 40, 42 could be replaced with appropriate I/O boards. As is the case with respect to the processor board 32 and I/O board 30 shown in FIGURE 4, the circuit-level implementation of the bridge can be carried out in various ways, as will be readily appreciated by those skilled in the pertinent art. Program Code Paradigm

FIGURE 5 illustrates the organization of the program code within one preferred embodiment of the processor board 32 shown in FIGURE 4. The program code is organized into units (referred to herein as SoftSlots) in the ROM in the processor 90 and in the EEPROM 92. The SoftSlots 120, 122 are based in part upon the object-oriented programming paradigm in that each SoftSlot 120, 122 is a class defining variables and methods (i.e., functions). Instances, i.e., objects, of each SoftSlot are formed by instantiation. A SoftSlot can be defined as a parent or child of another SoftSlot, so that inheritance of variables and methods is possible. These aspects of the SoftSlots will be readily recognized by those skilled in object-oriented programming. In addition to the object-oriented paradigm of the SoftSlots, the

SoftSlots 120, 122 are organized as a linked list. In particular, beginning with the TAPCORE SoftSlot 124 in the processor 90 and the final SoftSlot 126 in the EEPROM 92, each SoftSlot points to a subsequent SoftSlot. At start-up, the SoftSlots are sequenced through in the order of the linked list. As each SoftSlot is processed, each SoftSlot performs certain needed hardware and software initialization. After the initialization is performed, instances (i.e., objects) of the SoftSlots are created. During normal operation of the processor board 30, the objects perform various functions, including creating additional objects, for controlling the functionality and communication of the device in which the processor board 30 is housed.

The program code provided by the SoftSlots forms the basic operating system of the processor 90, controls the communication of the device in which the processor board 32 is housed, and possibly controls the functionality of the device. The operating system is a multi-tasking operating system that organizes tasks in a task ring, in which the tasks are sequentially executed.

The SoftSlots included in one preferred embodiment of the invention are illustrated in FIGURE 5 and briefly described in the following. The actual program code in each SoftSlot can be implemented in various ways, as will be appreciated by those skilled in the pertinent art. The TAPCORE SoftSlot 124 is an ancestor of all other SoftSlots and includes basic operating system methods and variables. In the linked list of SoftSlots for startup initialization, the TAPCORE SoftSlot 124 is the first SoftSlot and it points to the EVENT SoftSlot 126. The EVENT SoftSlot 126 is a child of the TAPECORE and defines variables and methods for providing the multi¬ tasking task ring. In the linked list, the EVENT SoftSlot points to the I/O PORT SoftSlot 128. The I/O PORT SoftSlot 128 is also a child of the TAPCORE SoftSlot. It is a virtual SoftSlot in that during normal operation no instances of the I/O PORT SoftSlot are created. Rather, the I/O PORT SoftSlot defines variables and methods that are inherited by SoftSlots that are descendants of the I/O PORT SoftSlot. The variables and methods defined by the I O PORT SoftSlot support interfacing the I/O board 30. The I/O PORT SoftSlot points to the PACKET SoftSlot 130 in the linked list. The PACKET SoftSlot 130 provides variables and methods that define packets, which are the unit of information communicated between devices in the MediaLink and MediaWAN communication protocols. The PACKET SoftSlot is a child of the EVENT SoftSlot, so that packets are events that control the execution of themselves. The PACKET SoftSlot 130 points to the UART SoftSlot 132, which defines variables and methods for controlling the UART within the processor 90. The UART SoftSlot is a child of the IO Port SoftSlot.

The UART SoftSlot 132 points to the MEDIALINK SoftSlot 134, which in turn points to the MEDIAWAN SoftSlot 136. The MEDIALINK SoftSlot provides variables and methods that define the MediaLink bus network communication protocol, and the MEDIAWAN SoftSlot provides variables and methods that define the MediaWAN point-to-point communication protocol, supporting a 125k baud rate, a 9600 baud rate and other baud rates. The MEDIALINK and MEDIAWAN SoftSlots 134, 136 are each a child of the IO Port SoftSlot. The MEDIAWAN SoftSlot 136 points to the Virtual Device Management

(VDM) SoftSlot 138, which is a child of the TAPCORE SoftSlot. The VDM SoftSlot 138 provides variables and methods that identify the type of device, e.g., an amplifier, that the processor board 32 is housed in, and the VDM SoftSlot 138 provides methods that allow the device to identify itself when queried by other devices. The VDM SoftSlot 138 also provides methods that allow the processor 90 to write to the RAM 94 and program the EEPROM 92 on the processor board 32.

The VDM SoftSlot 138 points to the NULL APP SoftSlot 140, which is the last SoftSlot within the processor 90. The NULL APP SoftSlot 140 is a child of the TAPCORE SoftSlot and provides variables and methods that define a generic device. The functionality and identity of the device in which the processor board 32 is housed is defined by the NULL APP SoftSlot, unless there is one or more APPLICATION SoftSlots 122 within the EEPROM 92. The NULL APP SoftSlot reads the identifier on the I/O board 30, and based thereon selects either the bus netwoik protocol defined by the. MEDIALINK SoftSlot 134 or the point-to-point communication protocol provided by the MEDIAWAN SoftSlot 136, as described below.

The NULL APP SoftSlot 140 points to the first APPUCAΗON SoftSlot 142 in the EEPROM 92, if there is one. More particularly, the NULL APP SoftSlot 140 points to a memory location in the EEPROM 92 that points (i.e., contains the memory address location) of the first APPLICATION SoftSlot 142; the bytes at this memory location are referred to herein as link bytes. If there are no APPLICATION SoftSlots or any other SoftSlots in the EEPROM 92, the link bytes contain zeros. In this case, during start-up initialization of the processor board 32, a determination is made that the device should run as a generic device as defined by the NULL APP SoftSlot 140. In contrast, if there are one or more APPLICATION SoftSlots 122 within the EEPROM 92, they define the identity and functionality of the device in which the processor board 32 is housed. The parent-child relationship of the APPLICATION SoftSlots 122 depends on the nature of the particular APPLICATION SoftSlot.

In addition to containing APPLICATION SoftSlots 122 to define the functionality of the device, the EEPROM 92 can contain SoftSlots that override a portion of the program code provided by the various SoftSlots 120 within the processor 90. For example, if it is desired to change a portion of the MEDIALINK SoftSlot 134, a SoftSlot can be electrically programmed into the EEPROM 92 to patch or override the desired portion of the MEDIALINK SoftSlot 134.

Method of Automatic Configuration The flow diagram in FIGURE 6 illustrates the process performed by the processor board 32 to select the proper communication protocol and baud rate based upon the identifier on the I O board that is connected to the processor board. The process is performed as part of the start-up initialization, during which the linked-list of SoftSlots 120, 122 illustrated in FIGURE 5 are sequenced through. In particular, as illustrated in FIGURE 6, first a series of software and hardware initialization steps 150 are performed by SoftSlots positioned prior to the NULL APP SoftSlot 140 in the linked-list of SoftSlots.

The NULL APP SoftSlot 140 performs the steps 152 through 160, which are referred to herein as the Auto Sense routine. First, as indicated by decision diamond 152, a deteirnination is made as to whether an I/O board is connected to the processor board 32. If no I/O board is connected to the processor board 32, the Auto Sense routine is bypassed and any remaining initialization steps 162 are performed. On the other hand, if a I/O board is present, e.g., the I/O board 30, the processor 90 reads the electronic identifier 76 on the I/O board 30, as indicated by the block 154. Then, at block 156, the processor 90 analyzes the identification provided by the identifier 76 to determine the proper communication protocol and baud rate to use. The processor 90 then locates the appropriate SoftSlot to provide the needed communication protocol, as indicated at block 158. For example, when the I/O board 30 is present for use with the bus network 10 at a 125k baud rate, the MEDIALINK SoftSlot 134 is utilized. In contrast, if the I/O board 58, which is constructed for use in a point-to-point configuration with an RS232 cable, is present, the MEDIAWAN SoftSlot 136 is utilized with either a 125k baud rate or a 9600 baud rate, depending on that specified by the identifier 80 on the I/O board 58. After locating the appropriate SoftSlot, program code contained within the SoftSlot is activated, as indicated at the block 160.

Any remaining initialization steps 162 specified by subsequent SoftSlots in the linked-list are then performed. After the start-up initialization is completed, the device runs according to the activated program code contained within the SoftSlots.

While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention. For example, while the processor board 32 described above only contained SoftSlots for two communication protocols, additional communication protocols can be readily supported by including additional SoftSlots in the processor board 32, in the ROM in the processor 90, in the EEPROM 92, or in some other memory device. The electronic identifier on an I/O board would identify which of the communication protocols is to be used. Furthermore, while only the fiber optic I/O board 30 was described for use with the bus network 10, various other I/O boards could be used if a transmission medium other than fiber optics is used for the bus network 10. In this case, if the processor board 32 must interact differently with different types of I/O boards for different transmission media, the SoftSlots would contain appropriate program code for each of the I/O board types for the various bus network transmission media. For example, if an I/O board constructed for a bus network formed of coaxial cables is used, the processor board 32 may require a different type of initialization. The electronic identifier on the I/O board would identify the type of transmission medium, and the processor board 32 would select the appropriate SoftSlot program code for the transmission medium type. Furthermore, configuration in addition to that previously described could be performed based upon the identification provided by the electronic identifier 76. For example, it is possible that a particular I/O board is to be used with various electronic identifier settings. In this case, the I/O board would configure itself based upon the electronic identifier setting. Hence, within the scope of the appended claims, it is to be understood that the invention can be practiced otherwise than as specifically described herein.

Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus that automatically configures itself for allowing an electronic device to communicate with one or more other electronic devices via various communication protocols, said apparatus comprising:

(a) an I/O board including:

(i) a plug connectable to a particular type of transmission medium for communication with one or more other devices, said plug suitable for receiving signals transmitted by said one or more other devices on said transmission medium;

(ϋ) a driver coupled to said plug for causing signals to be produced on said plug for transmission on said transmission medium to said one or more other devices;

(iii) an electronic identifier providing an identification of a first communication protocol, said I/O board being constructed to be used with said first communication protocol; and

(iv) a first connector coupled to said plug, said driver, and said electronic identifier; and

(b) a processor board including:

(i) a second connector detachably connected to said first connector of said I/O board to couple said I/O board to said processor board, said processor board processing signals received at said plug and producing signals for transmission on said transmission medium via said driver and said plug;

(ϋ) memory storing at least first and second units of program code, one of which is used to communicate according to said first communication protocol identified by said electronic identifier and the other of which is used to communicate according to a second communication protocol; and

(iii) a processor coupled to said memory and said second connector, said processor for: reading said electronic identifier on said I O board to determine said identification; analyzing said identification to determine which of said first and second communication protocols is to be followed; selecting one of said first and second units of program code to communicate according to said first communication protocol; and executing said one of said first and second units of program code so that said device communicates with said one or more other devices according to said first communication protocol.

2. The apparatus of Claim 1, wherein said processor requires no program code from said I/O board.

3. The apparatus of Claim 1, wherein: said identification provided by said electronic identifier on said I/O board also identifies a baud rate at which said I/O board is intended to be used; said processor analyzes said identification to determine said baud rate; and said processor executes said one of said first and second units of program code so that said device communicates with said one or more other devices according to said first communication protocol at said baud rate.

4. The apparatus of Claim 1, wherein said second connector is detachably connected to said first connector so that said I/O board can be disconnected from said processor board and a second I/O board constructed to be used with a second communication protocol can be coupled to said processor board, said second I/O board including a second electronic identifier providing a second identification of said second communication protocol.

5. The apparatus of Claim 4, wherein said particular type of transmission medium to which said plug of said I/O board is connectable comprises a fiber optic cable, and wherein said second I O board is formed to be used with a second type of transmission medium comprising a RS232 cable.

6. The apparatus of Claim 1, wherein said electronic identifier comprises a dip switch.

7. The apparatus of Claim 1, wherein said first communication protocol is a bus network communication protocol and said second communication protocol is a point-to-point communication protocol.

8. A method of automatically configuring an electronic device for communicating with one or more other electronic devices via various communication protocols, said electronic device detachably connected to an I/O board constructed to be connected to a particular type of transmission medium and for use with a first communication protocol, said I/O board including an electronic identifier providing an identification of said communication protocol, said electronic device including memory storing first and second units of program code, one of which is used to communicate according to said first communication protocol and the other of which is used to communicate according to a second communication protocol, said electronic device further including a processor, said method for execution by said processor, said method comprising the steps of:

(a) reading said electronic identifier on said I/O board to determine said identification;

(b) analyzing said identification to determine which of said first and second communication protocols is to be followed;

(c) selecting one of said first and seconds units of program code to communicate according to said first communication protocol; and

(d) executing said one of said first and second units of program code so that said electronic device communicates with said one or more other electromc devices according to said first communication protocol.

9. The method of Claim 8, wherein said electronic identifier on said I/O board comprises a dip switch and said step of reading said electronic identifier comprises determining settings of said dip switch.

10. The method of Claim 8, wherein: said identification provided by said electronic identifier of said I/O board also identifies a baud rate at which said I/O board is intended to be used; said step of analyzing said identification also analyzes said identification to determine said baud rate; and said step of executing said one of said first and second units of program code comprises executing said one of said first and second units of program code so that said electronic device communicates with said one or more other devices according to said first communication protocol at said baud rate.

11. The method of Claim 8, wherein said method is performed during startup initialization of said electronic device.

12. The method of Claim 8, wherein said first communication protocol is a bus network communication protocol and said second communication protocol is a point-to-point communication protocol.

13. A processor board that automatically configures itself for allowing an electronic device to communicate with one or more other electronic devices via various communication protocols, said processor board comprising:

(a) a connector detachably connectable to an I/O board to couple said I/O board to said processor board, said I/O board being constructed to be connected to a particular type of transmission medium for use with a first communication protocol, said I O board including an electronic identifier providing an identification of said first communication protocol;

(b) memory storing first and second units of program code, one of which is used to communicate according to said first communication protocol and the other of which is used to communicate according to a second communication protocol; and

(c) a processor coupled to said memory and said connector, said processor for:

(i) reading said electronic identifier on said I/O board to determine said identification;

(ϋ) analyzing said identification to determine which of said first and second communication protocols is to be followed;

(iii) selecting one of said first and seconds units of program code to communicate according to said first communication protocol; and

(iv) executing said one of said first and second units of program code so that said electronic device communicates with said one or more other devices according to said first communication protocol.

14. The processor board of Claim 13, wherein said processor requires no program code from said I/O board.

15. The processor board of Claim 13, wherein: said identification provided by said electronic identifier on said I/O board also identifies a baud rate at which said I/O board is intended to be used; said processor analyzes said identification to determine said baud rate; and said processor executes said one of said first and second units of program code so that said device communicates with said one or more other devices according to said first communication protocol at said baud rate.

16. The processor board of Claim 13, wherein said connector is detachably connectable to said I/O board so that said I/O board can be disconnected from said processor board and a second I/O board constructed to be used with said second communication protocol can be coupled to said processor board, said second I/O board including a second electronic identifier providing a second identification of said second communication protocol.

17. The processor board of Claim 16, wherein said first type of transmission medium with which said I/O board is constructed to be used comprises a fiber optic cable, and wherein said second I/O board is formed to be used with a second type of transmission medium comprising a RS232 cable.

18. The processor board of Claim 13, wherein said first communication protocol is a bus network communication protocol and said second communication protocol is a point-to-point communication protocol.