WO1996023353A1

WO1996023353A1 - Finite impulse response filter

Info

Publication number: WO1996023353A1
Application number: PCT/US1995/015219
Authority: WO
Inventors: Alan G. Corry
Original assignee: Microunity Systems Engineering, Inc.
Priority date: 1995-01-23
Filing date: 1995-11-21
Publication date: 1996-08-01
Also published as: AU4243296A; US5500811A

Abstract

A compact FIR filter uses one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize an FIR filter for performing real-time filter is therefore reduced.

Description

FINITE IMPULSE RESPONSE FILTER

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to digital filters and, more particularly, to Finite Impulse Response (FIR) filters.

2. State of the Art

In conventional practice, computations involved in realizing a FIR filter have been memory-access intensive. One data output point of a FIR filter is calculated as

N

ι=l

and a succeeding output data point is calculated as

N Y₂ = 2 A_lX_i = A₁X₂+..A_NX_{N 1}

where A_j is one of a series of coefficients defining a windowing function of the filter and X_j is one of a series of input data points.

Figure 1 shows a known system for performing the foregoing computations. In the system, the coefficients A_j and the input data points X_j are stored in a random access memory 11. The RAM 11 is addressed by an address generator 13 to output corresponding A^ and X_j to a multiplier 15 to form the product A_jX_j. The product A^X_j is input to either an adder 17 or, in the case i= l , to an accumulator register 19 through a multiplexer 16. When i ≠ , the previous sum j = 1

stored in the accumulator register 19 is added to the current product A^X_j in the adder 17 and the cumulative result is stored in the accumulator register 19 through the multiplexer 16. After the sum of the N products has been accumulated in the accumulator register 19, the contents of the accumulator register 19 is output as an output data point. In practice, the coefficients A_j may either be fixed in the case of a non-adaptive filter or may be varied between the calculation of output data points in the case of an adaptive filter.

The system of Figure 1 requires the address generator 13 to generate 2N addresses per output data point despite the fact that of the 2N operands involved in the calculation, only one of the operands, a new input data point, may differ from the operands involved in the previous calculation.

To address the foregoing problem, various modifications to the basic circuit arrangement of Figure 1 have been proposed. For example, in U.S. Patent No. 5,297,069, incorporated herein by reference, a circuit is disclosed for realizing a FIR filter that is similar to the circuit of Figure 1 except that it additionally includes a buffer memory 20 between the RAM 11 and the multiplier 15, as shown in Figure 2. Output data points of a digital filter are calculated by storing input data points in an addressable memory and accessing the addressable memory to supply a new input data point exactly once for each output data point after a first output data point and storing each input data point in a first recirculating memory for so long as that input data point is needed to calculate a next output data point. The input data points stored in the first recirculating memory (recirculating shift register 21) are used to calculate output data points. Furthermore, coefficients are stored in a second recirculating memory (recirculating shift register 23) and used to calculate the output data points. The recirculating shift register 21 has one less stage than the recirculating shift register 23 in order to "shift" the series of input data points X_j with respect to the series of coefficients A . In the circuit of Figure 2, only one memory access is required per output data point.

The circuit of Figure 2 can be modified to realize special cases of the general FIR filter in a computationally efficient manner. For example, in the case of an odd FIR filter, even-indexed coefficients A₂, A₄, A^... are uniformly zero. Therefore, imagining the series of coefficients being "shifted across" the longer series of input data points after the calculation of each output data point, the zero even-indexed coefficients will first be aligned with even- indexed input data points, then with odd-indexed input data points, then again with even-indexed input data points, and so forth such that half the X_j's are not used to calculate each output. The X_j's can therefore be split into two recirculating shift registers, one holding even-indexed X_j and the other holding odd-indexed X_j. The shift registers are then used alternately for every other output calculation.

The circuit of Figure 2 may also be modified to realize a symmetric FIR filter. In a symmetric FIR filter, the first and last coefficients A_j and A_n are equal as are the second and next to last coefficients A₂ and A_n__j , and so forth. To realize a symmetric FIR filter in a computationally efficient manner, only one of each pair of equal coefficients is stored and the input data points corresponding to the pair of equal coefficients are added and multiplied by the single stored coefficient since AJXJ + A_nX_n = A_j(X^ +X_n) for A_j = A_n. Modified circuits for realizing odd and symmetric FIR filters are described in the aforementioned U.S. Patent No. 5,297,069. Special forms of the symmetric FIR filter include the polyphase interpolating symmetric FIR filter and the polyphase decimating symmetric FIR filter. In the polyphase interpolating symmetric FIR filter the N input samples X_j are composed of recurring sequences of one non-zero sample followed by D- 1 zero samples. In the polyphase decimating symmetric FIR filter the N input samples X_j are composed of recurring sequences of one wanted sample followed by D-l unwanted samples. In both cases, since it is known a priori that the result of most multiplies will either be zero or will be "thrown away," this characteristic of the input samples allows the N-point convolution to be rewritten as D N/D-point convolutions. Take for example the case of a 16- point interpolating symmetric filter with the following coefficients and input sequence:

Table I

COEFFICIENTS AQ A_j A₂ A₃ A₄ A₅ A₆ A_? A_? A₆ A₅ A₄ A3 A₂ A_j AQ

INPUT SEQUENCE 0 0 0 X3 0 0 0 X₂ 0 0 0 X_j 0 0 0 X_Q

Because of the characteristics of the input sequence, the N = 16-point convolution can be rewritten as N/D (16/4 = 4) four-point convolutions. In particular, note that as the data input sequence is "shifted across" the coefficient sequence, the coefficients to be multiplied by non-zero data values occur in repeating groups of four, i.e., {AQ, A₄, A₇, A3}, {A3, A7, A₄, AQ},

{A₂, A_(j, A5, A_j} and {A_j , A5, A^, A₂}. The convolution may therefore be written as follows:

/ = /₀ then/_j then/₂ then/₃

then A₃X! -I- A_?X₂ + A₄X₃ + A_QX₄ then A₂X_j + A_?X₂ + A₄X₃ + AQX₄ then A_lX_{ + A₅X₂ + A₆X₃ + A₂X₄

A generalized block diagram of a polyphase interpolating filter is shown in Figure 3. The input data points are input in common to the individual filter phases s f_Q, f_j, f and f3- A commutator is used to sequentially select the output point of one of the filter phases as the output point of the overall polyphase interpolating filter.

In the case of a polyphase decimating filter, on the other hand, the N- point convolution to be again be rewritten as D N/D-point convolutions, but the filter utilizes a different structure. Take for example the case of a 16-point, decimate-by-four symmetric filter with the following coefficients and input sequence:

Table II COEFFICIENTS A_Q AJ A₂ A3 A₄ A₅ A₆ A₇ A₇ A₆ A₅ A₄ A3 A₂ AJ AQ

INPUT SEQUENCE X₁₅ X₁₄ X₁₃ X₁₂ X_π X₁₀ X₉ Xg X₇ X₆ X₅ X₄ X₃ X₂ X! X_Q

Because of the characteristics of the input sequence, the N= 16-point convolution can be rewritten as N/D (16/4 = 4) four-point convolutions. In particular, note that as the data input sequence is "shifted across" the coefficient sequence, for each shift the results of which are used, three additional shifts occur, both before and after, the results of which are thrown away. A relationship is therefore created between groups of coefficients that are multiplied by the same data points at different instants. On this basis, the coefficients may be grouped as {AQ, A , A₇, A3}, {A3, A , A₄, AQ} , {A₂, Ag, A5, A_j} and {A_j , A5, Ag, A₂}, the same groups as in the interpolating filter case. The convolution, however, is written as follows:

/ = /₀ + /i + /₂ + /3

= AQXQ + A₄X_j + A₇Xg + A₃X₁₂

+ A3X3 + A₇X₇ + A₄X_n + AQX₁₅ + A₂X₂ + A₆X₆ + A₅X₁₀ + A_jX₁₄

+ AJ XJ + A₅X₅ + A₆X₉ + A₂X₁₃

A generalized block diagram of a polyphase decimating filter is shown in Figure 4. The input data points are distributed between the individual filter phases s f , f _j , f₂ and f3 using a commutator. One output point of the overall polyphase inteφolating filter is formed by summing the output points of each of the individual filter phases. In the case of both interpolation and decimation, breaking the overall convolution calculation into smaller pieces allows greater computational efficiency to be obtained. However, while the initial N-point filter may be symmetric and can be easily sequenced, the individual N/D-point polyphase filters are not symmetric. This lack of symmetry requires an address sequencer of increased complexity. Furthermore, a filter may require more multiply/accumulate operations than can be accomplished by a single multiplier. The usual approach in such a situation is to add a second multiplier. This approach results in a factor of two increase in area to implement the filter.

SUMMARY OF THE INVENTION

The present invention, generally speaking, achieves a compact FIR filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize a FIR filter for performing real-time filter is therefore reduced.

BRIEF DESCRIPTION OF THE DRAWING

The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:

Figure 1 is a block diagram of a first circuit, according to the prior art, for realizing a FIR filter; Figure 2 is a block diagram of a second circuit, according to the prior art, for realizing a FIR filter;

Figure 3 is a generalized block diagram of a conventional polyphase interpolating filter; Figure 4 is a generalized block diagram of a conventional polyphase decimating filter;

Figure 5 is a block diagram of a circuit for realizing a polyphase interpolating symmetric FIR filter in accordance with the present invention;

Figure 6 is a more detailed diagram of the data storage unit of Figure 5;

Figure 7 is a timing diagram of the data storage unit of Figure 6;

Figure 8 is a block diagram of a circuit for realizing a polyphase decimating symmetric FIR filter in accordance with the present invention;

Figure 9 is a more detailed diagram of the data storage unit of Figure 8;

Figure 10 is a more detailed block diagram of the multiplier of Figure 5 and Figure 8;

Figure 11 is a more detailed block diagram of the basic cell of the multiplier of Figure 10; and

Figure 12 is a more detailed block diagram of the coefficient address generator of Figure 5 and Figure 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Considering again the previous example of a 16-point symmetric filter with the coefficients as shown in Table I above, four convolutions must be computed using four filter phases f_Q, f_j, f₂ and f3 as follows:

Table III

^Fo^: ^A3 ^A7 A₄ ^A0 ^' ^A2 ^A6 ^A5 ^Al - ^Al ^A5 ^A6 A₂ ^f3= ^Ao A₄ ^A7 ^A3

While the initial 16-point filter was symmetric and could be easily sequenced, the individual polyphase filters are not symmetric about the usual While the initial 16-point filter was symmetric and could be easily sequenced, the individual polyphase filters are not symmetric about the usual axis of symmetry, indicated by a dotted line. Symmetry of a different sort is evident, however, between different ones of the polyphase filters. Specifically, f_Q is identical to f3 reversed and f_j is identical to f₂ reversed.

Assuming, nevertheless, that there were symmetry within the individual polyphase filters about the usual axis of symmetry, the following grouping would obtain:

Table IV ef₀: (A₄,A₇) (A_Q,A₃) ef_j: (A₅,A₆) (A_{1 ?}A₂)

ef₃: (A₇,A₄) (A₃,A_Q) Clearly, symmetry cannot be made to exist where there is none. However, if the paired constants and their corresponding data points could be processed at the same time using a circuit of only marginally greater complexity, then the same speed advantage would be obtained as if the individual polyphase filters were symmetric, without any countervailing disadvantage. Such a circuit would, for example, consume the input pair (XQ,X3) and produce the result AQXQ + A3X3. Furthermore, since reverse symmetry does exist between different polyphase filters about a horizontal axis (again indicated by a dotted line), the potential exists for achieving comparable storage efficiency as if the individual polyphase filters were symmetric. Note that other pair groupings are also possible, the particular pair grouping described being chosen simply for convenience of implementation.

Arithmetic processors are known that compute in a single timestep two products and their sum or difference. For example, MacTaggart, FFT Butterfly Processor Using Distributed Arithmetic (Electronics Letters, 20 Jan. 1983, Vol. 19, No. 2, pp. 43-44, incorporated herein by reference), describes a design for an arithmetic processor that computes, one at a time, the following two output quantities: Assume for a moment that instead of computing Re(Z), the complex conjugate R(Z)* is computed, i.e.:

Re(Z)* = Re(B)Re(W) + Im(B)Im(W) Then, if B and W are assigned such that B = (XO -I- jX3) and W = (AO + jA3), the result is:

Re(Z)* = X₀A₀+X₃A₃ In this manner, the known arithmetic processor may be used as a multiplier to compute two multiply accumulate steps per clock.

The known arithmetic processor may be readily adapted to perform the foregoing computation. Considering the formation of partial products in an array multiplier, there are only four possible ways in which the separate components of the output Z, considered on a bit-by-bit basis, will be modified by the results of the multiplication operations. These possibilities are set forth in Table V: Table V

Bit k Of Input Data Points Quantity to be Added to Form kth Partial Product

X3_k xo_k

0 0 0

0 1 ^A0

1 0 ^A3

1 1 AQ + A₃

The various quantities in the right-hand column can in turn be represented as the sum or difference of only two quantities, defined as K_j (AQ + A₃)/2 and K = (AQ - A₃)/2, as follows: 10 -

Table VI

Bit k Of Input Data Points Quantity to be Added to Form kth Partial Product

X3_k xo_k

0 0 ι - ^κι

0 1 K! + K₂

1 0 ^κl ^{" κ}2

1 1 κ_{1 + Kl}

The left-hand term of each of the quantities in the right-hand column in Table V is always K_j. It can therefore be accounted for by adding 4K_j to the result at the outset. Thereafter, the formation of each successive partial product involves only the addition or subtraction of K_j or K₂. More particularly, if X0_k = 1, then K_j or K₂ is added, whereas if X0_k = 0, then K_j or K₂ is subtracted. The one of K_j or K₂ to be added or subtracted is determined by whether the two input bits of the two data points are equal or not equal. That is, if X0_k = X3_k (as determined by a simple EXOR function) then Kγ is selected, and if X0_k≠ then K₂ is selected.

A block diagram of a circuit for realizing an interpolating symmetric FIR filter in accordance with the present invention is shown in Figure 5. For simplicity and for convenience of description, control circuitry for producing a common clock signal, select signals for the multiplexer 17 and memory control signals for the coefficient address generator 13' and the memory coefficient 11 are not shown. The coefficient memory 11 may be a RAM, a ROM, a PLA, or other form of digital memory.

As compared to the circuit of Figure 1 , in the circuit of Figure 5, two constants K_j and K₂ and two data points X_j and X: are input to the multiplier circuit 15' at a time. The constants K_j and K₂ are derived from the coefficients A_j and A_k as described previously. The two data points X_j and X: are produced from a data storage unit 110. The multiplier 15' produces the result A_jX_j+AjX: during a single timestep. A sequence of such results is accumulated, beginning with the first pair of a given polyphase filter and ending with the last pair of the same polyphase filter, to produce an output point Y(n) of the filter f. Alternatively, the coefficients themselves may be stored in memory and input to the multiplier, in which case circuitry is required for calculating the constants K_j and K₂.

The data storage unit 110 is shown in greater detail in Figure 6. Because the same data points are used for each phase in the polyphase inteφolating filter, the amount of data stored is relatively small. Shift registers may therefore be used to advantage to store the data points. The data storage unit uses two shift registers, a "new data" shift register 111 and an "old data" shift register 113.

Each of the shift registers 111 and 113 has three paths through which input data may be received. The three paths are provided by two two-input multiplexers, multiplexers 115 and 117 for the new data shift register and multiplexers 119 and 121 for the old data shift register. The multiplexers 115 and 119 each have a one-clock delay associated with them. Delay stages 123 and 125, respectively, connect the outputs of the multiplexers 115 and 119 to an input of the multiplexers 117 and 121.

One input of each of the multiplexers 115 and 119 accepts data not previously stored in the respective shift registers 111 and 113. In the case of the new data shift register, this data is a new data input point. In the case of the old data shift register, this data is a data point previously stored in and output by the new data shift register at stage 2. Note that the output of each of the shift registers 111 and 113 is taken at stage 2. The remaining input of each of the multiplexers is coupled by a feedback path to one of the stages of the respective shift registers. In the case of the new data shift register, both the multiplexers 115 and 117 have inputs connected to stage 0, the head of the shift register. In the case of the old data shift register, the multiplexer 121 has an input connected to the head of the shift register. The multiplexer 119, on the other hand, has an input connected to stage 4 of the shift register. The three data paths through the new data shift register are therefore as follows: (1) from the head of the shift register back through line 125 and through input 0 of multiplexer 117; (2) from the head of the shift register back through line 127, then through input 0 of multiplexer 115, and through the delay stage 123 and input 1 of multiplexer 117; and (3) from the new data input D_{jj j} through input 1 of the multiplexer 115, and through the delay stage 123 and input 1 of multiplexer 117. Path (1) is selected when the control signals Advance and Pushl are both 0, path (2) is selected when only the Advance signal is 1, and path (3) is selected when the control signal Pushl is 1 and, either at the same time or subsequently, the control signal Advance is 1.

Similarly the three data paths through the new data shift register are as follows: (1) from the head of the shift register back through line 129 and through input 0 of multiplexer 121; (2) from the stage 4 of the shift register back through line 131 , then through input 0 of multiplexer 119, and through the delay stage 125 and input 1 of multiplexer 121; and (3) from the stage 2 output of the new data shift register back through line 133, through input 1 of the multiplexer 115, and through the delay stage 125 and input 1 of multiplexer 121. Path (1) is selected when the control signals Advance and Push2 are both 0, path (2) is selected when only the Advance signal is 1, and path (3) is selected when the control signal Push2 is 1 and, either at the same time or subsequently, the control signal Advance is 1.

During computation of a single output point, the contents of both shift registers 11 and 113 recirculate in the normal fashion. Hence XQ and X_n are presented to the multiplier, followed by X_j and X_n_ι, followed by X₂ and X_n_ ₂, etc. At length, X_n/ and

₁ are presented to the multiplier. These data points are recirculated. In the meantime, however, a new data point ^xn+ l ^W* ^{nave Deen n}P^{ut t0 the new} ^^{ata sn}^^{1 re}S^^ster behind X(_n/2)+ ι ^so as to appear next at the output stage 2. The data point X_(n/2₎ + 1 ^wiU ^nave been input to the old data shift register, and the data point XQ discarded. The data points X_j and X_(n/2₎ + i ^{are tnen} presented to the multiplier, commencing calculation of a new output point. Operation proceeds in this manner. The data storage unit of Figure 6 is designed for an 8X, two-channel (I, Q) inteφolating filter having a 12-point filter kernel. Referring to the timing diagram of Figure 7, an illustration is provided of circuit timing beginning with calculation of a first output point and ending after a first portion of calculation of a second output point. The signals in the upper portion of Figure 7 are shown again in the bottom portion of Figure 7 beginning at a later time.

Beginning at time t_Q, an input data point 11 _j is assumed to be stored in the output stage, stage 2, of the new data shift register, producing the data point 111 as the output signal NEW DQ J . Succeeding stages 3-11 of the new data shift register are assumed to store the input data points 11Q, 10J, 10Q, ...7Q. Finally, stages 0 and 1 of the new data shift register are assumed to store input data points 6_j and 6Q. Similarly, at time t_Q, an input data point 0_j is assumed to be stored in the output stage, stage 2, of the old data shift register, producing the data point 0_j as the output signal OLD_DQ_TJJ. Succeeding stages 3-11 of the old data shift register are assumed to store the input data points 0_Q, l_j, 1Q,...4Q. Finally, stages 0 and 1 of the old data shift register are assumed to store input data points 5_j and 5Q.

Between time t_Q and time t_j , the new input data points 12 and 12Q appear on the input line NEW D_jj^. The signal Pushl is high, while the signal Advance is low. Data is transferred on every clock edge. Therefore, at time t_j , the data point 12_j will have propagated through the delay of the multiplexer 115 and the additional delay stage 123 to appear at input 1 of the multiplexer 117, the data point 12Q will have propagated through the delay of the multiplexer 115 to appear at the input of the delay stage 123, the data point 6 previously stored in stage 0 will have been circulated through to stage 10, and the data point 6Q previously stored in stage 1 will have been circulated through to stage 11. As for the old data shift register, during the same period of time, the data point 5 previously stored in stage 0 will have been circulated through to stage 10, and the data point 5Q previously stored in stage 1 will have been circulated through to stage 11. During this period, data points are output as follows: {0τ, l lτ}, {0_Q, 11_Q}. During the period t_j to t^, the Advance signal only is active high. Data is therefore transferred through data path (2), line 127 in the case of the new data shift register and line 131 in the case of the old data shift register. Because the line 127 connects to the head of the new data shift register, data remains in order. Considering the delay elements at the end of each shift register as forming the equivalent of two extra stages 12 and 13, data in the new data shift register appears in the sequence (beginning with stage 0) 7_j, 7Q, 6J, 6Q, 12J, 12Q, ll_j, 11Q, 10 , 10Q, 9 , 9Q, 8_T, 8Q. The new data points 12_j, 12Q have been advanced toward the output stage, stage 2, in preparation for beginning calculation of a new data output point. During this period, data points are output as follows: {l_j, 10_τ}, { 1Q, 10Q},{2J, 9_T}, {2Q, 9Q} , {3J,

*ύ^> Q. 8Q)' ^{41' ⁷Q^}' ^{4Q' ⁷Q

The line 131 , however, connects to stage 4 of the old data shift register.

Data in the old data shift register therefore appears in the sequence (beginning with stage 0) 4 , 4Q, 5J, 5Q, l , 1Q, 2J, 2Q, 3J, 3Q, 4J, 4Q, 5J, 5Q.

During the time period t to t^, Advance remains active high and Push2 also becomes active high. Data is therefore transferred through data path (3) of the old data shift register. Pushl , however, remains low such that data continues to be transferred through data path (2) of the new data shift register. Data points are output as follows: {5_j, 6_j}, {5Q, 6Q}. Data in the new data shift register appears in the sequence (beginning with stage 0) 6 , 6Q, 12J, 12Q, l l_j, 11Q, 101, 10Q, 9J, 9Q, 8J, 8Q, 7J, 7Q. Data in the old data shift register appears in the sequence (beginning with stage 0) 5 , 5Q, l_j, 1Q, 2J, 2Q_> 3J, 3Q, 4J, 4Q, 5J, 5Q, 6 , 6Q, the latter two data points having been pushed from stage 2 of the new data shift register into the delay pipeline of the old data shift register. Calculation of a new output data point is now ready to begin by outputting {l_j, 12_j}, { 1Q, 12Q}, etc. Data is advanced in both shift registers for one more cycle (from tg to t₇) to move the data points 7_j, 7Q and 6τ, 6 from the delay pipelines into the shift registers proper. Once the foregoing output data sequence has been produced once, it is repeated seven additional times for a total of eight times, once for each phase of the 8X interpolating filter. The data sequence is repeated for the final time during the period t₄g to t^ . Also during this time period, new input data points 13_j and 13Q are advanced in preparation for calculating a new output data point. A block diagram of a circuit for realizing a decimating symmetric FIR filter in accordance with the present invention is shown in Figure 8. Again, for simplicity and for convenience of description, control circuitry for producing a common clock signal, select signals for the multiplexer 17 and memory control signals for the coefficient address generator 13' and the memory coefficient 11 are not shown. The coefficient memory 11 may be a RAM, a ROM, a PLA, or other form of digital memory.

As compared to the circuit of Figure 5, in the circuit of Figure 8, there is provided an additional accumulator 120 including an adder 117, a multiplexer 116 and an accumulator register 119. Recall that, whereas in the case of an inteφolating filter the filter output is one of the phase outputs, in the case of a decimating filter, the filter output is the sum of the phase outputs. Accordingly, the different phase outputs f_(n) are accumulated in the accumulator 120 to form the filter output Y(n).

The data storage unit 111 is shown in greater detail in Figure 9. A similar approach is used as in the case of the inteφolating filter. However, since in the case of a decimating filter different data is stored for each filter phase, two random access memories 211 and 213 are used instead of the two shift registers 111 and 113 of the data storage unit for the inteφolating filter. Because of the random access nature of the memories (as compared to shift registers), the implementation becomes relatively simple. A multiplexer 215 at the data input of the new data queue 211 is used to select between either a new input data point or a data point previously output from the queue. A multiplexer 219 at the data input of the old data queue 231 is used to select between either an input data point from the new data queue or a data point previously output from the old data queue. Write operations are delayed by two clocks using delay elements 231, 233 and 235 to ensure that data is not overwritten before it gets read out.

In an exemplary embodiment, the data storage unit is used to realize a two-channel, 8X symmetric decimating filter. Corresponding I and Q data is stored side-by-side at a single memory address. Half of the data is stored in the new data queue and half of the data is stored in the old data queue. Therefore, to calculate a 96-point filter for example, 48 address locations are required in each memory. The 96-point filter may be composed into eight 12- point filter phases, six data points of which are stored in the new data queue and six data points of which are stored in the old data queue. The 48 address locations of each memory are therefore grouped in groups of six, 0-5, 6-11, etc. A free-running mod-47 counter (not shown) is used to repeatedly count from 0 to 47. A coefficient address generator (also not shown) is used to read out the coefficients of each respective phase of the eight filter phases once during one cycle of the data address counter from 0 to 47.

Table IV illustrates operation of the data storage unit from when calculation of one output data point has been completed to when calculation of a next output data point has begun.

Table VII

The multiplier 15' is shown in greater detail in Figure 10. Preferably, the multiplier is realized in the form of an integrated circuit, or IC chip, and is based on a two-dimensionally pipelined configuration which allows the constant throughput of parallel data.

The multiplier incoφorates an array 20 of basic cells 21, each of which includes a two-bit-wide shift register and a full adder. The basic cells are interconnected as indicated with carry bits being propagated directly downward to a next cell and sum bits being propagated downward and one cell to the right. The input words K_j and K2 are shifted separately from "top- to-bottom" of the multiplier through the array of full adders. A data select on the two input words K_j and K2 is performed at the inputs to each full adder under the control of an Exclusive OR or Exclusive NOR block 23 which operates on the separate bits of X_j and X: as described previously in relation to Table VI. The word selected (i.e., either K_j or K₂) at each full adder is then either added to, or subtracted from, the accumulated partial product as determined by the appropriate bit of X:. A "time wedge" 23 (collection of pipeline registers) is connected to the X_j, X: input port to ensure that a constant data throughput can be maintained in the pipeline.

Referring to Figure 11 , a basic cell 21 is realized using a combination of inverters, buffers, and a full adder/subtracter 35. Data inputs to the cell include K_j and K₂, a sum input signal (sum in), and a carry input signal (carry in), while data outputs from the cell include a sum output signal (sum out), and a carry input signal (carry out). In the case of all but the first row of cells, sum in and carry in are connected to sum out from one cell in the preceding row and carry out from another cell in the preceding row. In the case of the first row of cells, sum in and carry in are connected to K_j , shifted so as to accomplish a multiplication by four. This array initialization is accomplished within block 27 of Figure 10.

Control inputs to the cell include clock in and clock out inputs, a data select input, an add/subtract input.

In operation, the data select line is set in accordance with the bits of X_j and X: so as select the appropriate one of K_j and K₂. When data select is true, K_j is selected, and when data select is false, K₂ is selected. The inputs are then clocked by the input clock and driven by the input buffer 31. Meanwhile, add/sub will have been set in accordance with the appropriate bit of X_j so as to cause the circuit 35 to operate as either an adder or subtracter. Block 34 performs this function. Once add/sub has been set and the inputs have been driven, the remainder of circuit 35 then computes the sum or difference. When the output clock is activated, sum out and carry out are driven with the results of the computation by the buffer 33. As for the outputs K_j and K₂, the buffers 31 and 33 realize the two-bit shift register mentioned previously, whereby K_j and K are shifted from stage to stage.

Once the last row of cells has performed its addition or subtraction, a final summation is performed in block 29 of Figure 10 to produce the final output. Note that although operation has been described in terms of multiplication/accumulation with respect to one data point pair and its correspond coefficient pair, because of the fully pipelined nature of the circuit of Figure 10, once the pipeline has been filled, the result of a different multiplication/accumulation operation is produced each clock cycle.

Referring again to Table IV, as previously noted, reverse symmetry exists between different polyphase filters about the horizontal axis (indicated by the dotted line). In accordance with one embodiment of the invention, this property is exploited in order to achieve comparable storage efficiency as if the individual polyphase filters were symmetric. Considering again the example of calculating ReZ) = XQAQ + X3A3, if the input operands X3 and XQ are interchanged before being applied to the multiplier, then the multiplier's output will instead be Re(Z) = X0A3 + X3A_Q. This is precisely the result required when calculating the polyphase filter ef- . More generally, Table IV can be rewritten in the following form: Table VIII efO: (A4,A7) (A0,A3) ef l: (A5.A6) (A1,A2) ef2: ^5^A6)^ (AT Ϊ)"** ef3: (A4,A7 » (A0,A3)«*

The subscript "**" in the lower half of the table denotes that the input operands are reversed as compared to their order during the calculations represented in the upper half of the table. In this manner, it is possible to achieve the effect of accessing a filter's coefficients in the reverse order, which is required for reducing the size of the coefficient memory storage.

In addition to achieving the effect of accessing a filter's coefficients in the reverse order within a pair, the coefficients pairs in the lower half of the table must be accessed in the reverse phase order from the coefficients pairs in the upper half of the table. For example, if the coefficients pairs (A_Q,A3)__nQ, (^A4'^A7)phO' (^Al'^A2)phl ^an<^ ^^A5'^A6^phl ^{ere store}^ ^at memory addresses 0, 1 , 2, and 3, respectively and were accessed in that order to calculate phases CVQ and ef _j, in order to thereafter calculate phases ef 3 and ef ₄, the same coefficients pairs must be accessed in the reverse phase order, i.e.,

(^Al'^A2>phl > (^A5'^A6)phl' <^A0'^A3 h0 ^and (^A4'^A7 hO' corresponding to memory addresses 2, 3, 0 and 1.

An address sequencer for producing the foregoing sequencing may consist of two counter, a modulo-m counter, where m is the number of coefficients pairs in a polyphase filter branch, and a binary counter.

Referring to Figure 12, the modulo-m counter 51 is clocked at the computer rate of the multiplier. The binary counter 53 counts from 0 to n._j, where n is the number of filter branches, and is clocked whenever the modulo- m counter overflows. The binary counter 53 therefore progressively addresses sections of memory in which sets of coefficient pairs for the various filter branch are stored, and the modulo-m counter 51 progressively addresses the particular coefficient pairs within each set. The MSB of the binary counter 53 is not used to address the coefficient memory but is used as a control signal. That is, when the MSB of the binary counter 53 is asserted, it indicates that the lower half of the coefficient table is to then be accessed. In order to access the lower half of the coefficient table in reverse phase order, the remaining bits of the binary counter 53 are XORed with the MSB and are thereby inverted. The MSB is also input to the input pad and multiplex block 24 in Figure 10 as a control signal MXCTL. This signal is used to reverse the order of the input operands.

It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.

Claims

What is claimed is:

1. A method of calculating output data points of a polyphase Finite Impulse Response filter using a complex multiplier, comprising the steps of: a) applying to the complex multiplier a pair of constants K ^ and K related to a pair of filter coefficients A_j and A:; b) applying to the complex multiplier a pair of input operands X_j and

c) operating the complex multiplier to form the quantity A_jX_j +

A_jXj.

2. The method of claim 1 wherein K_j = (A_j + A:)/2 and K₂ = (A_j

3. The method of Claim 2, comprising the further step of: d) repeating step a) through step c) with different index values i and

J-

4. The method of Claim 3, wherein step b) comprises applying X_j to a fifirrsstt ooppeerraanndd iinnppuutt ooff tthhee ccoommpplleexx mmuullttiipplier and applying X: to a second operand input of the complex multiplier.

5. The method of Claim 4, comprising the further step of: e) repeating step a) through step c) with the same index values i and j as during a previous iteration of step a) through step c).

6. The method of Claim 5, wherein step e) comprises applying X_j to said sseeccoonndd ooppeerraanndd iinnppuutt ooff tthhee ccoommpplleexx muultiplier and applying X: to said first operand input of the complex multiplier.

7. The method of Claim 3, comprising: dl) repeating step a) through step d) for each of a plurality of sets of index value pairs.

8. The method of Claim 7, wherein step b) comprises applying X_j to a first operand input of the complex multiplier and applying X: to a second operand input of the complex multiplier.

9. The method of Claim 8, comprising the further step of: e) repeating step a) through step d) for each of a plurality of sets of index value pairs, with the same index values i and j as during step dl)).

10. The method of Claim 9, wherein step e) comprises applying X_j to said s seeccoonndd ooppeerraanndd iinnppuutt ooff tthhee ccoommpplleexx muultiplier and applying X: to said first operand input of the complex multiplier.

11. The method of Claim 10, wherein said plurality is a number N/2 where N is an even number, step dl)) comprising repeating step a) through step d) first for a set S_j of index value pairs and last for a set S_j^ of index value pairs, and step e) comprising repeating step a) through step d) first for a set ϊ-N/2 of index value pairs and last for a set S_j of index value pairs.

12. A apparatus for calculating output data points of a digital filter comprising: a memory storing a plurality of filter-coefficient-related constants and for storing a plurality of input data points; an address generator connected to said memory; and a complex multiplier/accumulator connected to said memory and having a first input port, a second input port and an output port, said complex multiplier/accumulator receiving at said first input port signals representing a pair of constants related to filter coefficients A_j and A_j, receiving at said second input port signals representing a pair of input data points X_j and X:, and producing at said output port signals representing the quantity A_jX_j + A_jX_j.

13. The apparatus of Claim 12, wherein said complex multiplier/accumulator comprises an array of interconnected basic cells arrayed in rows and columns, each row of said basic cells forming a different intermediate multiply/accumulate result.

14. The apparatus of Claim 13, wherein said complex multiplier/accumulator further comprises a control circuit for generating for each row of said basic cells a select signal in accordance with corresponding single bits of X_j and X: .

15. The apparatus of Claim 14, wherein said control circuit further generates for each row of said basic cells a add/subtract signal in accordance with a corresponding single bit of one of X_j and X:.

16. The apparatus of Claim 15, wherein each of said basic cells comprises a multiplexer responsive to said select signal for a row of said basic cell for selecting a bit from one of said pair of constants related to filter coefficients A_j and A:, and a full adder/subtracter receiving a sum input signal and a carry input signal from adjacent basic cells and responsive to said add/subtract signal for said row of said basic cell for adding or subtracting said bit to or from a radix-2 quantity represented by said sum input signal and said carry input signal to produce a sum output signal and a carry output signal.

17. The apparatus of Claim 12, wherein said address generator generates a mux control signal and said complex multiplier/accumulator comprises a multiplexer responsive to said mux control signal for selectively interchanging at said second input port said signals representing said pair of input data points X_j and Xj.

18. The apparatus of Claim 17, wherein said address generator comprises: first means operating at a first rate Rl for repeatedly generating a symmetric sequence of binary numbers HQ, H₂, ..., H_N__j where H_q = H_{j j}__j_ ,; second means connected to said first means and operating at a second rate R = MR_j for repeatedly generating a monotonic sequence of binary numbers LQ, L^, ..., L_M __j where M is an integer; and third means connected to said first and second means for forming a concatenation HL of one of said symmetric sequence of binary numbers and one of said monotonic sequence of binary numbers as a address for said memory.

19. The apparatus of Claim 18, wherein said first means comprises a binary counter and a plurality of EX OR gates each connected to different output bits of said binary counter and each connected also to a same output bit of said binary counter of greater significance than said different output bits.

20. The apparatus of Claim 19, wherein said second means comprises a modulo-M counter clocked by a clock signal and producing an overflow signal, said overflow signal being connected to clock said binary counter.