WO1996025708A1

WO1996025708A1 - Arrangement for serial data transmission

Info

Publication number: WO1996025708A1
Application number: PCT/SE1996/000183
Authority: WO
Inventors: Stig Borg; Erik Johnsson; Henrik MALMSTRÖM
Original assignee: Essnet Ab
Priority date: 1995-02-13
Filing date: 1996-02-13
Publication date: 1996-08-22
Also published as: SE9500525D0; AU4735996A; SE9500525L

Abstract

In an arrangement for serial data transmission between a first data processing unit (2), arranged for sending parallel data, and a second data processing unit (4), arranged for receiving parallel data, the parallel data is converted to serial form and is then converted back to parallel form, a status signal being transmitted from the second data processing unit (4) to the first data processing unit (2) and indicating whether the said second data processing unit (4) is in data-receive status or not. The data transmission arrangement comprises a first interface unit (6) which is arranged for converting parallel data to serial data and for control signal transmission, and a second interface unit (8) which can be connected to the second data processing unit (4) and which is arranged for converting serial data to parallel data and for control signal transmission. The two said interface units (6) and (8) can be connected to one another by means of a signal transmission member (22) arranged for transmitting data signals and control signals. The status signal can be transmitted in real time to a data processor in the first data processing unit (2), the transmission of data being adapted according to the status of the second data processing unit (4).

Description

Apparatus fQr serial data transmission

The present invention relates to an arrangement for serial data transmission in accordance with the preamble of Patent Claim 1, and to an information presentation arrangement in accordance with Patent Claim 13, which incorporates the arrangement according to the invention and the method according to the invention.

Background to the invention

For data transmission from a main unit in a data processing system to a peripheral unit which requires parallel data input, use is normally made of parallel data transmission via a cable system comprising leads for a number of data bits and for control signals and different voltage levels. In one example of such an arrangement in accordance with the prior art, information is to be presented as an image on a display unit of the LCD type. The main unit then typically comprises a data processor, a memory unit, an application program which is executed with the aid of the processor, an intermediate storage memory in the form of an image memory for temporary storage of the information which is to be presented on the LCD display, and an input/output unit for parallel input and output of data. A display unit of standard type additionally comprises a presentation panel, a number of drive circuits for LCD segments included in the panel, a control unit which, by means of the drive circuits, controls the data output to the presentation panel, and an input/output unit which corresponds to that which is located in the main unit. The main unit and the display unit are coupled together with a cable normally comprising eight data leads for transmission of an 8-bit data word, a number of voltage leads for supply voltage, different voltage levels and earthing, and a number of control signal leads for transmission of control signals such as clock signal, resetting signal, register selector, read/write signal, and enable signal. In total, these leads can, for example, be seventeen in number, and normally not less than fourteen, depending on what functions of the display unit are to be used.

During normal operation, the application program is used to compile the information which in accordance with the above is to be presented as an image on the LCD screen, a representation of the image is stored in the image memory and is then transmitted by means of the processor to the control unit of the display unit, which control unit in turn effects the outputting of the image information to the presentation panel. Such a display unit requires a relatively long time between updates and reading-in of data, and for this reason one of the data bits is arranged for sending status information in the form of a clear signal back to the processor of the main unit, which clear signal indicates that the display unit is ready to receive a new data word. Thus, in data transmission, the clear signal data bit is read off routinely and with regular intervals, and at the clear signal a data word is read out to the input/output unit and is transmitted in parallel form to the display unit. The routine read-out of the clear signal thereafter continues until a new data word can be read off, and the procedure is repeated until all the information which is to be transmitted has been read out from the image memory.

Problems of the prior art

In many applications it is desirable to be able to place the peripheral unit at a certain distance from the main unit. The cable which is required in the prior art for the coupling between the units is cumbersome on account of the many leads, difficult to bend and takes up a great deal of space. In those cases where it is desired to place the peripheral unit far from the main unit, at a distance of the order of several metres to tens of metres, there is increased risk of data loss and electro- maernetic interference (EMI) . In the case of some types of peripheral units, for example slow LCD screens, and of data transmission over long distances, an additional aim is to decrease the transmission speed, which is difficult in the case of parallel data transmission in accordance with the prior art and additionally requires costly compensation circuits in the receiving peripheral unit. A well-known alternative to parallel data transmission is serial data transmission, but in applications with serial data transmission in accordance with the prior art there are special problems due to the fact that during the data transmission it is not easy to read the status of the peripheral unit back to the main unit. In the example given above, the data processor in the main unit, in the case of serial transmission, would need to receive a signal indicating that the control circuit in the display unit is ready to receive data, and this cannot be done without difficulty in the prior art. In the case of data transmission with constant interrogation, in accordance with the prior art described above, the processor in the main unit is severely loaded and has to be dimensioned accordingly, with attendant higher costs as a result. All in all, the prior art necessitates the use of an inconveniently large number of components and a great deal of cabling material, which results in the high cost of such an arrangement.

Objects and advantages of the invention

A primary object of the invention is to make available an arrangement for data transmission between a first data processing unit and a second data processing unit of the above-mentioned type, in which arrangement the costly and space-consuming cabling material and electronics components have been reduced in quantity and number, by means of eliminating the need for a number of leads, an intermediate memory and various compensation circuits. Another object is to make available an arrangement for this kind of data transmission over long distances, with reduced risk of data loss and inter¬ ference. It is also an object of the present invention to make available an arrangement for serial data trans- mission between an essentially transmitting first data processing unit and an essentially receiving second data processing unit, in particular a receiving second data processing unit which requires parallel data input, which arrangement and which method permit, during the data transmission, reading back of the status of the receiving data processing unit. Yet another object of the invention is to make available an arrangement which, on connecting up of a receiving unit, and as a function of the type of unit, is automatically switched between serial trans¬ mission according to the invention and serial trans¬ mission according to the prior art, in order thereby to increase the flexibility and usability of the arrangement according to the invention. Particular advantages are that the arrangement according to the invention requires simpler logic circuits in the receiver unit than is the case in the prior art, that less processor capacity is required for the data transmission because a hardware-dependent signal [lacuna] the status of the receiving unit, and that by this means an interrupt-driven data transmission has been achieved, which provides for a more efficient utilization of processor and other components involved. It is also advantageous that the data transmission speed is adapted automatically to the characteristics of the receiving unit and that the said processor does not need to have knowledge of the serial data transmission protocol, and instead can read data to and from an existing parallel input/output unit. The above-mentioned objects and advantages are achieved by means of a data transmission arrangement of the abovementioned type and an information presentation unit which have the features specified in Patent Claims 1 and 13. Further advantageous developments and embodiments are specified in the associated subclaims.

Figures

The invention will now be described in greater detail on the basis of an illustrative embodiment and with reference to the attached figures. Figure 1 shows a circuit diagram of an embodiment of the data transmission arrangement according to the invention, coupled between two data processing units; Figure 2 shows a circuit diagram of an illustrative embodiment of a first inter¬ face unit according to the invention; Figure 3 shows a circuit diagram of an illustrative embodiment of a second interface unit according to the invention; and Figure 4 shows a circuit diagram of the signal paths according to the invention.

Description of an illustrative embodiment of the invention

Figure 1 shows a circuit diagram of an embodiment of a data transmission arrangement 1 according to the invention, which arrangement is coupled, in the figure, between a first data processing unit 2 and a second data processing unit 4. The first data processing unit 2 can be, for example, a cash register apparatus or a lottery terminal, and the second data processing unit 4 can be, for example, a data presentation arrangement such as an LCD screen, a cathode-ray screen, a screen of another type, or some other type of peripheral unit operating in parallel form. The first data processing unit 2 comprises a microprocessor 26, a memory unit 28, which can be a RAM unit for example, a power supply unit 29 arranged for supplying power to the various components in the arrangements and for generating voltages of different potentials, and it can also comprise a program sequence in the form of an application program which can be executed with the aid of the processor and the memory unit. The application program is in this example arranged to generate or compile a representation of an image which is to be presented on the LCD screen in the second data processing unit. The first data processing unit also comprises an address bus and/or a data bus 25 and signal and/or voltage leads 23 via which the microprocessor and the memory unit are operatively connected to one another. The address bus, the data bus and the signal leads are also connected to a parallel data input/output unit 30 which is included in the said data processing unit and which is used for the parallel input and output, respectively, of data and control signals. In this document, the expression "control signals" also covers the said voltages, which can thus be transmitted via control signal leads.

The second data processing unit 4, which is thus an LCD screen in this example, likewise comprises a parallel data input/output unit 31 arranged for parallel input and output, respectively, of data and control signals. There is also a presentation panel 44 containing LCD segments, a number of drive circuits 42 connected to the segments, a control unit 38 for controlling the function of the LCD screen, and a signal and/or voltage transmission member 40. The said units and the members are connected to one another via leads and data buses, and are connected to the said parallel data input/output unit 31. The data transmission arrangement 1 which, in the figure, has been drawn within a broken line, comprises a first interface unit 6 comprising a parallel input/output unit 10 which is connected via an address bus, a data bus and control signal lines to a parallel-to-serial data conversion member 12, and to a first control signal transmission member 14, which are in turn connected to a first serial data input/output unit 15. The arrangement 1 furthermore comprises a second interface unit 8 which in turn comprises a second serial data input/output unit 16. The said serial data input/output unit 16 is connected to a serial-to-parallel data conversion member 18 and a second control signal transmission member 20, which are in turn connected to a parallel data input/output unit 24. The two interface units 6 and 8 can be connected to one another with the aid of a signal transmission member 22 which can comprise, for example, an electrical or optical lead and/or members for wireless signal transmission. As the figure shows, the interface units 6 and 8 can also be connected to respective data processing units 2 and 4 directly by means of leads or via contact devices included in the said input/output units.

Also shown diagrammatically, and on a larger scale, are the signals and signal paths S1-S8 which, according to an illustrative embodiment of the invention, are to be transmitted and be arranged between the data processing arrangements 2 and 4 via the data transmission arrangement 1 and the signal transmission member 22. SI, S2 and S3 are voltage signals with different potentials, and in this illustrative example SI = -15 V, S2 = +12 V, and S3 = 0, i.e. earth. These voltage levels can of course have other voltage values, and they can also be routed along a path other than by way of the data transmission arrangement 1. The signal path S4 is arranged for transmission of serial data, for example one data word or one byte at a time consisting of 8 data bits dO - d7, from the first data processing unit 2 to the second data processing unit 4. S5 is arranged for trans- mission of a status signal from the second data processing unit 4 to the first data processing unit 2, and which signal in this example indicates that the LCD screen is ready to receive a data word. S6 is an enable signal for generating a signal-receive status in units on the receiving side of the data transmission arrangement. S7 is a read-in signal (load) for reading-in signals and data in the various units, and S8 is a clock signal for synchronizing the operations of the various units.

Transmission of information which has been compiled by the application program 27, and which has been represented in the memory unit 28, now proceeds by means of the microprocessor 26 reading out the information from the memory unit and transmitting it as a sequence of data words or bytes to the LCD screen, and more specifically a data word at a time, as a function of the said status signal S5 which is transmitted from the LCD screen to the microprocessor via the data trans¬ mission arrangement. In one illustrative example, the method for transmission according to the invention comprises the following steps:

1. A status inquiry signal, for example in the form of four data bits, is sent from the microprocessor and is transmitted via the data signal line S4 to the control unit 38 of the second data processing unit 4.

2. A status signal is sent back from the control unit 38 to the microprocessor 26 via S5, which signal is read off by the microprocessor at one of the bits on the data bus 25, and if the status signal S5 indicates that the data processing unit 4 is in data-receive status, the procedure continues to the next step, otherwise step 1 is repeated.

3. Thus, if the receiving data processing unit 4 is in data-receive status, a data word is read out with the aid of the microprocessor from the memory unit 28 to the data bus 25 and is transmitted to the parallel-to-serial data conversion member 12.

4. The data word is converted by means of the said parallel-to-serial data conversion member 12 into serial form and is sent via S4 to the receiving, second interface unit 8.

5. The data word is read in to the serial-to-parallel data conversion member 18 and is converted to parallel form. 6. A read-out signal S7 is transmitted from the micro¬ processor to the second interface unit 8 and, as a function of the said read-out signal S7, data is read out in parallel form to the control unit 38 via the parallel data input/output units 24 and 31 and via a data bus included in the second data processing unit 4.

7. An enable signal S6 is transmitted from the micro¬ processor, which signal effects activation of the presentation of the transmitted data word on the display in the data processing unit 2. This sequence is then repeated until all the information which is to be presented has been transmitted and upon updating of the information which is to be presented.

Figure 2 shows an embodiment of a first interface unit 6 which comprises a parallel data input/output unit 10 which is coupled to a programmable control unit 46 via an address bus 21, a data bus 25 and a control signal line 19. The programmable control unit 46 is in turn connected to a first serial data input/output unit 15 via signal leads, a data output buffer 63, and an anti-EMI circuit 64. The control unit 46 is also connected via a compensation circuit 47 to a further serial data input/output unit 17. Here too a data output buffer and an anti-EMI circuit can be coupled in. The programmable control unit 46 comprises parallel-to-serial data conversion members and control signal transmission members and is arranged for serial output of parallel- input data. This embodiment of the interface unit 6 is arranged to convert and transmit data as has been mentioned above. However, it is also arranged to transmit data via the further serial data input/output unit 17 in accordance with a second transmission protocol and a second serial interface which can, for example, be of the I2C standard already known per se. However, with I2C interfaces, for example, and other known serial interfaces, the data transmission speed cannot be adapted as is required in an application where a relatively large amount of information is to be transmitted. A receiving unit of this kind could, for example, be a large presentation unit for presentation of a relatively large amount of information, such as an LCD screen with 128 x 240 pixels. Nor can status signals for the receiving unit be transmitted in real time to the sending unit, which is possible with data transmission according to the invention. However, the supplementary data transmission interface can be used, for example, for parallel transmission of a small amount of information to a supplementary peripheral unit. The interface arrangement 6 of the serial data input/output unit 17 is in actual fact arranged to be automatically switched between the two said transmission modes by means of the compensation circuit 47. On connection of a serial interface, for example a I2C bus interface, to the serial data input/output unit 17, a switching signal is transmitted to the microprocessor via the said data bus. The same switching signal or another switching signal also effects switching of the compensation circuit 47 so that serial data output from the control member 46 is adapted for transmission in accordance with the connected interface. In the address data bus it is also possible to arrange at least one data buffer which is preferably unidirectional, and preferably reversible data buffers can be arranged at the data bus 60. Current amplifiers 65 can additionally be arranged on the various signal leads.

Figure 3 shows an embodiment of the second interface unit 8, which comprises a serial data input/output unit 16 which is connected to a shift register 48. Serially transmitted data and signals are shifted into the shift register and are then transmitted to a parallel register 50. The data thus converted from serial to parallel form is then transmitted from the parallel register 50 to a parallel data input/output unit 24. The data output buffer 52 is also coupled to the parallel data input/output unit 24. The interface unit 8 also comprises voltage leads 54 and control signal leads 56 which are coupled between the serial data input/output unit 16 and the parallel data input/output unit 24, and it can also comprise, like the first interface unit 6 described above, current amplifiers and further data buffers. The members and functions described can also be included in, and can be realized by means of, a programmable control member of the type which has been described in connection with Figure 2.

Figure 4 shows in principle the signal paths in accordance with an illustrative embodiment of the invention, the arrows indicating the direction of the signals. SI, S2 and S3 are fed into the first interface unit 6 and are led via first control signal transmission members 14 to the second interface unit 8, and are then output via second control signal transmission members 20 from the said second interface unit 8. A data word for example, containing the data bits dO - d7, is fed in parallel form to the parallel-to-serial data conversion member 12 and is then led in serial form onwards via the signal line S4 to the serial-to-parallel data conversion member 18, and then output from the second interface unit 8 in the form of a data word which is now once again in parallel form. The status signal S5 is input to the second interface unit 8 and is transmitted via the second control signal transmission member 20 to the first interface unit 6, where it is led onwards via the control signal transmission member 14 to one of the data bits on the parallel data bus, for example d7. The control signals S6, S7 and S8 are input to the first interface unit 6 and transmitted via the control signal trans¬ mission member 14 to the control signal transmission member 20 of the second interface unit 8, and then once again output from the second interface unit. In different embodiments, the various signals can be led directly through the interface units or via data buffers, current amplifiers or other compensation circuits. In the embodiment which has been taken as an example above, it has thus been possible, by means of the invention, to make available a data transmission arrangement for transmitting data between two data processing units operating in parallel form, and the transmission of data and control signals has been reduced to eight signals and signal paths. It is of course possible within the scope of the invention to design the data transmission arrangement in other ways. For example, the second, essentially receiving data processing unit can be provided with its own current and voltage supply, which would further reduce the number of signal leads. Other component designs and the use of data transmission between different types of data processing units are also possible. In addition, the two interface units 6 and 8 can be arranged for corresponding data transmission in the other direction too.

Claims

Patent Claims

1. Arrangement for serial data transmission between a first data processing unit (2) , arranged for sending parallel data, and a second data processing unit (4) , arranged for receiving parallel data, characterized in that it comprises a first interface unit (6) which can be connected to the first data processing unit (2) and which is arranged for converting parallel data to serial data and for control signal transmission; a second interface unit (8) which can be connected to the second data processing unit (4) and which is arranged for converting serial data to parallel data and for control signal transmission; and in that the two said interface units

(6, 8) can be connected to one another by means of a signal transmission member (22) arranged for transmitting data signals and control signals.

2. Data transmission arrangement according to Claim 1, characterized in that the first interface unit (6) comprises a first parallel data input/output unit (10) arranged for connection to the first data processing unit (2) and for inputting and outputting parallel data and at least one control signal; a parallel-to-serial data conversion member (12) connected to the said parallel data input/output unit (10) and arranged for converting parallel data to serial data; a first control signal transmission member (14) connected to the said parallel data input/output unit (10) and arranged for transmitting a control signal; and a first serial input/output unit (15) which is connected to the said parallel-to-serial data conversion member (12) and the said control signal transmission member (14) and is arranged for inputting and outputting serial data and at least one control signal, and is arranged for connection to the said signal transmission member (22) .

3. Data transmission arrangement according to Claim 1 or Claim 2, characterized in that the second interface unit (8) comprises a serial data input/output unit (16) arranged for connection to the said signal transmission member (22) and for inputting and outputting serial data and at least one control signal; a serial-to-parallel data conversion member (18) connected to the said serial data input/output unit (16) and arranged for converting parallel data to serial data; a second control signal transmission member (20) connected to the said serial data input/output unit (16) and arranged for transmitting a control signal; and a second parallel data input/output unit (24) connected to the said serial-to-parallel data conversion member (18) and to the said control signal transmission member (20) and arranged for inputting and outputting parallel data and at least one control signal.

4. Data transmission arrangement according to any one of the preceding claims, characterized in that it is arranged to convert and serially transmit, from the data- sending, first data processing unit (2) to the data- receiving, second data processing unit (4) , a data word which has been input in parallel form at the first parallel data input/output unit (10) ; to transmit control signals which have been input at the said first parallel data input/output unit (10) , including a clock signal for synchronizing the operations and signal handling of the members included in the arrangement and in the two said data processing members, an enable signal for setting a data-receive status in the members on the receiving side of the data transmission arrangement, and a read-out signal for reading out a data word from the serial-to- parallel data conversion member (18) to the second parallel data input/output unit (24) ; and arranged to transmit from the data-receiving, second data processing unit (4) to the data-sending, first data processing unit (2) , a status signal by means of which a data-receive status of the said second data processing unit can be indicated.

5. Data transmission arrangement according to Claim 4, characterized in that it is additionally arranged to transmit, from the first data processing unit (2) to the second data processing unit (4) , electrical voltages with at least two different potentials for supplying power to the members included, on the one hand, in the two interface units ( h , 6 ) , and, on the other hand, in the second data processing unit (2) .

6. Data transmission arrangement according to any one of the preceding claims, characterized in that at least one of the two interface units (6, 8) comprises a current amplifier for -amplifying signals which are to be transmitted, and/or a voltage converter and/or another signal amplifier.

7. Data transmission arrangement according to any one of Claims 2 to 6, characterized in that the said parallel-to-serial data conversion member (12) comprises series register members for sequential output of data which has been input in parallel form, for example a data word.

8. Data transmission arrangement according to any one of Claims 2 to 7, characterized in that the said serial-to-parallel data conversion member (18) comprises a shift register for receiving serial data, for example a data word, a parallel register connected thereto for parallelizing the said data, and a data buffer which is connected to the parallel register and is used for temporary storage of the said parallel data on data output.

9. Data transmission arrangement according to any one of the preceding claims, characterized in that the said first interface unit (6) comprises a programmable control member comprising the said parallel-to-serial data conversion member (12) and the said first control signal transmission member (14) and/or in that the said second interface unit (8) comprises a programmable control member comprising the said serial-to-parallel data conversion member (18) and the said second control signal transmission member (20) ; and a program sequence specially suited for the said data conversion and the said control signal transmission can be executed in the respective programmable control member.

10. Data transmission arrangement according to any one of the preceding claims, characterized in that it comprises a signal transmission member (22) by means of which the two said interface units (6, 8) can be coupled together, and which comprises leads for data signals, control signals and supply voltages.

11. Data transmission arrangement according to any one of the preceding claims, characterized in that the said first interface unit (6) comprises a further serial data input/output unit (17) which is connected to the said parallel-to-serial data conversion member (12) and to the said first control signal transmission member

(14) ; in that the said other serial data input/output unit (17) can be connected to a third interface unit; in that the first interface unit (6) is arranged for data transmission via the said other serial data input/output unit both to a third interface unit which is of the same type as the second interface unit (8) , and to a third interface unit which is of another type already known per se; and in that the first interface unit (6) is arranged to be automatically switched between the two said different types of data transmission, by means of detection members and switching members included in the first interface unit (6) .

12. Data transmission arrangement according to Claim 11, characterized in that the said third serial data input/output unit (17) can be automatically switched between data transmission according to the arrangement which is specified in Claims 1 to 10, and data trans¬ mission to and from a I2C data bus; and in that the third serial data input/output unit (17) comprises members for detecting any connection of a I2C data bus interface unit and activatable members for switching to I2C data transmission which are activated upon connection of a said 12 C data bus interface unit.

13. Information presentation arrangement comprising a data processing unit (2) which is arranged for generating and/or processing information or data which is to be presented, and comprising a data processor (26) , a memory unit (28) connected to the data processor (26) , and a parallel data input/output unit (30) ; and a data presentation arrangement (4) comprising a presentation panel (32) for visual presentation of information, and an input/output unit (34) for inputting and outputting data which is to be presented, control signals and, if appropriate, a supply voltage, and the data processing unit (2) and the data presentation arrangement (4) are coupled together by means of a data transmission arrangement according to any one of Claims 1 to 12.

14. Information presentation arrangement according to Claim 13, characterized in that the data processing unit

(2) is a main unit of a lottery terminal and the data presentation unit (4) is an LCD screen.