WO1996025744A1 - On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same - Google Patents
On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same Download PDFInfo
- Publication number
- WO1996025744A1 WO1996025744A1 PCT/US1996/001756 US9601756W WO9625744A1 WO 1996025744 A1 WO1996025744 A1 WO 1996025744A1 US 9601756 W US9601756 W US 9601756W WO 9625744 A1 WO9625744 A1 WO 9625744A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory cells
- address
- memory
- programming
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
- G11C29/765—Masking faults in memories by using spares or by reconfiguring using address translation or modifications in solid state disks
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96906349A EP0809849B1 (en) | 1995-02-13 | 1996-02-07 | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
JP52502596A JP3764167B2 (en) | 1995-02-13 | 1996-02-07 | On-chip memory redundancy circuit for programmable nonvolatile memory device and programming method thereof |
AT96906349T ATE206241T1 (en) | 1995-02-13 | 1996-02-07 | INTEGRATED MEMORY REDUNDANCY CIRCUIT FOR PROGRAMMABLE FIXED-VALUE MEMORY AND PROGRAMMING METHODS |
DE69615538T DE69615538T2 (en) | 1995-02-13 | 1996-02-07 | INTEGRATED MEMORY REDUNDANCY CIRCUIT FOR PROGRAMMABLE FIXED VALUE STORAGE AND PROGRAMMING PROCESS |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/387,244 US5513144A (en) | 1995-02-13 | 1995-02-13 | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
US08/387,244 | 1995-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1996025744A1 true WO1996025744A1 (en) | 1996-08-22 |
Family
ID=23529081
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/001756 WO1996025744A1 (en) | 1995-02-13 | 1996-02-07 | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
Country Status (8)
Country | Link |
---|---|
US (3) | US5513144A (en) |
EP (1) | EP0809849B1 (en) |
JP (1) | JP3764167B2 (en) |
KR (1) | KR100386132B1 (en) |
AT (1) | ATE206241T1 (en) |
DE (1) | DE69615538T2 (en) |
TW (1) | TW290690B (en) |
WO (1) | WO1996025744A1 (en) |
Families Citing this family (148)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5657332A (en) * | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
US5513144A (en) * | 1995-02-13 | 1996-04-30 | Micron Technology, Inc. | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
US5838620A (en) * | 1995-04-05 | 1998-11-17 | Micron Technology, Inc. | Circuit for cancelling and replacing redundant elements |
EP0798642B1 (en) * | 1996-03-29 | 2001-11-07 | STMicroelectronics S.r.l. | Redundancy management method and architecture, particularly for non-volatile memories |
US5724282A (en) * | 1996-09-06 | 1998-03-03 | Micron Technology, Inc. | System and method for an antifuse bank |
US5768287A (en) | 1996-10-24 | 1998-06-16 | Micron Quantum Devices, Inc. | Apparatus and method for programming multistate memory device |
US5764568A (en) * | 1996-10-24 | 1998-06-09 | Micron Quantum Devices, Inc. | Method for performing analog over-program and under-program detection for a multistate memory cell |
US5771346A (en) | 1996-10-24 | 1998-06-23 | Micron Quantum Devices, Inc. | Apparatus and method for detecting over-programming condition in multistate memory device |
US5732033A (en) | 1996-11-14 | 1998-03-24 | Micron Technology, Inc. | Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing |
US10839321B2 (en) * | 1997-01-06 | 2020-11-17 | Jeffrey Eder | Automated data storage system |
US5912579A (en) * | 1997-02-06 | 1999-06-15 | Zagar; Paul S. | Circuit for cancelling and replacing redundant elements |
US5909049A (en) | 1997-02-11 | 1999-06-01 | Actel Corporation | Antifuse programmed PROM cell |
US5935258A (en) * | 1997-03-04 | 1999-08-10 | Micron Electronics, Inc. | Apparatus for allowing data transfers with a memory having defective storage locations |
US5970022A (en) * | 1997-03-21 | 1999-10-19 | Winbond Electronics Corporation | Semiconductor memory device with reduced read disturbance |
US5910921A (en) * | 1997-04-22 | 1999-06-08 | Micron Technology, Inc. | Self-test of a memory device |
US6172935B1 (en) * | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
US5881003A (en) * | 1997-07-16 | 1999-03-09 | International Business Machines Corporation | Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration |
US5909449A (en) * | 1997-09-08 | 1999-06-01 | Invox Technology | Multibit-per-cell non-volatile memory with error detection and correction |
US6011733A (en) * | 1998-02-26 | 2000-01-04 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus |
US5970013A (en) * | 1998-02-26 | 1999-10-19 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus with broadcast write |
JP2000048567A (en) * | 1998-05-22 | 2000-02-18 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
US6122203A (en) * | 1998-06-29 | 2000-09-19 | Cypress Semiconductor Corp. | Method, architecture and circuit for writing to and reading from a memory during a single cycle |
US5986970A (en) * | 1998-06-29 | 1999-11-16 | Cypress Semiconductor Corp. | Method, architecture and circuit for writing to a memory |
KR100333720B1 (en) * | 1998-06-30 | 2002-06-20 | 박종섭 | A redundancy circuit in ferroelectric memory device |
US6289438B1 (en) * | 1998-07-29 | 2001-09-11 | Kabushiki Kaisha Toshiba | Microprocessor cache redundancy scheme using store buffer |
US6199177B1 (en) * | 1998-08-28 | 2001-03-06 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
US6910152B2 (en) * | 1998-08-28 | 2005-06-21 | Micron Technology, Inc. | Device and method for repairing a semiconductor memory |
JP2000076898A (en) * | 1998-08-31 | 2000-03-14 | Mitsubishi Electric Corp | Semiconductor memory device, inspecting method thereof and manufacture thereof |
US6567302B2 (en) | 1998-12-29 | 2003-05-20 | Micron Technology, Inc. | Method and apparatus for programming multi-state cells in a memory device |
JP4251717B2 (en) * | 1999-06-03 | 2009-04-08 | 富士通マイクロエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
US6438672B1 (en) | 1999-06-03 | 2002-08-20 | Agere Systems Guardian Corp. | Memory aliasing method and apparatus |
US6687814B1 (en) * | 1999-07-12 | 2004-02-03 | Micron Technology, Inc. | Controller with interface attachment |
US6484271B1 (en) | 1999-09-16 | 2002-11-19 | Koninklijke Philips Electronics N.V. | Memory redundancy techniques |
US6574763B1 (en) | 1999-12-28 | 2003-06-03 | International Business Machines Corporation | Method and apparatus for semiconductor integrated circuit testing and burn-in |
JP3893005B2 (en) * | 2000-01-06 | 2007-03-14 | 富士通株式会社 | Nonvolatile semiconductor memory device |
US20020196687A1 (en) * | 2001-06-08 | 2002-12-26 | Sauvageau Anthony J. | Methods and apparatus for analyzing and repairing memory |
JP2003022693A (en) * | 2001-07-09 | 2003-01-24 | Mitsubishi Electric Corp | Semiconductor memory |
US7219271B2 (en) * | 2001-12-14 | 2007-05-15 | Sandisk 3D Llc | Memory device and method for redundancy/self-repair |
US7047465B1 (en) | 2002-02-28 | 2006-05-16 | Xilinx, Inc. | Methods for using defective programmable logic devices by customizing designs based on recorded defects |
EP1357559B1 (en) * | 2002-04-26 | 2006-06-14 | STMicroelectronics S.r.l. | Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device |
EP1365419B1 (en) | 2002-05-21 | 2008-12-31 | STMicroelectronics S.r.l. | Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor |
EP1403879B1 (en) * | 2002-09-30 | 2010-11-03 | STMicroelectronics Srl | Method for replacing failed non-volatile memory cells and corresponding memory device |
US6868022B2 (en) * | 2003-03-28 | 2005-03-15 | Matrix Semiconductor, Inc. | Redundant memory structure using bad bit pointers |
US7000155B2 (en) * | 2003-04-21 | 2006-02-14 | International Business Machines Corporation | Redundancy register architecture for soft-error tolerance and methods of making the same |
US8775112B2 (en) * | 2003-09-15 | 2014-07-08 | Nvidia Corporation | System and method for increasing die yield |
US8732644B1 (en) | 2003-09-15 | 2014-05-20 | Nvidia Corporation | Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits |
US8775997B2 (en) | 2003-09-15 | 2014-07-08 | Nvidia Corporation | System and method for testing and configuring semiconductor functional circuits |
US7173852B2 (en) * | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
US7216277B1 (en) | 2003-11-18 | 2007-05-08 | Xilinx, Inc. | Self-repairing redundancy for memory blocks in programmable logic devices |
US8711161B1 (en) * | 2003-12-18 | 2014-04-29 | Nvidia Corporation | Functional component compensation reconfiguration system and method |
US8723231B1 (en) * | 2004-09-15 | 2014-05-13 | Nvidia Corporation | Semiconductor die micro electro-mechanical switch management system and method |
US8711156B1 (en) | 2004-09-30 | 2014-04-29 | Nvidia Corporation | Method and system for remapping processing elements in a pipeline of a graphics processing unit |
US7424655B1 (en) | 2004-10-01 | 2008-09-09 | Xilinx, Inc. | Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits |
US7284229B1 (en) | 2004-10-01 | 2007-10-16 | Xilinx, Inc. | Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein |
US7412635B1 (en) | 2004-10-01 | 2008-08-12 | Xilinx, Inc. | Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits |
US7251804B1 (en) | 2004-10-01 | 2007-07-31 | Xilinx, Inc. | Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof |
US7395404B2 (en) * | 2004-12-16 | 2008-07-01 | Sandisk Corporation | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array |
US7315916B2 (en) * | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
US7277336B2 (en) * | 2004-12-28 | 2007-10-02 | Sandisk 3D Llc | Method and apparatus for improving yield in semiconductor devices by guaranteeing health of redundancy information |
ITMI20042538A1 (en) * | 2004-12-29 | 2005-03-29 | Atmel Corp | METHOD AND SYSTEM FOR THE REDUCTION OF SOFT-WRITING IN A FLASH MEMORY AT MULTIPLE LEVELS |
WO2006085633A1 (en) * | 2005-02-10 | 2006-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Memory element and semiconductor device |
US8021193B1 (en) * | 2005-04-25 | 2011-09-20 | Nvidia Corporation | Controlled impedance display adapter |
US7793029B1 (en) | 2005-05-17 | 2010-09-07 | Nvidia Corporation | Translation device apparatus for configuring printed circuit board connectors |
US7212454B2 (en) * | 2005-06-22 | 2007-05-01 | Sandisk 3D Llc | Method and apparatus for programming a memory array |
US9092170B1 (en) | 2005-10-18 | 2015-07-28 | Nvidia Corporation | Method and system for implementing fragment operation processing across a graphics bus interconnect |
US8417838B2 (en) * | 2005-12-12 | 2013-04-09 | Nvidia Corporation | System and method for configurable digital communication |
US8412872B1 (en) | 2005-12-12 | 2013-04-02 | Nvidia Corporation | Configurable GPU and method for graphics processing using a configurable GPU |
US20070136640A1 (en) * | 2005-12-14 | 2007-06-14 | Jarrar Anis M | Defect detection and repair in an embedded random access memory |
US7324389B2 (en) * | 2006-03-24 | 2008-01-29 | Sandisk Corporation | Non-volatile memory with redundancy data buffered in remote buffer circuits |
US7567461B2 (en) | 2006-08-18 | 2009-07-28 | Micron Technology, Inc. | Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells |
US7886204B2 (en) * | 2006-09-27 | 2011-02-08 | Sandisk Corporation | Methods of cell population distribution assisted read margining |
US7716538B2 (en) * | 2006-09-27 | 2010-05-11 | Sandisk Corporation | Memory with cell population distribution assisted read margining |
US7477547B2 (en) * | 2007-03-28 | 2009-01-13 | Sandisk Corporation | Flash memory refresh techniques triggered by controlled scrub data reads |
US7573773B2 (en) * | 2007-03-28 | 2009-08-11 | Sandisk Corporation | Flash memory with data refresh triggered by controlled scrub data reads |
US7966518B2 (en) * | 2007-05-15 | 2011-06-21 | Sandisk Corporation | Method for repairing a neighborhood of rows in a memory array using a patch table |
US7958390B2 (en) * | 2007-05-15 | 2011-06-07 | Sandisk Corporation | Memory device for repairing a neighborhood of rows in a memory array using a patch table |
US7853916B1 (en) | 2007-10-11 | 2010-12-14 | Xilinx, Inc. | Methods of using one of a plurality of configuration bitstreams for an integrated circuit |
US7619438B1 (en) | 2007-10-11 | 2009-11-17 | Xilinx, Inc. | Methods of enabling the use of a defective programmable device |
US7810059B1 (en) | 2007-10-11 | 2010-10-05 | Xilinx, Inc. | Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams |
US8724483B2 (en) * | 2007-10-22 | 2014-05-13 | Nvidia Corporation | Loopback configuration for bi-directional interfaces |
US20090119444A1 (en) * | 2007-11-01 | 2009-05-07 | Zerog Wireless, Inc., Delaware Corporation | Multiple write cycle memory using redundant addressing |
TWI360061B (en) | 2007-12-31 | 2012-03-11 | Htc Corp | Electronic device and method for operating applica |
TWI381390B (en) * | 2008-04-10 | 2013-01-01 | Phison Electronics Corp | Bad block determining method for flash memory, storage system and controller thereof |
US8687639B2 (en) * | 2009-06-04 | 2014-04-01 | Nvidia Corporation | Method and system for ordering posted packets and non-posted packets transfer |
US8371094B2 (en) * | 2009-10-23 | 2013-02-12 | Frito-Lay North America, Inc. | Method and apparatus for compacting product |
US9284075B2 (en) | 2009-10-23 | 2016-03-15 | Frito-Lay North America, Inc. | Apparatus for compacting product and high speed bagmaking |
US9176909B2 (en) | 2009-12-11 | 2015-11-03 | Nvidia Corporation | Aggregating unoccupied PCI-e links to provide greater bandwidth |
US9331869B2 (en) * | 2010-03-04 | 2016-05-03 | Nvidia Corporation | Input/output request packet handling techniques by a device specific kernel mode driver |
US9202569B2 (en) | 2011-08-12 | 2015-12-01 | Micron Technology, Inc. | Methods for providing redundancy and apparatuses |
US8687421B2 (en) | 2011-11-21 | 2014-04-01 | Sandisk Technologies Inc. | Scrub techniques for use with dynamic read |
US9330031B2 (en) | 2011-12-09 | 2016-05-03 | Nvidia Corporation | System and method for calibration of serial links using a serial-to-parallel loopback |
US9230689B2 (en) | 2014-03-17 | 2016-01-05 | Sandisk Technologies Inc. | Finding read disturbs on non-volatile memories |
US9552171B2 (en) | 2014-10-29 | 2017-01-24 | Sandisk Technologies Llc | Read scrub with adaptive counter management |
US9978456B2 (en) | 2014-11-17 | 2018-05-22 | Sandisk Technologies Llc | Techniques for reducing read disturb in partially written blocks of non-volatile memory |
US9349479B1 (en) | 2014-11-18 | 2016-05-24 | Sandisk Technologies Inc. | Boundary word line operation in nonvolatile memory |
US9449700B2 (en) | 2015-02-13 | 2016-09-20 | Sandisk Technologies Llc | Boundary word line search and open block read methods with reduced read disturb |
US10163479B2 (en) | 2015-08-14 | 2018-12-25 | Spin Transfer Technologies, Inc. | Method and apparatus for bipolar memory write-verify |
US9653154B2 (en) | 2015-09-21 | 2017-05-16 | Sandisk Technologies Llc | Write abort detection for multi-state memories |
US10818331B2 (en) | 2016-09-27 | 2020-10-27 | Spin Memory, Inc. | Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
US10366774B2 (en) * | 2016-09-27 | 2019-07-30 | Spin Memory, Inc. | Device with dynamic redundancy registers |
US10460781B2 (en) | 2016-09-27 | 2019-10-29 | Spin Memory, Inc. | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank |
US10192602B2 (en) | 2016-09-27 | 2019-01-29 | Spin Transfer Technologies, Inc. | Smart cache design to prevent overflow for a memory device with a dynamic redundancy register |
US10437723B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device |
US10446210B2 (en) | 2016-09-27 | 2019-10-15 | Spin Memory, Inc. | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers |
US10360964B2 (en) | 2016-09-27 | 2019-07-23 | Spin Memory, Inc. | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device |
US10437491B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register |
US10628316B2 (en) | 2016-09-27 | 2020-04-21 | Spin Memory, Inc. | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register |
US10192601B2 (en) | 2016-09-27 | 2019-01-29 | Spin Transfer Technologies, Inc. | Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers |
US10546625B2 (en) | 2016-09-27 | 2020-01-28 | Spin Memory, Inc. | Method of optimizing write voltage based on error buffer occupancy |
EP3367385B1 (en) * | 2017-02-28 | 2020-07-08 | ams AG | Memory arrangement and method for operating a memory arrangement |
US10489245B2 (en) | 2017-10-24 | 2019-11-26 | Spin Memory, Inc. | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them |
US10656994B2 (en) | 2017-10-24 | 2020-05-19 | Spin Memory, Inc. | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
US10529439B2 (en) | 2017-10-24 | 2020-01-07 | Spin Memory, Inc. | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
US10481976B2 (en) | 2017-10-24 | 2019-11-19 | Spin Memory, Inc. | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers |
US10516094B2 (en) | 2017-12-28 | 2019-12-24 | Spin Memory, Inc. | Process for creating dense pillars using multiple exposures for MRAM fabrication |
US10424726B2 (en) | 2017-12-28 | 2019-09-24 | Spin Memory, Inc. | Process for improving photoresist pillar adhesion during MRAM fabrication |
US10891997B2 (en) | 2017-12-28 | 2021-01-12 | Spin Memory, Inc. | Memory array with horizontal source line and a virtual source line |
US10360962B1 (en) | 2017-12-28 | 2019-07-23 | Spin Memory, Inc. | Memory array with individually trimmable sense amplifiers |
US10811594B2 (en) | 2017-12-28 | 2020-10-20 | Spin Memory, Inc. | Process for hard mask development for MRAM pillar formation using photolithography |
US10395712B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Memory array with horizontal source line and sacrificial bitline per virtual source |
US10395711B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Perpendicular source and bit lines for an MRAM array |
US10840439B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) fabrication methods and systems |
US10367139B2 (en) | 2017-12-29 | 2019-07-30 | Spin Memory, Inc. | Methods of manufacturing magnetic tunnel junction devices |
US10546624B2 (en) | 2017-12-29 | 2020-01-28 | Spin Memory, Inc. | Multi-port random access memory |
US10784439B2 (en) | 2017-12-29 | 2020-09-22 | Spin Memory, Inc. | Precessional spin current magnetic tunnel junction devices and methods of manufacture |
US10886330B2 (en) | 2017-12-29 | 2021-01-05 | Spin Memory, Inc. | Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch |
US10424723B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction devices including an optimization layer |
US10840436B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture |
US10438995B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Devices including magnetic tunnel junctions integrated with selectors |
US10438996B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Methods of fabricating magnetic tunnel junctions integrated with selectors |
US10446744B2 (en) | 2018-03-08 | 2019-10-15 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
US11107978B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
US11107974B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic layer |
US10529915B2 (en) | 2018-03-23 | 2020-01-07 | Spin Memory, Inc. | Bit line structures for three-dimensional arrays with magnetic tunnel junction devices including an annular free magnetic layer and a planar reference magnetic layer |
US10784437B2 (en) | 2018-03-23 | 2020-09-22 | Spin Memory, Inc. | Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
US10411185B1 (en) | 2018-05-30 | 2019-09-10 | Spin Memory, Inc. | Process for creating a high density magnetic tunnel junction array test platform |
US10600478B2 (en) | 2018-07-06 | 2020-03-24 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10559338B2 (en) | 2018-07-06 | 2020-02-11 | Spin Memory, Inc. | Multi-bit cell read-out techniques |
US10593396B2 (en) | 2018-07-06 | 2020-03-17 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
US10692569B2 (en) | 2018-07-06 | 2020-06-23 | Spin Memory, Inc. | Read-out techniques for multi-bit cells |
US10990472B2 (en) * | 2018-07-24 | 2021-04-27 | Micron Technology, Inc. | Spare substitution in memory system |
US10650875B2 (en) | 2018-08-21 | 2020-05-12 | Spin Memory, Inc. | System for a wide temperature range nonvolatile memory |
US10699761B2 (en) | 2018-09-18 | 2020-06-30 | Spin Memory, Inc. | Word line decoder memory architecture |
US10971680B2 (en) | 2018-10-01 | 2021-04-06 | Spin Memory, Inc. | Multi terminal device stack formation methods |
US11621293B2 (en) | 2018-10-01 | 2023-04-04 | Integrated Silicon Solution, (Cayman) Inc. | Multi terminal device stack systems and methods |
US11107979B2 (en) | 2018-12-28 | 2021-08-31 | Spin Memory, Inc. | Patterned silicide structures and methods of manufacture |
KR20210157862A (en) * | 2020-06-22 | 2021-12-29 | 에스케이하이닉스 주식회사 | Memory, memory system and operation method of memory system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2682503A1 (en) * | 1991-10-09 | 1993-04-16 | Intel Corp | Process for repairing overerased (overwritten) cells contained in a flash memory |
EP0596198A2 (en) * | 1992-07-10 | 1994-05-11 | Sony Corporation | Flash eprom with erase verification and address scrambling architecture |
US5347489A (en) * | 1992-04-21 | 1994-09-13 | Intel Corporation | Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0283899A (en) * | 1988-09-20 | 1990-03-23 | Fujitsu Ltd | Semiconductor memory |
GB8901093D0 (en) * | 1989-01-18 | 1989-03-15 | Almond Jeffrey W | Attenuated viruses |
DE4118804C2 (en) * | 1990-06-08 | 1996-01-04 | Toshiba Kawasaki Kk | Serial access memory array |
JP2716906B2 (en) * | 1992-03-27 | 1998-02-18 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP3001342B2 (en) * | 1993-02-10 | 2000-01-24 | 日本電気株式会社 | Storage device |
JPH06259987A (en) * | 1993-03-10 | 1994-09-16 | Mitsubishi Electric Corp | Semiconductor memory device |
US5513144A (en) * | 1995-02-13 | 1996-04-30 | Micron Technology, Inc. | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same |
-
1995
- 1995-02-13 US US08/387,244 patent/US5513144A/en not_active Expired - Lifetime
-
1996
- 1996-02-05 US US08/596,528 patent/US5648934A/en not_active Expired - Lifetime
- 1996-02-07 KR KR1019970705538A patent/KR100386132B1/en not_active IP Right Cessation
- 1996-02-07 AT AT96906349T patent/ATE206241T1/en not_active IP Right Cessation
- 1996-02-07 EP EP96906349A patent/EP0809849B1/en not_active Expired - Lifetime
- 1996-02-07 WO PCT/US1996/001756 patent/WO1996025744A1/en active IP Right Grant
- 1996-02-07 DE DE69615538T patent/DE69615538T2/en not_active Expired - Lifetime
- 1996-02-07 JP JP52502596A patent/JP3764167B2/en not_active Expired - Fee Related
- 1996-02-26 TW TW085102180A patent/TW290690B/zh not_active IP Right Cessation
-
1997
- 1997-02-19 US US08/802,376 patent/US5751647A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2682503A1 (en) * | 1991-10-09 | 1993-04-16 | Intel Corp | Process for repairing overerased (overwritten) cells contained in a flash memory |
US5347489A (en) * | 1992-04-21 | 1994-09-13 | Intel Corporation | Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy |
EP0596198A2 (en) * | 1992-07-10 | 1994-05-11 | Sony Corporation | Flash eprom with erase verification and address scrambling architecture |
Also Published As
Publication number | Publication date |
---|---|
US5751647A (en) | 1998-05-12 |
KR19980702143A (en) | 1998-07-15 |
JPH11500561A (en) | 1999-01-12 |
TW290690B (en) | 1996-11-11 |
US5513144A (en) | 1996-04-30 |
JP3764167B2 (en) | 2006-04-05 |
ATE206241T1 (en) | 2001-10-15 |
DE69615538D1 (en) | 2001-10-31 |
EP0809849A1 (en) | 1997-12-03 |
KR100386132B1 (en) | 2003-08-19 |
DE69615538T2 (en) | 2002-05-08 |
EP0809849B1 (en) | 2001-09-26 |
US5648934A (en) | 1997-07-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5513144A (en) | On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same | |
US6553510B1 (en) | Memory device including redundancy routine for correcting random errors | |
US7313022B2 (en) | Non-volatile semiconductor memory | |
JP3941149B2 (en) | Semiconductor nonvolatile memory device | |
US6751122B2 (en) | Nonvolatile semiconductor memory device | |
US7168013B2 (en) | Memory with element redundancy | |
US7599236B2 (en) | In-circuit Vt distribution bit counter for non-volatile memory devices | |
US6469932B2 (en) | Memory with row redundancy | |
US7437625B2 (en) | Memory with element redundancy | |
US6711056B2 (en) | Memory with row redundancy | |
JP2002074980A (en) | Semiconductor integrated circuit device | |
JP4439539B2 (en) | Nonvolatile semiconductor memory and test method thereof | |
JP4387547B2 (en) | Nonvolatile semiconductor memory | |
US7640465B2 (en) | Memory with element redundancy | |
US20180165025A1 (en) | Semiconductor memory device and operation setting method thereof | |
JP2004521430A (en) | Method and circuit arrangement for memory error handling | |
US6108250A (en) | Fast redundancy scheme for high density, high speed memories | |
JPH11260097A (en) | Self test and correction of charge loss error in sector erasable and programmable flash memory | |
JP2000057795A (en) | Non-volatile semiconductor memory | |
TWI752704B (en) | Memory storage apparatus and operating method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 1996 525025 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1019970705538 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1996906349 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1996906349 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1019970705538 Country of ref document: KR |
|
WWG | Wipo information: grant in national office |
Ref document number: 1996906349 Country of ref document: EP |
|
WWG | Wipo information: grant in national office |
Ref document number: 1019970705538 Country of ref document: KR |